mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
-hpc3.cpp: Hooked up INT3 and PIT register accessors. [Ryan Holtz]
-ioc2.cpp: Various changes: [Ryan Holtz] * Hooked up z80scc and 8042kbdc interrupts. * Fixed IRQ-lowering logic to actually clear the MIPS IRQ line. * Hooked up 8042kbdc reset. Gets Gentoo Linux booting (though it hangs during startup), and the IRIX 5.3 installer runs until it fails due to SCSI emulation issues.
This commit is contained in:
mooglyguy
parent
3918180bf4
commit
ae69b747b8
@ -35,6 +35,7 @@ public:
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// construction/destruction
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kbdc8042_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock = 0);
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void reset() { device_reset(); }
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void set_keyboard_type(kbdc8042_type_t keybtype) { m_keybtype = keybtype; }
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auto system_reset_callback() { return m_system_reset_cb.bind(); }
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auto gate_a20_callback() { return m_gate_a20_cb.bind(); }
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@ -16,7 +16,7 @@
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#define LOG_PBUS4 (1 << 4)
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#define LOG_CHAIN (1 << 5)
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#define VERBOSE (0)
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#define VERBOSE (LOG_PBUS_DMA | LOG_PBUS4 | LOG_UNKNOWN | LOG_ETHERNET)
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#include "logmacro.h"
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DEFINE_DEVICE_TYPE(SGI_HPC3, hpc3_device, "hpc3", "SGI HPC3")
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@ -38,9 +38,6 @@ void hpc3_device::device_start()
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save_item(NAME(m_enetr_nbdp));
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save_item(NAME(m_enetr_cbp));
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save_item(NAME(m_unk0));
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save_item(NAME(m_unk1));
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save_item(NAME(m_ic_unk0));
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save_item(NAME(m_scsi0_desc));
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save_item(NAME(m_scsi0_addr));
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save_item(NAME(m_scsi0_flags));
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@ -52,6 +49,7 @@ void hpc3_device::device_start()
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for (uint32_t i = 0; i < 8; i++)
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{
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save_item(NAME(m_pbus_dma[i].m_active), i);
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save_item(NAME(m_pbus_dma[i].m_buf_ptr), i);
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save_item(NAME(m_pbus_dma[i].m_cur_ptr), i);
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save_item(NAME(m_pbus_dma[i].m_desc_ptr), i);
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save_item(NAME(m_pbus_dma[i].m_desc_flags), i);
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@ -69,10 +67,6 @@ void hpc3_device::device_reset()
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m_enetr_nbdp = 0x80000000;
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m_enetr_cbp = 0x80000000;
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m_unk0 = 0;
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m_unk1 = 0;
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m_ic_unk0 = 0;
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m_scsi0_desc = 0;
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m_scsi0_addr = 0;
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m_scsi0_flags = 0;
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@ -84,6 +78,7 @@ void hpc3_device::device_reset()
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{
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m_pbus_dma[i].m_active = 0;
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m_pbus_dma[i].m_cur_ptr = 0;
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m_pbus_dma[i].m_buf_ptr = 0;
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m_pbus_dma[i].m_desc_ptr = 0;
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m_pbus_dma[i].m_desc_flags = 0;
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m_pbus_dma[i].m_next_ptr = 0;
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@ -168,19 +163,19 @@ READ32_MEMBER(hpc3_device::hd_enet_r)
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switch (offset)
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{
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case 0x0004/4:
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LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0DESC Read: %08x (%08x): %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask, m_scsi0_desc);
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LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0 Desc Address Read: %08x & %08x\n", machine().describe_context(), m_scsi0_desc, mem_mask);
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return m_scsi0_desc;
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case 0x1004/4:
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LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0DMACTRL Read: %08x (%08x): %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask, m_scsi0_dma_ctrl);
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LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0 DMA Control Read: %08x & %08x\n", machine().describe_context(), m_scsi0_dma_ctrl, mem_mask);
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return m_scsi0_dma_ctrl;
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case 0x4000/4:
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LOGMASKED(LOG_ETHERNET, "%s: HPC3 ENETR CBP Read: %08x (%08x): %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask, m_enetr_nbdp);
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LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet CBP Read: %08x & %08x\n", machine().describe_context(), m_enetr_nbdp, mem_mask);
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return m_enetr_cbp;
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case 0x4004/4:
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LOGMASKED(LOG_ETHERNET, "%s: HPC3 ENETR NBDP Read: %08x (%08x): %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask, m_enetr_nbdp);
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LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet NBDP Read: %08x & %08x\n", machine().describe_context(), m_enetr_nbdp, mem_mask);
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return m_enetr_nbdp;
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default:
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LOGMASKED(LOG_UNKNOWN, "%s: Unknown HPC3 ENET/HDx Read: %08x (%08x)\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask);
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LOGMASKED(LOG_UNKNOWN, "%s: Unknown HPC3 ENET/HDx Read: %08x & %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask);
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return 0;
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}
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}
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@ -190,23 +185,23 @@ WRITE32_MEMBER(hpc3_device::hd_enet_w)
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switch (offset)
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{
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case 0x0004/4:
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LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0DESC Write: %08x\n", machine().describe_context(), data);
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LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0 Desc Address Write: %08x\n", machine().describe_context(), data);
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m_scsi0_desc = data;
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break;
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case 0x1004/4:
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LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0DMACTRL Write: %08x\n", machine().describe_context(), data);
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LOGMASKED(LOG_SCSI, "%s: HPC3 SCSI0 DMA Control Write: %08x\n", machine().describe_context(), data);
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m_scsi0_dma_ctrl = data;
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break;
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case 0x4000/4:
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LOGMASKED(LOG_ETHERNET, "%s: HPC3 ENETR CBP Write: %08x\n", machine().describe_context(), data);
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LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet CBP Write: %08x\n", machine().describe_context(), data);
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m_enetr_cbp = data;
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break;
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case 0x4004/4:
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LOGMASKED(LOG_ETHERNET, "%s: HPC3 ENETR NBDP Write: %08x\n", machine().describe_context(), data);
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LOGMASKED(LOG_ETHERNET, "%s: HPC3 Ethernet NBDP Write: %08x\n", machine().describe_context(), data);
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m_enetr_nbdp = data;
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break;
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default:
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LOGMASKED(LOG_UNKNOWN, "%s: Unknown HPC3 ENET/HDx write: %08x (%08x): %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), mem_mask, data);
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LOGMASKED(LOG_UNKNOWN, "%s: Unknown HPC3 ENET/HDx write: %08x = %08x & %08x\n", machine().describe_context(), 0x1fb90000 + (offset << 2), data, mem_mask);
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break;
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}
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}
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@ -275,21 +270,58 @@ template DECLARE_WRITE32_MEMBER(hpc3_device::hd_w<1>);
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READ32_MEMBER(hpc3_device::pbus4_r)
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{
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uint32_t ret = 0;
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switch (offset)
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{
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case 0x0000/4:
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ret = m_ioc2->get_local0_int_status();
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local0 Interrupt Status Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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case 0x0004/4:
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PBUS4 Unknown 0 Read: (%08x): %08x\n", machine().describe_context(), mem_mask, m_unk0);
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return m_unk0;
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ret = m_ioc2->get_local0_int_mask();
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local0 Interrupt Mask Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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case 0x0008/4:
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ret = m_ioc2->get_local1_int_status();
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local1 Interrupt Status Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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case 0x000c/4:
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LOGMASKED(LOG_PBUS4, "%s: Interrupt Controller(?) Read: (%08x): %08x\n", machine().describe_context(), mem_mask, m_ic_unk0);
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return m_ic_unk0;
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ret = m_ioc2->get_local1_int_mask();
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local1 Interrupt Mask Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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case 0x0010/4:
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ret = m_ioc2->get_map_int_status();
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mappable Interrupt Status: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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case 0x0014/4:
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PBUS4 Unknown 1 Read: (%08x): %08x\n", machine().describe_context(), mem_mask, m_unk1);
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return m_unk1;
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ret = m_ioc2->get_map0_int_mask();
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 0 Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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case 0x0018/4:
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ret = m_ioc2->get_map1_int_mask();
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 1 Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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case 0x0030/4:
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ret = m_ioc2->get_pit_reg(0);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 0 Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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case 0x0034/4:
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ret = m_ioc2->get_pit_reg(1);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 1 Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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case 0x0038/4:
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ret = m_ioc2->get_pit_reg(2);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 2 Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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case 0x003c/4:
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ret = m_ioc2->get_pit_reg(3);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Control Read: %08x & %08x\n", machine().describe_context(), ret, mem_mask);
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break;
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default:
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LOGMASKED(LOG_PBUS4 | LOG_UNKNOWN, "%s: Unknown HPC3 PBUS4 Read: %08x (%08x)\n", machine().describe_context(), 0x1fbd9000 + (offset << 2), mem_mask);
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return 0;
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break;
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}
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return ret;
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}
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WRITE32_MEMBER(hpc3_device::pbus4_w)
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@ -297,16 +329,40 @@ WRITE32_MEMBER(hpc3_device::pbus4_w)
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switch (offset)
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{
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case 0x0004/4:
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PBUS4 Unknown 0 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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m_unk0 = data;
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m_ioc2->set_local0_int_mask(data);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local0 Interrupt Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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break;
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case 0x000c/4:
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LOGMASKED(LOG_PBUS4, "%s: Interrupt Controller(?) Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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m_ic_unk0 = data;
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m_ioc2->set_local1_int_mask(data);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Local1 Interrupt Mask Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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break;
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case 0x0014/4:
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PBUS4 Unknown 1 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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m_unk1 = data;
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m_ioc2->set_map0_int_mask(data);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 0 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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break;
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case 0x0018/4:
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m_ioc2->set_map1_int_mask(data);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Mapped Interrupt 1 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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break;
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case 0x0020/4:
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m_ioc2->set_timer_int_clear(data);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 INT3 Timer Interrupt Clear Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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break;
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case 0x0030/4:
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m_ioc2->set_pit_reg(0, (uint8_t)data);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 0 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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break;
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case 0x0034/4:
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m_ioc2->set_pit_reg(1, (uint8_t)data);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 1 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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break;
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case 0x0038/4:
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m_ioc2->set_pit_reg(2, (uint8_t)data);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Counter 2 Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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break;
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case 0x003c/4:
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m_ioc2->set_pit_reg(3, (uint8_t)data);
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LOGMASKED(LOG_PBUS4, "%s: HPC3 PIT Control Write: %08x & %08x\n", machine().describe_context(), data, mem_mask);
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break;
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default:
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LOGMASKED(LOG_PBUS4 | LOG_UNKNOWN, "%s: Unknown HPC3 PBUS4 Write: %08x = %08x & %08x\n", machine().describe_context(), 0x1fbd9000 + (offset << 2), data, mem_mask);
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@ -318,7 +374,28 @@ READ32_MEMBER(hpc3_device::pbusdma_r)
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{
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uint32_t channel = offset / (0x2000/4);
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LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Read: %08x & %08x\n", machine().describe_context(), channel, 0x1fb80000 + offset*4, mem_mask);
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return 0;
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pbus_dma_t &dma = m_pbus_dma[channel];
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uint32_t ret = 0;
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switch (offset & 0x07ff)
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{
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case 0x0000/4:
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ret = dma.m_buf_ptr;
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LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Buffer Pointer Read: %08x & %08x\n", machine().describe_context(), channel, ret, mem_mask);
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break;
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case 0x0004/4:
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ret = dma.m_desc_ptr;
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LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Descriptor Pointer Read: %08x & %08x\n", machine().describe_context(), channel, ret, mem_mask);
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break;
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case 0x1000/4:
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ret = (dma.m_timer->remaining() != attotime::never) ? 2 : 0;
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LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Control Read: %08x & %08x\n", machine().describe_context(), channel, ret, mem_mask);
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break;
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default:
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LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Unknown Read: %08x & %08x\n", machine().describe_context(), channel, 0x1fb80000 + (offset << 2), mem_mask);
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break;
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}
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return ret;
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}
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WRITE32_MEMBER(hpc3_device::pbusdma_w)
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@ -330,6 +407,7 @@ WRITE32_MEMBER(hpc3_device::pbusdma_w)
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{
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case 0x0000/4:
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LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Buffer Pointer Write: %08x\n", machine().describe_context(), channel, data);
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dma.m_buf_ptr = data;
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break;
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case 0x0004/4:
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LOGMASKED(LOG_PBUS_DMA, "%s: PBUS DMA Channel %d Descriptor Pointer Write: %08x\n", machine().describe_context(), channel, data);
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@ -76,6 +76,7 @@ protected:
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struct pbus_dma_t
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{
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bool m_active;
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uint32_t m_buf_ptr;
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uint32_t m_cur_ptr;
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uint32_t m_desc_ptr;
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uint32_t m_desc_flags;
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@ -126,9 +127,6 @@ protected:
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uint32_t m_enetr_nbdp;
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uint32_t m_enetr_cbp;
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uint32_t m_unk0;
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uint32_t m_unk1;
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uint32_t m_ic_unk0;
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uint32_t m_scsi0_desc;
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uint32_t m_scsi0_addr;
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uint32_t m_scsi0_flags;
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@ -75,6 +75,7 @@ void ioc2_device::device_add_mconfig(machine_config &config)
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m_scc->out_txdb_callback().set(RS232B_TAG, FUNC(rs232_port_device::write_txd));
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m_scc->out_dtrb_callback().set(RS232B_TAG, FUNC(rs232_port_device::write_dtr));
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m_scc->out_rtsb_callback().set(RS232B_TAG, FUNC(rs232_port_device::write_rts));
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m_scc->out_int_callback().set(FUNC(ioc2_device::duart_int_w));
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rs232_port_device &rs232a(RS232_PORT(config, RS232A_TAG, default_rs232_devices, nullptr));
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rs232a.cts_handler().set(m_scc, FUNC(scc85230_device::ctsa_w));
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@ -91,6 +92,7 @@ void ioc2_device::device_add_mconfig(machine_config &config)
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KBDC8042(config, m_kbdc);
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m_kbdc->set_keyboard_type(kbdc8042_device::KBDC8042_PS2);
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m_kbdc->system_reset_callback().set_inputline(m_maincpu, INPUT_LINE_RESET);
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m_kbdc->input_buffer_full_callback().set(FUNC(ioc2_device::kbdc_int_w));
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PIT8254(config, m_pit, 0);
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m_pit->set_clk<0>(1000000);
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@ -162,7 +164,7 @@ void ioc2_device::device_reset()
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m_gen_ctrl_select_reg = 0;
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m_gen_ctrl_reg = 0;
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m_front_panel_reg = FRONT_PANEL_POWER_STATE;
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m_front_panel_reg = FRONT_PANEL_VOL_UP_HOLD | FRONT_PANEL_VOL_DOWN_HOLD | FRONT_PANEL_POWER_STATE;
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m_read_reg = 0;
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m_dma_sel = 0;
|
||||
@ -183,23 +185,25 @@ void ioc2_device::device_reset()
|
||||
void ioc2_device::raise_local0_irq(uint8_t source_mask)
|
||||
{
|
||||
m_int3_local0_status_reg |= source_mask;
|
||||
m_maincpu->set_input_line(MIPS3_IRQ0, (m_int3_local0_mask_reg & m_int3_local0_status_reg) != 0 ? ASSERT_LINE : CLEAR_LINE);
|
||||
m_maincpu->set_input_line(MIPS3_IRQ0, (m_int3_local0_mask_reg & m_int3_local0_status_reg) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
void ioc2_device::lower_local0_irq(uint8_t source_mask)
|
||||
{
|
||||
m_int3_local0_status_reg &= ~source_mask;
|
||||
m_maincpu->set_input_line(MIPS3_IRQ0, (m_int3_local0_mask_reg & m_int3_local0_status_reg) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
void ioc2_device::raise_local1_irq(uint8_t source_mask)
|
||||
{
|
||||
m_int3_local1_status_reg |= source_mask;
|
||||
m_maincpu->set_input_line(MIPS3_IRQ1, (m_int3_local1_mask_reg & m_int3_local1_status_reg) != 0 ? ASSERT_LINE : CLEAR_LINE);
|
||||
m_maincpu->set_input_line(MIPS3_IRQ1, (m_int3_local1_mask_reg & m_int3_local1_status_reg) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
void ioc2_device::lower_local1_irq(uint8_t source_mask)
|
||||
{
|
||||
m_int3_local1_status_reg &= ~source_mask;
|
||||
m_maincpu->set_input_line(MIPS3_IRQ1, (m_int3_local1_mask_reg & m_int3_local1_status_reg) ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(ioc2_device::timer0_int)
|
||||
@ -212,6 +216,34 @@ WRITE_LINE_MEMBER(ioc2_device::timer1_int)
|
||||
m_maincpu->set_input_line(MIPS3_IRQ3, ASSERT_LINE);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(ioc2_device::kbdc_int_w)
|
||||
{
|
||||
set_mappable_int(0x10, state);
|
||||
}
|
||||
|
||||
WRITE_LINE_MEMBER(ioc2_device::duart_int_w)
|
||||
{
|
||||
set_mappable_int(0x20, state);
|
||||
}
|
||||
|
||||
void ioc2_device::set_mappable_int(uint8_t mask, bool state)
|
||||
{
|
||||
if (state)
|
||||
m_int3_map_status_reg |= mask;
|
||||
else
|
||||
m_int3_map_status_reg &= ~mask;
|
||||
|
||||
if (m_int3_map_mask0_reg & m_int3_map_status_reg)
|
||||
raise_local0_irq(INT3_LOCAL0_MAPPABLE0);
|
||||
else
|
||||
lower_local0_irq(INT3_LOCAL0_MAPPABLE0);
|
||||
|
||||
if (m_int3_map_mask1_reg & m_int3_map_status_reg)
|
||||
raise_local1_irq(INT3_LOCAL1_MAPPABLE1);
|
||||
else
|
||||
lower_local1_irq(INT3_LOCAL1_MAPPABLE1);
|
||||
}
|
||||
|
||||
READ32_MEMBER(ioc2_device::read)
|
||||
{
|
||||
switch (offset)
|
||||
@ -400,25 +432,25 @@ READ32_MEMBER(ioc2_device::read)
|
||||
|
||||
case TIMER_COUNT0_REG:
|
||||
{
|
||||
const uint8_t data = m_pit->read(offset - TIMER_COUNT0_REG);
|
||||
const uint8_t data = m_pit->read(0);
|
||||
LOGMASKED(LOG_PIT, "%s: Read Timer Count0 Register: %02x\n", machine().describe_context(), data);
|
||||
return data;
|
||||
}
|
||||
case TIMER_COUNT1_REG:
|
||||
{
|
||||
const uint8_t data = m_pit->read(offset - TIMER_COUNT0_REG);
|
||||
const uint8_t data = m_pit->read(1);
|
||||
LOGMASKED(LOG_PIT, "%s: Read Timer Count1 Register: %02x\n", machine().describe_context(), data);
|
||||
return data;
|
||||
}
|
||||
case TIMER_COUNT2_REG:
|
||||
{
|
||||
const uint8_t data = m_pit->read(offset - TIMER_COUNT0_REG);
|
||||
const uint8_t data = m_pit->read(2);
|
||||
LOGMASKED(LOG_PIT, "%s: Read Timer Count2 Register: %02x\n", machine().describe_context(), data);
|
||||
return data;
|
||||
}
|
||||
case TIMER_CONTROL_REG:
|
||||
{
|
||||
const uint8_t data = m_pit->read(offset - TIMER_COUNT0_REG);
|
||||
const uint8_t data = m_pit->read(3);
|
||||
LOGMASKED(LOG_PIT, "%s: Read Timer Control Register: %02x\n", machine().describe_context(), data);
|
||||
return data;
|
||||
}
|
||||
@ -433,15 +465,15 @@ WRITE32_MEMBER( ioc2_device::write )
|
||||
{
|
||||
case PI1_DATA_REG:
|
||||
LOGMASKED(LOG_PI1, "%s: Write PI1 Data Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
m_pi1->write(space, offset, data & 0xff, 0xff);
|
||||
m_pi1->write(space, offset, (uint8_t)data);
|
||||
return;
|
||||
case PI1_CTRL_REG:
|
||||
LOGMASKED(LOG_PI1, "%s: Write PI1 Control Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
m_pi1->write(space, offset, data & 0xff, 0xff);
|
||||
m_pi1->write(space, offset, (uint8_t)data);
|
||||
return;
|
||||
case PI1_STATUS_REG:
|
||||
LOGMASKED(LOG_PI1, "%s: Write PI1 Status Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
m_pi1->write(space, offset, data & 0xff, 0xff);
|
||||
m_pi1->write(space, offset, (uint8_t)data);
|
||||
return;
|
||||
|
||||
case PI1_DMA_CTRL_REG:
|
||||
@ -495,6 +527,8 @@ WRITE32_MEMBER( ioc2_device::write )
|
||||
case PANEL_REG:
|
||||
LOGMASKED(LOG_PANEL, "%s: Write Front Panel Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
m_front_panel_reg &= ~(data & (FRONT_PANEL_VOL_UP_INT | FRONT_PANEL_VOL_DOWN_INT | FRONT_PANEL_POWER_BUTTON_INT));
|
||||
if (!(m_front_panel_reg & FRONT_PANEL_INT_MASK))
|
||||
lower_local1_irq(INT3_LOCAL1_PANEL);
|
||||
return;
|
||||
|
||||
case DMA_SEL_REG:
|
||||
@ -541,43 +575,27 @@ WRITE32_MEMBER( ioc2_device::write )
|
||||
case INT3_LOCAL0_MASK_REG:
|
||||
{
|
||||
LOGMASKED(LOG_INT3, "%s: Write Interrupt Local0 Mask Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
uint8_t old = m_int3_local0_mask_reg;
|
||||
m_int3_local0_mask_reg = data;
|
||||
bool old_line = (old & m_int3_local0_status_reg) != 0;
|
||||
bool new_line = (m_int3_local0_mask_reg & m_int3_local0_status_reg) != 0;
|
||||
if (old_line != new_line)
|
||||
{
|
||||
const uint32_t int_bits = (m_int3_local1_mask_reg & m_int3_local1_status_reg) | (m_int3_local0_mask_reg & m_int3_local0_status_reg);
|
||||
m_maincpu->set_input_line(MIPS3_IRQ0, int_bits != 0 ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
set_local0_int_mask(data);
|
||||
return;
|
||||
}
|
||||
|
||||
case INT3_LOCAL1_MASK_REG:
|
||||
{
|
||||
LOGMASKED(LOG_INT3, "%s: Write Interrupt Local1 Mask Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
uint8_t old = m_int3_local1_mask_reg;
|
||||
m_int3_local1_mask_reg = data;
|
||||
bool old_line = (old & m_int3_local1_status_reg) != 0;
|
||||
bool new_line = (m_int3_local1_mask_reg & m_int3_local1_status_reg) != 0;
|
||||
if (old_line != new_line)
|
||||
{
|
||||
const uint32_t int_bits = (m_int3_local1_mask_reg & m_int3_local1_status_reg) | (m_int3_local0_mask_reg & m_int3_local0_status_reg);
|
||||
m_maincpu->set_input_line(MIPS3_IRQ0, int_bits != 0 ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
set_local1_int_mask(data);
|
||||
return;
|
||||
}
|
||||
|
||||
case INT3_MAP_MASK0_REG:
|
||||
// TODO: Implement mappable interrupts
|
||||
LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Mask0 Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
m_int3_map_mask0_reg = data;
|
||||
set_map0_int_mask(data);
|
||||
return;
|
||||
|
||||
case INT3_MAP_MASK1_REG:
|
||||
// TODO: Implement mappable interrupts
|
||||
LOGMASKED(LOG_INT3, "%s: Write Interrupt Map Mask1 Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
m_int3_map_mask1_reg = data;
|
||||
set_map1_int_mask(data);
|
||||
return;
|
||||
|
||||
case INT3_MAP_POLARITY_REG:
|
||||
@ -589,44 +607,92 @@ WRITE32_MEMBER( ioc2_device::write )
|
||||
case INT3_TIMER_CLEAR_REG:
|
||||
{
|
||||
LOGMASKED(LOG_INT3, "%s: Write Interrupt Timer Clear Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
if (BIT(data, 0))
|
||||
m_maincpu->set_input_line(MIPS3_IRQ2, CLEAR_LINE);
|
||||
if (BIT(data, 1))
|
||||
m_maincpu->set_input_line(MIPS3_IRQ3, CLEAR_LINE);
|
||||
set_timer_int_clear(data);
|
||||
return;
|
||||
}
|
||||
|
||||
case TIMER_COUNT0_REG:
|
||||
LOGMASKED(LOG_PIT, "%s: Write Timer Count0 Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
m_pit->write(offset - TIMER_COUNT0_REG, data & 0xff);
|
||||
m_pit->write(0, (uint8_t)data);
|
||||
return;
|
||||
case TIMER_COUNT1_REG:
|
||||
LOGMASKED(LOG_PIT, "%s: Write Timer Count1 Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
m_pit->write(offset - TIMER_COUNT0_REG, data & 0xff);
|
||||
m_pit->write(1, (uint8_t)data);
|
||||
return;
|
||||
case TIMER_COUNT2_REG:
|
||||
LOGMASKED(LOG_PIT, "%s: Write Timer Count2 Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
m_pit->write(offset - TIMER_COUNT0_REG, data & 0xff);
|
||||
m_pit->write(2, (uint8_t)data);
|
||||
return;
|
||||
case TIMER_CONTROL_REG:
|
||||
LOGMASKED(LOG_PIT, "%s: Write Timer Control Register: %02x\n", machine().describe_context(), (uint8_t)data);
|
||||
m_pit->write(offset - TIMER_COUNT0_REG, data & 0xff);
|
||||
m_pit->write(3, (uint8_t)data);
|
||||
return;
|
||||
}
|
||||
}
|
||||
|
||||
void ioc2_device::set_local0_int_mask(uint32_t data)
|
||||
{
|
||||
uint8_t old = m_int3_local0_mask_reg;
|
||||
m_int3_local0_mask_reg = (uint8_t)data;
|
||||
bool old_line = (old & m_int3_local0_status_reg) != 0;
|
||||
bool new_line = (m_int3_local0_mask_reg & m_int3_local0_status_reg) != 0;
|
||||
if (old_line != new_line)
|
||||
{
|
||||
const uint32_t int_bits = (m_int3_local1_mask_reg & m_int3_local1_status_reg) | (m_int3_local0_mask_reg & m_int3_local0_status_reg);
|
||||
m_maincpu->set_input_line(MIPS3_IRQ0, int_bits != 0 ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
void ioc2_device::set_local1_int_mask(uint32_t data)
|
||||
{
|
||||
uint8_t old = m_int3_local1_mask_reg;
|
||||
m_int3_local1_mask_reg = (uint8_t)data;
|
||||
bool old_line = (old & m_int3_local1_status_reg) != 0;
|
||||
bool new_line = (m_int3_local1_mask_reg & m_int3_local1_status_reg) != 0;
|
||||
if (old_line != new_line)
|
||||
{
|
||||
const uint32_t int_bits = (m_int3_local1_mask_reg & m_int3_local1_status_reg) | (m_int3_local0_mask_reg & m_int3_local0_status_reg);
|
||||
m_maincpu->set_input_line(MIPS3_IRQ0, int_bits != 0 ? ASSERT_LINE : CLEAR_LINE);
|
||||
}
|
||||
}
|
||||
|
||||
void ioc2_device::set_map0_int_mask(uint32_t data)
|
||||
{
|
||||
m_int3_map_mask0_reg = (uint8_t)data;
|
||||
}
|
||||
|
||||
void ioc2_device::set_map1_int_mask(uint32_t data)
|
||||
{
|
||||
m_int3_map_mask1_reg = (uint8_t)data;
|
||||
}
|
||||
|
||||
void ioc2_device::set_timer_int_clear(uint32_t data)
|
||||
{
|
||||
if (BIT(data, 0))
|
||||
m_maincpu->set_input_line(MIPS3_IRQ2, CLEAR_LINE);
|
||||
if (BIT(data, 1))
|
||||
m_maincpu->set_input_line(MIPS3_IRQ3, CLEAR_LINE);
|
||||
}
|
||||
|
||||
void ioc2_device::handle_reset_reg_write(uint8_t data)
|
||||
{
|
||||
// guinness/fullhouse-specific implementations can handle bit 3 being used for ISDN reset on Indy only and bit 2 for EISA reset on Indigo 2 only, but for now we do nothing with it
|
||||
m_reset_reg = data;
|
||||
if (BIT(data, 1))
|
||||
{
|
||||
m_kbdc->reset();
|
||||
}
|
||||
m_reset_reg = 0;
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER( ioc2_device::power_button )
|
||||
{
|
||||
if (!newval)
|
||||
{
|
||||
m_front_panel_reg |= FRONT_PANEL_POWER_BUTTON_INT;
|
||||
}
|
||||
else
|
||||
m_front_panel_reg &= ~FRONT_PANEL_POWER_BUTTON_INT;
|
||||
|
||||
if (m_front_panel_reg & FRONT_PANEL_INT_MASK)
|
||||
raise_local1_irq(INT3_LOCAL1_PANEL);
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER( ioc2_device::volume_up )
|
||||
@ -634,12 +700,15 @@ INPUT_CHANGED_MEMBER( ioc2_device::volume_up )
|
||||
if (!newval)
|
||||
{
|
||||
m_front_panel_reg |= FRONT_PANEL_VOL_UP_INT;
|
||||
m_front_panel_reg |= FRONT_PANEL_VOL_UP_HOLD;
|
||||
m_front_panel_reg &= ~FRONT_PANEL_VOL_UP_HOLD;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_front_panel_reg &= ~FRONT_PANEL_VOL_UP_HOLD;
|
||||
m_front_panel_reg |= FRONT_PANEL_VOL_UP_HOLD;
|
||||
}
|
||||
|
||||
if (m_front_panel_reg & FRONT_PANEL_INT_MASK)
|
||||
raise_local1_irq(INT3_LOCAL1_PANEL);
|
||||
}
|
||||
|
||||
INPUT_CHANGED_MEMBER( ioc2_device::volume_down )
|
||||
@ -647,10 +716,13 @@ INPUT_CHANGED_MEMBER( ioc2_device::volume_down )
|
||||
if (!newval)
|
||||
{
|
||||
m_front_panel_reg |= FRONT_PANEL_VOL_DOWN_INT;
|
||||
m_front_panel_reg |= FRONT_PANEL_VOL_DOWN_HOLD;
|
||||
m_front_panel_reg &= ~FRONT_PANEL_VOL_DOWN_HOLD;
|
||||
}
|
||||
else
|
||||
{
|
||||
m_front_panel_reg &= ~FRONT_PANEL_VOL_DOWN_HOLD;
|
||||
m_front_panel_reg |= FRONT_PANEL_VOL_DOWN_HOLD;
|
||||
}
|
||||
|
||||
if (m_front_panel_reg & FRONT_PANEL_INT_MASK)
|
||||
raise_local1_irq(INT3_LOCAL1_PANEL);
|
||||
}
|
||||
|
||||
@ -59,6 +59,23 @@ public:
|
||||
INT3_LOCAL1_RETRACE = 0x80,
|
||||
};
|
||||
|
||||
uint32_t get_local0_int_status() const { return m_int3_local0_status_reg; }
|
||||
uint32_t get_local0_int_mask() const { return m_int3_local0_mask_reg; }
|
||||
uint32_t get_local1_int_status() const { return m_int3_local1_status_reg; }
|
||||
uint32_t get_local1_int_mask() const { return m_int3_local1_mask_reg; }
|
||||
uint32_t get_map_int_status() const { return m_int3_map_status_reg; }
|
||||
uint32_t get_map0_int_mask() const { return m_int3_map_mask0_reg; }
|
||||
uint32_t get_map1_int_mask() const { return m_int3_map_mask1_reg; }
|
||||
|
||||
void set_local0_int_mask(const uint32_t data);
|
||||
void set_local1_int_mask(const uint32_t data);
|
||||
void set_map0_int_mask(const uint32_t data);
|
||||
void set_map1_int_mask(const uint32_t data);
|
||||
void set_timer_int_clear(const uint32_t data);
|
||||
|
||||
uint8_t get_pit_reg(uint32_t offset) { return m_pit->read(offset); }
|
||||
void set_pit_reg(uint32_t offset, uint8_t data) { return m_pit->write(offset, data); }
|
||||
|
||||
protected:
|
||||
ioc2_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
@ -69,6 +86,10 @@ protected:
|
||||
|
||||
DECLARE_WRITE_LINE_MEMBER(timer0_int);
|
||||
DECLARE_WRITE_LINE_MEMBER(timer1_int);
|
||||
DECLARE_WRITE_LINE_MEMBER(kbdc_int_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(duart_int_w);
|
||||
|
||||
void set_mappable_int(uint8_t mask, bool state);
|
||||
|
||||
enum
|
||||
{
|
||||
@ -126,6 +147,10 @@ protected:
|
||||
FRONT_PANEL_VOL_DOWN_HOLD = 0x20,
|
||||
FRONT_PANEL_VOL_UP_INT = 0x40,
|
||||
FRONT_PANEL_VOL_UP_HOLD = 0x80,
|
||||
|
||||
FRONT_PANEL_INT_MASK = FRONT_PANEL_POWER_BUTTON_INT |
|
||||
FRONT_PANEL_VOL_DOWN_INT |
|
||||
FRONT_PANEL_VOL_UP_INT
|
||||
};
|
||||
|
||||
enum
|
||||
|
||||
@ -84,6 +84,10 @@ void sgi_mc_device::device_start()
|
||||
{
|
||||
m_sys_id = 0x11; // rev. B MC, EISA bus present
|
||||
}
|
||||
else
|
||||
{
|
||||
m_sys_id = 0x01; // rev. B MC, no EISA bus
|
||||
}
|
||||
|
||||
m_rpss_timer = timer_alloc(TIMER_RPSS);
|
||||
m_rpss_timer->adjust(attotime::never);
|
||||
|
||||
@ -37,6 +37,7 @@
|
||||
#define LOG_XMAP1 (1 << 5)
|
||||
#define LOG_REX3 (1 << 6)
|
||||
#define LOG_COMMANDS (1 << 7)
|
||||
#define LOG_ALL (LOG_UNKNOWN | LOG_VC2 | LOG_CMAP0 | LOG_CMAP1 | LOG_XMAP0 | LOG_XMAP1 | LOG_REX3)
|
||||
|
||||
#define VERBOSE (0)
|
||||
#include "logmacro.h"
|
||||
|
||||
Loading…
Reference in New Issue
Block a user