(MESS) amstrad: Allowed vpos counter to count past the active display. This allows raster interrupts to be set on a non-visible scanline. [Barry Rodewald]
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@ -953,8 +953,7 @@ WRITE_LINE_MEMBER(amstrad_state::amstrad_plus_hsync_changed)
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}
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// CPC+/GX4000 DMA channels
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amstrad_plus_handle_dma(); // a DMA command is handled at the leading edge of HSYNC (every 64us)
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if(m_asic.de_start != 0)
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m_asic.vpos++;
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m_asic.vpos++;
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}
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}
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m_gate_array.hsync = state ? 1 : 0;
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@ -972,7 +971,6 @@ WRITE_LINE_MEMBER(amstrad_state::amstrad_vsync_changed)
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/* Start of new frame */
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m_gate_array.y = -1;
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m_asic.vpos = 1;
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m_asic.de_start = 0;
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}
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@ -994,7 +992,6 @@ WRITE_LINE_MEMBER(amstrad_state::amstrad_plus_vsync_changed)
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/* Start of new frame */
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m_gate_array.y = -1;
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m_asic.vpos = 1;
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m_asic.de_start = 0;
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}
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@ -1014,9 +1011,12 @@ WRITE_LINE_MEMBER(amstrad_state::amstrad_de_changed)
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/* DE became active, store the starting MA and RA signals */
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mc6845_device *mc6845 = m_crtc;
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if(m_asic.de_start == 0)
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m_asic.vpos = 1;
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m_gate_array.ma = mc6845->get_ma();
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m_gate_array.ra = mc6845->get_ra();
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logerror("y = %d; ma = %02x; ra = %02x, address = %04x\n", m_gate_array.y, m_gate_array.ma, m_gate_array.ra, ( ( m_gate_array.ma & 0x3000 ) << 2 ) | ( ( m_gate_array.ra & 0x07 ) << 11 ) | ( ( m_gate_array.ma & 0x3ff ) << 1 ) );
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//logerror("y = %d; ma = %02x; ra = %02x, address = %04x\n", m_gate_array.y, m_gate_array.ma, m_gate_array.ra, ( ( m_gate_array.ma & 0x3000 ) << 2 ) | ( ( m_gate_array.ra & 0x07 ) << 11 ) | ( ( m_gate_array.ma & 0x3ff ) << 1 ) );
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amstrad_gate_array_get_video_data();
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m_asic.de_start = 1;
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}
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@ -1035,6 +1035,8 @@ WRITE_LINE_MEMBER(amstrad_state::amstrad_plus_de_changed)
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m_gate_array.ma = m_crtc->get_ma();
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m_gate_array.ra = m_crtc->get_ra();
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m_asic.h_start = m_gate_array.line_ticks;
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if(m_asic.de_start == 0)
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m_asic.vpos = 1;
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m_asic.de_start = 1;
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/* Start of screen */
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@ -1426,7 +1428,7 @@ WRITE8_MEMBER(amstrad_state::amstrad_plus_asic_6000_w)
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}
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if(offset == 0x0800) // Programmable raster interrupt
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{
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// logerror("ASIC: Wrote %02x to PRI\n",data);
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// logerror("ASIC: Wrote %02x to PRI\n",data);
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m_asic.pri = data;
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}
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if(offset >= 0x0801 && offset <= 0x0803) // Split screen registers
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@ -2570,7 +2572,7 @@ READ8_MEMBER(amstrad_state::amstrad_ppi_portb_r)
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data |= 0x02;
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}
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logerror("amstrad_ppi_portb_r\n");
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//logerror("amstrad_ppi_portb_r\n");
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/* Schedule a write to PC2 */
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timer_set(attotime::zero, TIMER_PC2_LOW);
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