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(nw) Updated rom naming/mapping and changed ram instantiation.

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This commit is contained in:
Ted Green 2016-05-24 08:33:43 -06:00
parent f5179f7ec8
commit ae838d3b6a
5 changed files with 62 additions and 52 deletions
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4
src/devices/cpu/mips/mips3drc.cpp
View File

@ -184,7 +184,9 @@ void mips3_device::clear_fastram(UINT32 select_start)
m_fastram[i].readonly = false;
m_fastram[i].base = nullptr;
}
m_fastram_select=select_start;
m_fastram_select=select_start;
// Set cache to dirty so that re-mapping occurs
m_cache_dirty = TRUE;
}
/*-------------------------------------------------

86
src/devices/machine/vrc4373.cpp
View File

@ -32,8 +32,8 @@ vrc4373_device::vrc4373_device(const machine_config &mconfig, const char *tag, d
: pci_host_device(mconfig, VRC4373, "NEC VRC4373 System Controller", tag, owner, clock, "vrc4373", __FILE__),
m_cpu_space(nullptr), m_cpu(nullptr), cpu_tag(nullptr), m_irq_num(-1),
m_mem_config("memory_space", ENDIANNESS_LITTLE, 32, 32),
m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32), m_ram_size(0), m_ram_base(0), m_simm_size(0), m_simm_base(0), m_pci1_laddr(0), m_pci2_laddr(0), m_pci_io_laddr(0), m_target1_laddr(0), m_target2_laddr(0),
m_region(*this, DEVICE_SELF)
m_io_config("io_space", ENDIANNESS_LITTLE, 32, 32), m_pci1_laddr(0), m_pci2_laddr(0), m_pci_io_laddr(0), m_target1_laddr(0), m_target2_laddr(0),
m_romRegion(*this, "rom")
{
}
@ -59,19 +59,21 @@ void vrc4373_device::device_start()
io_window_end = 0xffffffff;
io_offset = 0x00000000;
status = 0x0280;
m_ram_size = 1<<22;
m_ram_base = 0;
m_simm_size = 1<<21;
m_simm_base = 0;
// Reserve 8M for ram
m_ram.reserve(0x00800000 / 4);
// Reserve 32M for simm[0]
m_simm[0].reserve(0x02000000 / 4);
// ROM size = 1 MB
m_cpu_space->install_rom (0x1fc00000, 0x1fcfffff, m_region->base());
// ROM
UINT32 romSize = m_romRegion->bytes();
m_cpu_space->install_rom(0x1fc00000, 0x1fc00000 + romSize - 1, m_romRegion->base());
// Nile register mapppings
m_cpu_space->install_device(0x0f000000, 0x0f0000ff, *static_cast<vrc4373_device *>(this), &vrc4373_device::cpu_map);
// PCI Configuration also mapped at 0x0f000100
m_cpu_space->install_device(0x0f000100, 0x0f0001ff, *static_cast<vrc4373_device *>(this), &vrc4373_device::config_map);
// MIPS drc
m_cpu->add_fastram(0x1fc00000, 0x1fcfffff, TRUE, m_region->base());
m_cpu->add_fastram(0x1fc00000, 0x1fcfffff, TRUE, m_romRegion->base());
// DMA timer
m_dma_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(vrc4373_device::dma_transfer), this));
@ -90,6 +92,7 @@ void vrc4373_device::device_reset()
void vrc4373_device::map_cpu_space()
{
UINT32 winStart, winEnd, winSize;
UINT32 regConfig;
// VRC4373 is at 0x0f000000 to 0x0f0001ff
// ROM region starts at 0x1f000000
@ -99,17 +102,41 @@ void vrc4373_device::map_cpu_space()
// Clear fastram regions in cpu after rom
m_cpu->clear_fastram(1);
if (m_cpu_regs[NREG_BMCR]&0x8) {
m_cpu_space->install_ram(m_ram_base, m_ram_base+m_ram_size-1, &m_ram[0]);
m_cpu->add_fastram(m_ram_base, m_ram_size-1, FALSE, &m_ram[0]);
regConfig = m_cpu_regs[NREG_BMCR];
if (regConfig & 0x8) {
winSize = 1 << 22; // 4MB
for (int i = 14; i <= 15; i++) {
if (!((regConfig >> i) & 0x1)) winSize <<= 1;
else break;
}
winStart = (regConfig & 0x0fc00000);
winEnd = winStart + winSize - 1;
m_ram.resize(winSize / 4);
m_cpu_space->install_ram(winStart, winEnd, m_ram.data());
m_cpu->add_fastram(winStart, winEnd, FALSE, m_ram.data());
if (LOG_NILE)
logerror("%s: map_cpu_space ram_size=%08X ram_base=%08X\n", tag(),m_ram_size,m_ram_base);
logerror("map_cpu_space ram_size=%08X ram_base=%08X\n", winSize, winStart);
}
if (m_cpu_regs[NREG_SIMM1]&0x8) {
m_cpu_space->install_ram(m_simm_base, m_simm_base+m_simm_size-1, &m_simm[0]);
//m_cpu->add_fastram(m_simm_base, m_simm_size-1, FALSE, &m_simm[0]);
if (LOG_NILE)
logerror("%s: map_cpu_space simm_size=%08X simm_base=%08X\n", tag(),m_simm_size,m_simm_base);
// Map SIMMs
for (int simIndex = 0; simIndex < 4; simIndex++) {
regConfig = m_cpu_regs[NREG_SIMM1 + simIndex];
if (regConfig & 0x8) {
winSize = 1 << 21; // 2MB
for (int i = 13; i <= 17; i++) {
if (!((regConfig >> i) & 0x1)) winSize <<= 1;
else break;
}
winStart = (regConfig & 0x0fe00000);
winEnd = winStart + winSize - 1;
m_simm[simIndex].resize(winSize / 4);
m_cpu_space->install_ram(winStart, winEnd, m_simm[simIndex].data());
m_cpu->add_fastram(winStart, winEnd, FALSE, m_simm[simIndex].data());
if (LOG_NILE)
logerror("map_cpu_space simm_size[%i]=%08X simm_base=%08X\n", simIndex, winSize, winStart);
}
}
// PCI Master Window 1
@ -427,27 +454,10 @@ WRITE32_MEMBER(vrc4373_device::cpu_if_w)
}
break;
case NREG_BMCR:
if ((data>>3)&0x1) {
m_ram_size = 1<<22; // 4MB
for (int i=14; i<=15; i++) {
if (!((data>>i)&0x1)) m_ram_size<<=1;
else break;
}
m_ram.resize(m_ram_size/4);
m_ram_base = (data & 0x0fc00000);
}
map_cpu_space();
break;
case NREG_SIMM1:
if ((data>>3)&0x1) {
m_simm_size = 1<<21; // 2MB
for (int i=13; i<=17; i++) {
if (!((data>>i)&0x1)) m_simm_size<<=1;
else break;
}
m_simm.resize(m_simm_size/4);
m_simm_base = (data & 0x0fe00000);
}
case NREG_SIMM2:
case NREG_SIMM3:
case NREG_SIMM4:
map_cpu_space();
break;
default:

8
src/devices/machine/vrc4373.h
View File

@ -117,20 +117,16 @@ private:
void map_cpu_space();
UINT32 m_ram_size;
UINT32 m_ram_base;
std::vector<UINT32> m_ram;
UINT32 m_simm_size;
UINT32 m_simm_base;
std::vector<UINT32> m_simm;
std::vector<UINT32> m_simm[4];
UINT32 m_cpu_regs[0x7c];
UINT32 m_pci1_laddr, m_pci2_laddr, m_pci_io_laddr;
UINT32 m_target1_laddr, m_target2_laddr;
required_memory_region m_region;
required_memory_region m_romRegion;
emu_timer* m_dma_timer;
};

9
src/mame/drivers/atlantis.cpp
View File

@ -171,6 +171,7 @@ INPUT_PORTS_END
* Machine driver
*
*************************************/
#define PCI_ID_NILE ":pci:00.0"
static MACHINE_CONFIG_START( mwskins, atlantis_state )
@ -180,7 +181,7 @@ static MACHINE_CONFIG_START( mwskins, atlantis_state )
MCFG_MIPS3_DCACHE_SIZE(16384)
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_VRC4373_ADD( ":pci:00.0", ":maincpu")
MCFG_VRC4373_ADD( PCI_ID_NILE, ":maincpu")
MCFG_PCI9050_ADD( ":pci:0b.0")
MCFG_PCI9050_SET_MAP(0, map0)
MCFG_PCI9050_SET_MAP(1, map1) // 2 skipped for testing
@ -214,7 +215,7 @@ MACHINE_CONFIG_END
*************************************/
ROM_START( mwskins )
ROM_REGION32_LE( 0x80000, ":pci:00.0", 0 ) /* 512k for R4310 code */
ROM_REGION32_LE( 0x80000, PCI_ID_NILE":rom", 0 ) /* 512k for R4310 code */
ROM_LOAD( "skins_game_u4_boot_1.00.u4", 0x000000, 0x080000, CRC(0fe87720) SHA1(4b24abbe662a2d7b61e6a3f079e28b73605ba19f) )
DISK_REGION( "ide:0:hdd:image" )
@ -222,7 +223,7 @@ ROM_START( mwskins )
ROM_END
ROM_START( mwskinsa )
ROM_REGION32_LE( 0x80000, ":pci:00.0", 0 ) /* 512k for R4310 code */
ROM_REGION32_LE( 0x80000, PCI_ID_NILE":rom", 0 ) /* 512k for R4310 code */
ROM_LOAD( "skins_game_u4_boot_1.00.u4", 0x000000, 0x080000, CRC(0fe87720) SHA1(4b24abbe662a2d7b61e6a3f079e28b73605ba19f) )
DISK_REGION( "ide:0:hdd:image" )
@ -230,7 +231,7 @@ ROM_START( mwskinsa )
ROM_END
ROM_START( mwskinso )
ROM_REGION32_LE( 0x80000, ":pci:00.0", 0 ) /* 512k for R4310 code */
ROM_REGION32_LE( 0x80000, PCI_ID_NILE":rom", 0 ) /* 512k for R4310 code */
ROM_LOAD( "skins_game_u4_boot_1.00.u4", 0x000000, 0x080000, CRC(0fe87720) SHA1(4b24abbe662a2d7b61e6a3f079e28b73605ba19f) )
DISK_REGION( "ide:0:hdd:image" )

7
src/mame/drivers/iteagle.cpp
View File

@ -143,6 +143,7 @@ void iteagle_state::machine_reset()
{
}
#define PCI_ID_NILE ":pci:00.0"
#define PCI_ID_PERIPH ":pci:06.0"
#define PCI_ID_IDE ":pci:06.1"
// Seconday IDE Control ":pci:06.2"
@ -159,7 +160,7 @@ static MACHINE_CONFIG_START( iteagle, iteagle_state )
MCFG_MIPS3_DCACHE_SIZE(8192)
MCFG_PCI_ROOT_ADD( ":pci")
MCFG_VRC4373_ADD( ":pci:00.0", ":maincpu")
MCFG_VRC4373_ADD( PCI_ID_NILE, ":maincpu")
MCFG_ITEAGLE_PERIPH_ADD( PCI_ID_PERIPH)
MCFG_IDE_PCI_ADD( PCI_ID_IDE, 0x1080C693, 0x00, 0x0)
MCFG_IDE_PCI_IRQ_ADD( ":maincpu", MIPS3_IRQ2)
@ -369,7 +370,7 @@ INPUT_PORTS_END
*
*************************************/
#define EAGLE_BIOS \
ROM_REGION( 0x100000, ":pci:00.0", 0 ) /* MIPS code */ \
ROM_REGION( 0x100000, PCI_ID_NILE":rom", 0 ) /* MIPS code */ \
ROM_SYSTEM_BIOS( 0, "209", "bootrom 2.09" ) \
ROMX_LOAD( "eagle209.u15", 0x000000, 0x100000, CRC(e0fc1a16) SHA1(c9524f7ee6b95bd484a3b75bcbe2243cb273f84c), ROM_BIOS(1) ) \
ROM_SYSTEM_BIOS( 1, "208", "bootrom 2.08" ) \
@ -409,7 +410,7 @@ ROM_START( iteagle )
ROM_END
ROM_START( virtpool ) /* On earlier Eagle 1 PCB, possibly a prototype version - later boards are known as Eagle 2 */
ROM_REGION( 0x100000, ":pci:00.0", 0 ) /* MIPS code */
ROM_REGION( 0x100000, PCI_ID_NILE":rom", 0 ) /* MIPS code */
ROM_SYSTEM_BIOS( 0, "pool", "Virtual Pool bootrom" )
ROMX_LOAD( "eagle1_bootrom_v1p01", 0x000000, 0x080000, CRC(6c8c1593) SHA1(707d5633388f8dd4e9252f4d8d6f27c98c2cb35a), ROM_BIOS(1) )