Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-27 18:53:05 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

z80scc: Move rearming of tx interrupt from tx buffer write to transmit complete when using WR0_RESET_TX_INT. (nw)

Browse Source
This commit is contained in:
Ted Green 2017-06-05 11:52:50 -06:00
parent bd7bb286b8
commit ae850a9d66
1 changed files with 3 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/devices/machine/z80scc.cpp
View File

@ -1149,6 +1149,9 @@ void z80scc_channel::tra_complete()
m_uart->trigger_interrupt(m_index, INT_TRANSMIT); // Set TXIP bit m_uart->trigger_interrupt(m_index, INT_TRANSMIT); // Set TXIP bit
} }
} }
/* Arm interrupts since we completed another data byte, however it may be set by the reset tx int pending
command before the shifter is done and the disarm flag is evaluated again in tra_complete() */
m_tx_int_disarm = 0;
} }
else if (m_wr5 & WR5_SEND_BREAK) else if (m_wr5 & WR5_SEND_BREAK)
{ {
@ -2435,9 +2438,6 @@ void z80scc_channel::data_write(uint8_t data)
// check if to fire interrupt // check if to fire interrupt
LOG("- TX interrupt are %s\n", (m_wr1 & WR1_TX_INT_ENABLE) ? "enabled" : "disabled" ); LOG("- TX interrupt are %s\n", (m_wr1 & WR1_TX_INT_ENABLE) ? "enabled" : "disabled" );
/* Arm interrupts since we wrote another data byte, however it may be set by the reset tx int pending
command before the shifter is done and the disarm flag is evaluated again in tra_complete() */
m_tx_int_disarm = 0;
if (m_wr1 & WR1_TX_INT_ENABLE) if (m_wr1 & WR1_TX_INT_ENABLE)
{ {
if ((m_uart->m_variant & z80scc_device::SET_ESCC) && if ((m_uart->m_variant & z80scc_device::SET_ESCC) &&