diff --git a/src/mame/drivers/cyclemb.c b/src/mame/drivers/cyclemb.c index b76aad67d40..60897fd76c2 100644 --- a/src/mame/drivers/cyclemb.c +++ b/src/mame/drivers/cyclemb.c @@ -267,7 +267,7 @@ ADDRESS_MAP_END static MACHINE_RESET( cyclemb ) { - josvolly_8741_reset(); + cyclemb_8741_reset(machine); } @@ -402,32 +402,6 @@ static INPUT_PORTS_START( cyclemb ) PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_START("IN5") - PORT_DIPNAME( 0x01, 0x01, "IN5" ) - PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_START("DSW1") PORT_DIPNAME( 0x01, 0x01, "DSW1" ) PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) @@ -444,15 +418,7 @@ static INPUT_PORTS_START( cyclemb ) PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) - PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) - PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) - PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED ) PORT_START("DSW2") PORT_DIPNAME( 0x01, 0x01, "DSW2" ) @@ -471,6 +437,32 @@ static INPUT_PORTS_START( cyclemb ) PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) PORT_DIPSETTING( 0x00, DEF_STR( On ) ) PORT_BIT( 0xe0, IP_ACTIVE_LOW, IPT_UNUSED ) + + PORT_START("DSW3") + PORT_DIPNAME( 0x01, 0x01, "DSW3" ) + PORT_DIPSETTING( 0x01, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x02, 0x02, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x02, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x04, 0x04, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x04, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x08, 0x08, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x08, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x10, 0x10, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x10, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x20, 0x20, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x20, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x40, 0x40, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x40, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) + PORT_DIPNAME( 0x80, 0x80, DEF_STR( Unknown ) ) + PORT_DIPSETTING( 0x80, DEF_STR( Off ) ) + PORT_DIPSETTING( 0x00, DEF_STR( On ) ) INPUT_PORTS_END static const gfx_layout charlayout = diff --git a/src/mame/machine/tait8741.c b/src/mame/machine/tait8741.c index ab28534303f..1810577991e 100644 --- a/src/mame/machine/tait8741.c +++ b/src/mame/machine/tait8741.c @@ -535,112 +535,85 @@ READ8_HANDLER( josvolly_8741_0_r ) { return josvolly_8741_r(space,0,offset); } WRITE8_HANDLER( josvolly_8741_1_w ) { josvolly_8741_w(space,1,offset,data); } READ8_HANDLER( josvolly_8741_1_r ) { return josvolly_8741_r(space,1,offset); } +static struct +{ + UINT8 rxd; + UINT8 txd; + UINT8 rst; +}cyclemb_mcu; + +void cyclemb_8741_reset(running_machine *machine) +{ + cyclemb_mcu.txd = 0; + cyclemb_mcu.rst = 1; +} + static void cyclemb_8741_w(const address_space *space, int num, int offset, int data) { - JV8741 *mcu = &i8741[num]; - - if(offset==1) + if(offset == 1) //command port { - LOG(("%s:8741[%d] CW %02X\n", cpuexec_describe_context(space->machine), num, data)); - - /* read pointer */ - mcu->cmd = data; - /* CMD */ + printf("%02x CMD PC=%04x\n",data,cpu_get_pc(space->cpu)); switch(data) { - case 0: - mcu->txd = data ^ 0x40; - mcu->sts |= 0x02; - mcu->rst = 0; - break; - case 1: - /* - status codes: - 0x06 sub NG IOX2 - 0x05 sub NG IOX1 - 0x04 sub NG CIOS - 0x03 sub NG OPN - 0x02 sub NG ROM - 0x01 sub NG RAM - 0x00 ok - */ - mcu->rxd = 0 ^ 0x40; - mcu->sts |= 0x02; - /* ?? */ - //mcu->rxd = 0; /* SBSTS ( DIAG ) , killed */ - mcu->sts |= 0x01; /* RD ready */ - mcu->rst = 0; - break; - case 2: - mcu->rxd = (input_port_read(space->machine, "DSW2") & 0x1f) << 2; - mcu->sts |= 0x01; /* RD ready */ - mcu->rst = 0; - break; - case 3: /* normal mode ? */ - //mcu->rxd = input_port_read(space->machine, "DSW1"); - mcu->sts |= 0x01; /* RD ready */ - mcu->rst = 1; - break; - - case 0xf0: /* clear main sts ? */ - mcu->txd = data ^ 0x40; - mcu->sts |= 0x02; - break; + case 0: + cyclemb_mcu.rxd = 0x40; + cyclemb_mcu.rst = 0; + break; + case 1: + /* + status codes: + 0x06 sub NG IOX2 + 0x05 sub NG IOX1 + 0x04 sub NG CIOS + 0x03 sub NG OPN + 0x02 sub NG ROM + 0x01 sub NG RAM + 0x00 ok + */ + cyclemb_mcu.rxd = 0x40; + cyclemb_mcu.rst = 0; + break; + case 2: + cyclemb_mcu.rxd = (input_port_read(space->machine, "DSW2") & 0x1f) << 2; + cyclemb_mcu.rst = 0; + break; + case 3: + //cyclemb_mcu.rxd = input_port_read(space->machine, "DSW2"); + cyclemb_mcu.rst = 1; + break; } } - else + else //data port { - /* data */ - LOG(("%s:8741[%d] DW %02X\n", cpuexec_describe_context(space->machine), num, data)); - - mcu->txd = data; - mcu->sts |= 0x02; /* TXD busy */ -#if 1 - /* interrupt ? */ - if(num == 0) - { - if(josvolly_nmi_enable) - { - cputag_set_input_line(space->machine, "audiocpu", INPUT_LINE_NMI, PULSE_LINE); - josvolly_nmi_enable = 0; - } - } -#endif + printf("%02x DATA PC=%04x\n",data,cpu_get_pc(space->cpu)); + cyclemb_mcu.txd = data; } - josvolly_8741_do(space->machine, num); } static INT8 cyclemb_8741_r(const address_space *space,int num,int offset) { - JV8741 *mcu = &i8741[num]; - int ret; - - if(offset==1) + if(offset == 1) //status port { - if(mcu->rst) + printf("STATUS PC=%04x\n",cpu_get_pc(space->cpu)); + + return 1; + } + else //data port + { + printf("READ PC=%04x\n",cpu_get_pc(space->cpu)); + if(cyclemb_mcu.rst) { - //printf("%02x\n",mcu->txd); - switch(mcu->txd) + switch(cpu_get_pc(space->cpu)) { - case 0x00: mcu->rxd = input_port_read(space->machine, "IN0"); //dip-sw1 - case 0x40: mcu->rxd = input_port_read(space->machine, "IN1"); //dip-sw3 - case 0x41: mcu->rxd = input_port_read(space->machine, "IN2"); //dip-sw3 - case 0x84: mcu->rxd = input_port_read(space->machine, "IN3"); //dip-sw3 - case 0x11: mcu->rxd = input_port_read(space->machine, "IN4"); //dip-sw3 + case 0x760: cyclemb_mcu.rxd = ((input_port_read(space->machine,"DSW1") & 0x1f) << 2) | (mame_rand(space->machine) & 1); break; + case 0x35c: cyclemb_mcu.rxd = ((input_port_read(space->machine,"DSW3")) & 0xff); break; } } - ret = mcu->sts; - LOG(("%s:8741[%d] SR %02X\n",cpuexec_describe_context(space->machine),num,ret)); + + return cyclemb_mcu.rxd; } - else - { - /* clear status port */ - mcu->sts &= ~0x01; /* RD ready */ - ret = mcu->rxd; - LOG(("%s:8741[%d] DR %02X\n",cpuexec_describe_context(space->machine),num,ret)); - //mcu->rst = 0; - } - return ret; + + return 0; } diff --git a/src/mame/machine/tait8741.h b/src/mame/machine/tait8741.h index e1d805b7e02..f22d7d49792 100644 --- a/src/mame/machine/tait8741.h +++ b/src/mame/machine/tait8741.h @@ -54,6 +54,7 @@ READ8_HANDLER( josvolly_8741_1_r ); Cycle Mahbou set. ****************************************************************************/ +void cyclemb_8741_reset(running_machine *machine); WRITE8_HANDLER( cyclemb_8741_0_w ); //WRITE8_HANDLER( cyclemb_8741_1_w ); READ8_HANDLER( cyclemb_8741_0_r );