note (nw)

This commit is contained in:
hap 2016-11-04 15:53:38 +01:00
parent 421b5e2638
commit aea3cef80a
2 changed files with 4 additions and 4 deletions

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@ -548,9 +548,9 @@ static MACHINE_CONFIG_START( fexcel68k, fidel68k_state )
/* basic machine hardware */
MCFG_CPU_ADD("maincpu", M68000, XTAL_12MHz)
MCFG_CPU_PROGRAM_MAP(fexcel68k_map)
MCFG_TIMER_DRIVER_ADD_PERIODIC("irq_on", fidel68k_state, irq_on, attotime::from_hz(589)) // from 556 timer (22nf, 91K+20K, 100)
MCFG_TIMER_START_DELAY(attotime::from_hz(589) - attotime::from_nsec(1525)) // active for 1.525us
MCFG_TIMER_DRIVER_ADD_PERIODIC("irq_off", fidel68k_state, irq_off, attotime::from_hz(589))
MCFG_TIMER_DRIVER_ADD_PERIODIC("irq_on", fidel68k_state, irq_on, attotime::from_hz(618)) // theoretical frequency from 556 timer (22nf, 91K + 20K POT @ 14.8K, 0.1K), measurement was 580Hz
MCFG_TIMER_START_DELAY(attotime::from_hz(618) - attotime::from_nsec(1525)) // active for 1.525us
MCFG_TIMER_DRIVER_ADD_PERIODIC("irq_off", fidel68k_state, irq_off, attotime::from_hz(618))
MCFG_TIMER_DRIVER_ADD_PERIODIC("display_decay", fidelz80base_state, display_decay_tick, attotime::from_msec(1))
MCFG_DEFAULT_LAYOUT(layout_fidel_ex_68k)

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@ -6,7 +6,7 @@
TODO:
- Sound is too short and high pitch, better when you underclock the cpu.
Is cpu cycle timing wrong? or internal divider?
Is cpu cycle timing wrong? or waitstate on p1000_w?
******************************************************************************/