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tms32051.c: Modernized cpu core. [Wilbert Pol]

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This commit is contained in:
Wilbert Pol 2013-12-31 16:05:21 +00:00
parent a8a62c3212
commit aecdd2151d
4 changed files with 1467 additions and 1358 deletions
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1307
src/emu/cpu/tms32051/32051ops.c
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390
src/emu/cpu/tms32051/32051ops.h
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@ -1,251 +1,251 @@
static void (*const tms32051_opcode_table[256])(tms32051_state *cpustate) =
const tms32051_device::opcode_func tms32051_device::s_opcode_table[256] =
{
/* 0x00 - 0x0f */
op_lar_mem, op_lar_mem, op_lar_mem, op_lar_mem,
op_lar_mem, op_lar_mem, op_lar_mem, op_lar_mem,
op_lamm, op_smmr, op_subc, op_rpt_mem,
op_out, op_ldp_mem, op_lst_st0, op_lst_st1,
&tms32051_device::op_lar_mem, &tms32051_device::op_lar_mem, &tms32051_device::op_lar_mem, &tms32051_device::op_lar_mem,
&tms32051_device::op_lar_mem, &tms32051_device::op_lar_mem, &tms32051_device::op_lar_mem, &tms32051_device::op_lar_mem,
&tms32051_device::op_lamm, &tms32051_device::op_smmr, &tms32051_device::op_subc, &tms32051_device::op_rpt_mem,
&tms32051_device::op_out, &tms32051_device::op_ldp_mem, &tms32051_device::op_lst_st0, &tms32051_device::op_lst_st1,
/* 0x10 - 0x1f */
op_lacc_mem, op_lacc_mem, op_lacc_mem, op_lacc_mem,
op_lacc_mem, op_lacc_mem, op_lacc_mem, op_lacc_mem,
op_lacc_mem, op_lacc_mem, op_lacc_mem, op_lacc_mem,
op_lacc_mem, op_lacc_mem, op_lacc_mem, op_lacc_mem,
&tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem,
&tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem,
&tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem,
&tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem, &tms32051_device::op_lacc_mem,
/* 0x20 - 0x2f */
op_add_mem, op_add_mem, op_add_mem, op_add_mem,
op_add_mem, op_add_mem, op_add_mem, op_add_mem,
op_add_mem, op_add_mem, op_add_mem, op_add_mem,
op_add_mem, op_add_mem, op_add_mem, op_add_mem,
&tms32051_device::op_add_mem, &tms32051_device::op_add_mem, &tms32051_device::op_add_mem, &tms32051_device::op_add_mem,
&tms32051_device::op_add_mem, &tms32051_device::op_add_mem, &tms32051_device::op_add_mem, &tms32051_device::op_add_mem,
&tms32051_device::op_add_mem, &tms32051_device::op_add_mem, &tms32051_device::op_add_mem, &tms32051_device::op_add_mem,
&tms32051_device::op_add_mem, &tms32051_device::op_add_mem, &tms32051_device::op_add_mem, &tms32051_device::op_add_mem,
/* 0x30 - 0x3f */
op_sub_mem, op_sub_mem, op_sub_mem, op_sub_mem,
op_sub_mem, op_sub_mem, op_sub_mem, op_sub_mem,
op_sub_mem, op_sub_mem, op_sub_mem, op_sub_mem,
op_sub_mem, op_sub_mem, op_sub_mem, op_sub_mem,
&tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem,
&tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem,
&tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem,
&tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem, &tms32051_device::op_sub_mem,
/* 0x40 - 0x4f */
op_bit, op_bit, op_bit, op_bit,
op_bit, op_bit, op_bit, op_bit,
op_bit, op_bit, op_bit, op_bit,
op_bit, op_bit, op_bit, op_bit,
&tms32051_device::op_bit, &tms32051_device::op_bit, &tms32051_device::op_bit, &tms32051_device::op_bit,
&tms32051_device::op_bit, &tms32051_device::op_bit, &tms32051_device::op_bit, &tms32051_device::op_bit,
&tms32051_device::op_bit, &tms32051_device::op_bit, &tms32051_device::op_bit, &tms32051_device::op_bit,
&tms32051_device::op_bit, &tms32051_device::op_bit, &tms32051_device::op_bit, &tms32051_device::op_bit,
/* 0x50 - 0x5f */
op_mpya, op_mpys, op_sqra, op_sqrs,
op_mpy_mem, op_mpyu, op_invalid, op_bldp,
op_xpl_dbmr, op_opl_dbmr, op_apl_dbmr, op_cpl_dbmr,
op_xpl_imm, op_opl_imm, op_apl_imm, op_cpl_imm,
&tms32051_device::op_mpya, &tms32051_device::op_mpys, &tms32051_device::op_sqra, &tms32051_device::op_sqrs,
&tms32051_device::op_mpy_mem, &tms32051_device::op_mpyu, &tms32051_device::op_invalid, &tms32051_device::op_bldp,
&tms32051_device::op_xpl_dbmr, &tms32051_device::op_opl_dbmr, &tms32051_device::op_apl_dbmr, &tms32051_device::op_cpl_dbmr,
&tms32051_device::op_xpl_imm, &tms32051_device::op_opl_imm, &tms32051_device::op_apl_imm, &tms32051_device::op_cpl_imm,
/* 0x60 - 0x6f */
op_addc, op_add_s16_mem, op_adds, op_addt,
op_subb, op_sub_s16_mem, op_subs, op_subt,
op_zalr, op_lacl_mem, op_lacc_s16_mem,op_lact,
op_xor_mem, op_or_mem, op_and_mem, op_bitt,
&tms32051_device::op_addc, &tms32051_device::op_add_s16_mem, &tms32051_device::op_adds, &tms32051_device::op_addt,
&tms32051_device::op_subb, &tms32051_device::op_sub_s16_mem, &tms32051_device::op_subs, &tms32051_device::op_subt,
&tms32051_device::op_zalr, &tms32051_device::op_lacl_mem, &tms32051_device::op_lacc_s16_mem,&tms32051_device::op_lact,
&tms32051_device::op_xor_mem, &tms32051_device::op_or_mem, &tms32051_device::op_and_mem, &tms32051_device::op_bitt,
/* 0x70 - 0x7f */
op_lta, op_ltp, op_ltd, op_lt,
op_lts, op_lph, op_pshd, op_dmov,
op_adrk, op_b, op_call, op_banz,
op_sbrk, op_bd, op_calld, op_banzd,
&tms32051_device::op_lta, &tms32051_device::op_ltp, &tms32051_device::op_ltd, &tms32051_device::op_lt,
&tms32051_device::op_lts, &tms32051_device::op_lph, &tms32051_device::op_pshd, &tms32051_device::op_dmov,
&tms32051_device::op_adrk, &tms32051_device::op_b, &tms32051_device::op_call, &tms32051_device::op_banz,
&tms32051_device::op_sbrk, &tms32051_device::op_bd, &tms32051_device::op_calld, &tms32051_device::op_banzd,
/* 0x80 - 0x8f */
op_sar, op_sar, op_sar, op_sar,
op_sar, op_sar, op_sar, op_sar,
op_samm, op_lmmr, op_popd, op_mar,
op_spl, op_sph, op_sst_st0, op_sst_st1,
&tms32051_device::op_sar, &tms32051_device::op_sar, &tms32051_device::op_sar, &tms32051_device::op_sar,
&tms32051_device::op_sar, &tms32051_device::op_sar, &tms32051_device::op_sar, &tms32051_device::op_sar,
&tms32051_device::op_samm, &tms32051_device::op_lmmr, &tms32051_device::op_popd, &tms32051_device::op_mar,
&tms32051_device::op_spl, &tms32051_device::op_sph, &tms32051_device::op_sst_st0, &tms32051_device::op_sst_st1,
/* 0x90 - 0x9f */
op_sacl, op_sacl, op_sacl, op_sacl,
op_sacl, op_sacl, op_sacl, op_sacl,
op_sach, op_sach, op_sach, op_sach,
op_sach, op_sach, op_sach, op_sach,
&tms32051_device::op_sacl, &tms32051_device::op_sacl, &tms32051_device::op_sacl, &tms32051_device::op_sacl,
&tms32051_device::op_sacl, &tms32051_device::op_sacl, &tms32051_device::op_sacl, &tms32051_device::op_sacl,
&tms32051_device::op_sach, &tms32051_device::op_sach, &tms32051_device::op_sach, &tms32051_device::op_sach,
&tms32051_device::op_sach, &tms32051_device::op_sach, &tms32051_device::op_sach, &tms32051_device::op_sach,
/* 0xa0 - 0xaf */
op_norm, op_invalid, op_mac, op_macd,
op_blpd_bmar, op_blpd_imm, op_tblr, op_tblw,
op_bldd_slimm, op_bldd_dlimm, op_mads, op_madd,
op_bldd_sbmar, op_bldd_dbmar, op_splk, op_in,
&tms32051_device::op_norm, &tms32051_device::op_invalid, &tms32051_device::op_mac, &tms32051_device::op_macd,
&tms32051_device::op_blpd_bmar, &tms32051_device::op_blpd_imm, &tms32051_device::op_tblr, &tms32051_device::op_tblw,
&tms32051_device::op_bldd_slimm, &tms32051_device::op_bldd_dlimm, &tms32051_device::op_mads, &tms32051_device::op_madd,
&tms32051_device::op_bldd_sbmar, &tms32051_device::op_bldd_dbmar, &tms32051_device::op_splk, &tms32051_device::op_in,
/* 0xb0 - 0xbf */
op_lar_simm, op_lar_simm, op_lar_simm, op_lar_simm,
op_lar_simm, op_lar_simm, op_lar_simm, op_lar_simm,
op_add_simm, op_lacl_simm, op_sub_simm, op_rpt_simm,
op_ldp_imm, op_ldp_imm, op_group_be, op_group_bf,
&tms32051_device::op_lar_simm, &tms32051_device::op_lar_simm, &tms32051_device::op_lar_simm, &tms32051_device::op_lar_simm,
&tms32051_device::op_lar_simm, &tms32051_device::op_lar_simm, &tms32051_device::op_lar_simm, &tms32051_device::op_lar_simm,
&tms32051_device::op_add_simm, &tms32051_device::op_lacl_simm, &tms32051_device::op_sub_simm, &tms32051_device::op_rpt_simm,
&tms32051_device::op_ldp_imm, &tms32051_device::op_ldp_imm, &tms32051_device::op_group_be, &tms32051_device::op_group_bf,
/* 0xc0 - 0xcf */
op_mpy_simm, op_mpy_simm, op_mpy_simm, op_mpy_simm,
op_mpy_simm, op_mpy_simm, op_mpy_simm, op_mpy_simm,
op_mpy_simm, op_mpy_simm, op_mpy_simm, op_mpy_simm,
op_mpy_simm, op_mpy_simm, op_mpy_simm, op_mpy_simm,
&tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm,
&tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm,
&tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm,
&tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm,
/* 0xd0 - 0xdf */
op_mpy_simm, op_mpy_simm, op_mpy_simm, op_mpy_simm,
op_mpy_simm, op_mpy_simm, op_mpy_simm, op_mpy_simm,
op_mpy_simm, op_mpy_simm, op_mpy_simm, op_mpy_simm,
op_mpy_simm, op_mpy_simm, op_mpy_simm, op_mpy_simm,
&tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm,
&tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm,
&tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm,
&tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm, &tms32051_device::op_mpy_simm,
/* 0xe0 - 0xef */
op_bcnd, op_bcnd, op_bcnd, op_bcnd,
op_xc, op_xc, op_xc, op_xc,
op_cc, op_cc, op_cc, op_cc,
op_retc, op_retc, op_retc, op_retc,
&tms32051_device::op_bcnd, &tms32051_device::op_bcnd, &tms32051_device::op_bcnd, &tms32051_device::op_bcnd,
&tms32051_device::op_xc, &tms32051_device::op_xc, &tms32051_device::op_xc, &tms32051_device::op_xc,
&tms32051_device::op_cc, &tms32051_device::op_cc, &tms32051_device::op_cc, &tms32051_device::op_cc,
&tms32051_device::op_retc, &tms32051_device::op_retc, &tms32051_device::op_retc, &tms32051_device::op_retc,
/* 0xf0 - 0xff */
op_bcndd, op_bcndd, op_bcndd, op_bcndd,
op_xc, op_xc, op_xc, op_xc,
op_ccd, op_ccd, op_ccd, op_ccd,
op_retcd, op_retcd, op_retcd, op_retcd
&tms32051_device::op_bcndd, &tms32051_device::op_bcndd, &tms32051_device::op_bcndd, &tms32051_device::op_bcndd,
&tms32051_device::op_xc, &tms32051_device::op_xc, &tms32051_device::op_xc, &tms32051_device::op_xc,
&tms32051_device::op_ccd, &tms32051_device::op_ccd, &tms32051_device::op_ccd, &tms32051_device::op_ccd,
&tms32051_device::op_retcd, &tms32051_device::op_retcd, &tms32051_device::op_retcd, &tms32051_device::op_retcd
};
static void (*const tms32051_opcode_table_be[256])(tms32051_state *cpustate) =
const tms32051_device::opcode_func tms32051_device::s_opcode_table_be[256] =
{
/* 0x00 - 0x0f */
op_abs, op_cmpl, op_neg, op_pac,
op_apac, op_spac, op_invalid, op_invalid,
op_invalid, op_sfl, op_sfr, op_invalid,
op_rol, op_ror, op_invalid, op_invalid,
&tms32051_device::op_abs, &tms32051_device::op_cmpl, &tms32051_device::op_neg, &tms32051_device::op_pac,
&tms32051_device::op_apac, &tms32051_device::op_spac, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_sfl, &tms32051_device::op_sfr, &tms32051_device::op_invalid,
&tms32051_device::op_rol, &tms32051_device::op_ror, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x10 - 0x1f */
op_addb, op_adcb, op_andb, op_orb,
op_rolb, op_rorb, op_sflb, op_sfrb,
op_sbb, op_sbbb, op_xorb, op_crgt,
op_crlt, op_exar, op_sacb, op_lacb,
&tms32051_device::op_addb, &tms32051_device::op_adcb, &tms32051_device::op_andb, &tms32051_device::op_orb,
&tms32051_device::op_rolb, &tms32051_device::op_rorb, &tms32051_device::op_sflb, &tms32051_device::op_sfrb,
&tms32051_device::op_sbb, &tms32051_device::op_sbbb, &tms32051_device::op_xorb, &tms32051_device::op_crgt,
&tms32051_device::op_crlt, &tms32051_device::op_exar, &tms32051_device::op_sacb, &tms32051_device::op_lacb,
/* 0x20 - 0x2f */
op_bacc, op_baccd, op_idle, op_idle2,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_bacc, &tms32051_device::op_baccd, &tms32051_device::op_idle, &tms32051_device::op_idle2,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x30 - 0x3f */
op_cala, op_invalid, op_pop, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_reti, op_invalid, op_rete, op_invalid,
op_push, op_calad, op_invalid, op_invalid,
&tms32051_device::op_cala, &tms32051_device::op_invalid, &tms32051_device::op_pop, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_reti, &tms32051_device::op_invalid, &tms32051_device::op_rete, &tms32051_device::op_invalid,
&tms32051_device::op_push, &tms32051_device::op_calad, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x40 - 0x4f */
op_clrc_intm, op_setc_intm, op_clrc_ov, op_setc_ov,
op_clrc_cnf, op_setc_cnf, op_clrc_ext, op_setc_ext,
op_clrc_hold, op_setc_hold, op_clrc_tc, op_setc_tc,
op_clrc_xf, op_setc_xf, op_clrc_carry, op_setc_carry,
&tms32051_device::op_clrc_intm, &tms32051_device::op_setc_intm, &tms32051_device::op_clrc_ov, &tms32051_device::op_setc_ov,
&tms32051_device::op_clrc_cnf, &tms32051_device::op_setc_cnf, &tms32051_device::op_clrc_ext, &tms32051_device::op_setc_ext,
&tms32051_device::op_clrc_hold, &tms32051_device::op_setc_hold, &tms32051_device::op_clrc_tc, &tms32051_device::op_setc_tc,
&tms32051_device::op_clrc_xf, &tms32051_device::op_setc_xf, &tms32051_device::op_clrc_carry, &tms32051_device::op_setc_carry,
/* 0x50 - 0x5f */
op_invalid, op_trap, op_nmi, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_zpr, op_zap, op_sath, op_satl,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_trap, &tms32051_device::op_nmi, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_zpr, &tms32051_device::op_zap, &tms32051_device::op_sath, &tms32051_device::op_satl,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x60 - 0x6f */
op_intr, op_intr, op_intr, op_intr,
op_intr, op_intr, op_intr, op_intr,
op_intr, op_intr, op_intr, op_intr,
op_intr, op_intr, op_intr, op_intr,
&tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr,
&tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr,
&tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr,
&tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr,
/* 0x70 - 0x7f */
op_intr, op_intr, op_intr, op_intr,
op_intr, op_intr, op_intr, op_intr,
op_intr, op_intr, op_intr, op_intr,
op_intr, op_intr, op_intr, op_intr,
&tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr,
&tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr,
&tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr,
&tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr, &tms32051_device::op_intr,
/* 0x80 - 0x8f */
op_mpy_limm, op_and_s16_limm,op_or_s16_limm, op_xor_s16_limm,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_mpy_limm, &tms32051_device::op_and_s16_limm,&tms32051_device::op_or_s16_limm, &tms32051_device::op_xor_s16_limm,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x90 - 0x9f */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0xa0 - 0xaf */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0xb0 - 0xbf */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0xc0 - 0xcf */
op_invalid, op_invalid, op_invalid, op_invalid,
op_rpt_limm, op_rptz, op_rptb, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_rpt_limm, &tms32051_device::op_rptz, &tms32051_device::op_rptb, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0xd0 - 0xdf */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0xe0 - 0xef */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0xf0 - 0xff */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
};
static void (*const tms32051_opcode_table_bf[256])(tms32051_state *cpustate) =
const tms32051_device::opcode_func tms32051_device::s_opcode_table_bf[256] =
{
/* 0x00 - 0x0f */
op_spm, op_spm, op_spm, op_spm,
op_invalid, op_invalid, op_invalid, op_invalid,
op_lar_limm, op_lar_limm, op_lar_limm, op_lar_limm,
op_lar_limm, op_lar_limm, op_lar_limm, op_lar_limm,
&tms32051_device::op_spm, &tms32051_device::op_spm, &tms32051_device::op_spm, &tms32051_device::op_spm,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_lar_limm, &tms32051_device::op_lar_limm, &tms32051_device::op_lar_limm, &tms32051_device::op_lar_limm,
&tms32051_device::op_lar_limm, &tms32051_device::op_lar_limm, &tms32051_device::op_lar_limm, &tms32051_device::op_lar_limm,
/* 0x10 - 0x1f */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x20 - 0x2f */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x30 - 0x3f */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x40 - 0x4f */
op_invalid, op_invalid, op_invalid, op_invalid,
op_cmpr, op_cmpr, op_cmpr, op_cmpr,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_cmpr, &tms32051_device::op_cmpr, &tms32051_device::op_cmpr, &tms32051_device::op_cmpr,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x50 - 0x5f */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x60 - 0x6f */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x70 - 0x7f */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
/* 0x80 - 0x8f */
op_lacc_limm, op_lacc_limm, op_lacc_limm, op_lacc_limm,
op_lacc_limm, op_lacc_limm, op_lacc_limm, op_lacc_limm,
op_lacc_limm, op_lacc_limm, op_lacc_limm, op_lacc_limm,
op_lacc_limm, op_lacc_limm, op_lacc_limm, op_lacc_limm,
&tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm,
&tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm,
&tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm,
&tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm, &tms32051_device::op_lacc_limm,
/* 0x90 - 0x9f */
op_add_limm, op_add_limm, op_add_limm, op_add_limm,
op_add_limm, op_add_limm, op_add_limm, op_add_limm,
op_add_limm, op_add_limm, op_add_limm, op_add_limm,
op_add_limm, op_add_limm, op_add_limm, op_add_limm,
&tms32051_device::op_add_limm, &tms32051_device::op_add_limm, &tms32051_device::op_add_limm, &tms32051_device::op_add_limm,
&tms32051_device::op_add_limm, &tms32051_device::op_add_limm, &tms32051_device::op_add_limm, &tms32051_device::op_add_limm,
&tms32051_device::op_add_limm, &tms32051_device::op_add_limm, &tms32051_device::op_add_limm, &tms32051_device::op_add_limm,
&tms32051_device::op_add_limm, &tms32051_device::op_add_limm, &tms32051_device::op_add_limm, &tms32051_device::op_add_limm,
/* 0xa0 - 0xaf */
op_sub_limm, op_sub_limm, op_sub_limm, op_sub_limm,
op_sub_limm, op_sub_limm, op_sub_limm, op_sub_limm,
op_sub_limm, op_sub_limm, op_sub_limm, op_sub_limm,
op_sub_limm, op_sub_limm, op_sub_limm, op_sub_limm,
&tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm,
&tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm,
&tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm,
&tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm, &tms32051_device::op_sub_limm,
/* 0xb0 - 0xbf */
op_and_limm, op_and_limm, op_and_limm, op_and_limm,
op_and_limm, op_and_limm, op_and_limm, op_and_limm,
op_and_limm, op_and_limm, op_and_limm, op_and_limm,
op_and_limm, op_and_limm, op_and_limm, op_and_limm,
&tms32051_device::op_and_limm, &tms32051_device::op_and_limm, &tms32051_device::op_and_limm, &tms32051_device::op_and_limm,
&tms32051_device::op_and_limm, &tms32051_device::op_and_limm, &tms32051_device::op_and_limm, &tms32051_device::op_and_limm,
&tms32051_device::op_and_limm, &tms32051_device::op_and_limm, &tms32051_device::op_and_limm, &tms32051_device::op_and_limm,
&tms32051_device::op_and_limm, &tms32051_device::op_and_limm, &tms32051_device::op_and_limm, &tms32051_device::op_and_limm,
/* 0xc0 - 0xcf */
op_or_limm, op_or_limm, op_or_limm, op_or_limm,
op_or_limm, op_or_limm, op_or_limm, op_or_limm,
op_or_limm, op_or_limm, op_or_limm, op_or_limm,
op_or_limm, op_or_limm, op_or_limm, op_or_limm,
&tms32051_device::op_or_limm, &tms32051_device::op_or_limm, &tms32051_device::op_or_limm, &tms32051_device::op_or_limm,
&tms32051_device::op_or_limm, &tms32051_device::op_or_limm, &tms32051_device::op_or_limm, &tms32051_device::op_or_limm,
&tms32051_device::op_or_limm, &tms32051_device::op_or_limm, &tms32051_device::op_or_limm, &tms32051_device::op_or_limm,
&tms32051_device::op_or_limm, &tms32051_device::op_or_limm, &tms32051_device::op_or_limm, &tms32051_device::op_or_limm,
/* 0xd0 - 0xdf */
op_xor_limm, op_xor_limm, op_xor_limm, op_xor_limm,
op_xor_limm, op_xor_limm, op_xor_limm, op_xor_limm,
op_xor_limm, op_xor_limm, op_xor_limm, op_xor_limm,
op_xor_limm, op_xor_limm, op_xor_limm, op_xor_limm,
&tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm,
&tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm,
&tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm,
&tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm, &tms32051_device::op_xor_limm,
/* 0xe0 - 0xef */
op_bsar, op_bsar, op_bsar, op_bsar,
op_bsar, op_bsar, op_bsar, op_bsar,
op_bsar, op_bsar, op_bsar, op_bsar,
op_bsar, op_bsar, op_bsar, op_bsar,
&tms32051_device::op_bsar, &tms32051_device::op_bsar, &tms32051_device::op_bsar, &tms32051_device::op_bsar,
&tms32051_device::op_bsar, &tms32051_device::op_bsar, &tms32051_device::op_bsar, &tms32051_device::op_bsar,
&tms32051_device::op_bsar, &tms32051_device::op_bsar, &tms32051_device::op_bsar, &tms32051_device::op_bsar,
&tms32051_device::op_bsar, &tms32051_device::op_bsar, &tms32051_device::op_bsar, &tms32051_device::op_bsar,
/* 0xf0 - 0xff */
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
op_invalid, op_invalid, op_invalid, op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
&tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid, &tms32051_device::op_invalid,
};

785
src/emu/cpu/tms32051/tms32051.c
View File

@ -46,362 +46,331 @@ enum
TMS32051_AR7,
};
struct PMST
const device_type TMS32051 = &device_creator<tms32051_device>;
/**************************************************************************
* Internal memory map
**************************************************************************/
static ADDRESS_MAP_START( internal_pgm, AS_PROGRAM, 16, tms32051_device )
AM_RANGE(0x0000, 0x1fff) AM_ROM // ROM TODO: is off-chip if MP/_MC = 0
AM_RANGE(0x2000, 0x23ff) AM_RAM AM_SHARE("saram") // SARAM TODO: is off-chip if RAM bit = 0
AM_RANGE(0xfe00, 0xffff) AM_RAM AM_SHARE("daram_b0") // DARAM B0 TODO: is off-chip if CNF = 0
ADDRESS_MAP_END
static ADDRESS_MAP_START( internal_data, AS_DATA, 16, tms32051_device )
AM_RANGE(0x0000, 0x005f) AM_READWRITE(cpuregs_r, cpuregs_w)
AM_RANGE(0x0060, 0x007f) AM_RAM // DARAM B2
AM_RANGE(0x0100, 0x02ff) AM_RAM AM_SHARE("daram_b0") // DARAM B0 TODO: is unconnected if CNF = 1
AM_RANGE(0x0300, 0x04ff) AM_RAM // DARAM B1
AM_RANGE(0x0800, 0x0bff) AM_RAM AM_SHARE("saram") // SARAM TODO: is off-chip if OVLY = 0
ADDRESS_MAP_END
tms32051_device::tms32051_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
: cpu_device(mconfig, TMS32051, "TMS32051", tag, owner, clock, "tms32051", __FILE__)
, m_program_config("program", ENDIANNESS_LITTLE, 16, 16, -1, ADDRESS_MAP_NAME(internal_pgm))
, m_data_config("data", ENDIANNESS_LITTLE, 16, 16, -1, ADDRESS_MAP_NAME(internal_data))
{
UINT16 iptr;
UINT16 avis;
UINT16 ovly;
UINT16 ram;
UINT16 mpmc;
UINT16 ndx;
UINT16 trm;
UINT16 braf;
};
struct ST0
{
UINT16 dp;
UINT16 intm;
UINT16 ovm;
UINT16 ov;
UINT16 arp;
};
struct ST1
{
UINT16 arb;
UINT16 cnf;
UINT16 tc;
UINT16 sxm;
UINT16 c;
UINT16 hm;
UINT16 xf;
UINT16 pm;
};
struct tms32051_state
{
UINT16 pc;
UINT16 op;
INT32 acc;
INT32 accb;
INT32 preg;
UINT16 treg0;
UINT16 treg1;
UINT16 treg2;
UINT16 ar[8];
INT32 rptc;
UINT16 bmar;
INT32 brcr;
UINT16 paer;
UINT16 pasr;
UINT16 indx;
UINT16 dbmr;
UINT16 arcr;
ST0 st0;
ST1 st1;
PMST pmst;
UINT16 ifr;
UINT16 imr;
UINT16 pcstack[8];
int pcstack_ptr;
UINT16 rpt_start, rpt_end;
UINT16 cbcr;
UINT16 cbsr1;
UINT16 cber1;
UINT16 cbsr2;
UINT16 cber2;
struct
{
int tddr;
int psc;
UINT16 tim;
UINT16 prd;
} timer;
struct
{
INT32 acc;
INT32 accb;
UINT16 arcr;
UINT16 indx;
PMST pmst;
INT32 preg;
ST0 st0;
ST1 st1;
INT32 treg0;
INT32 treg1;
INT32 treg2;
} shadow;
legacy_cpu_device *device;
address_space *program;
direct_read_data *direct;
address_space *data;
int icount;
};
INLINE tms32051_state *get_safe_token(device_t *device)
{
assert(device != NULL);
assert(device->type() == TMS32051);
return (tms32051_state *)downcast<legacy_cpu_device *>(device)->token();
}
static void delay_slot(tms32051_state *cpustate, UINT16 startpc);
static void save_interrupt_context(tms32051_state *cpustate);
static void restore_interrupt_context(tms32051_state *cpustate);
static void check_interrupts(tms32051_state *cpustate);
#define CYCLES(x) (cpustate->icount -= x)
#define ROPCODE(cpustate) cpustate->direct->read_decrypted_word((cpustate->pc++) << 1)
INLINE void CHANGE_PC(tms32051_state *cpustate, UINT16 new_pc)
offs_t tms32051_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options)
{
cpustate->pc = new_pc;
extern CPU_DISASSEMBLE( tms32051 );
return CPU_DISASSEMBLE_NAME(tms32051)(this, buffer, pc, oprom, opram, options);
}
INLINE UINT16 PM_READ16(tms32051_state *cpustate, UINT16 address)
#define CYCLES(x) (m_icount -= x)
#define ROPCODE() m_direct->read_decrypted_word((m_pc++) << 1)
void tms32051_device::CHANGE_PC(UINT16 new_pc)
{
return cpustate->program->read_word(address << 1);
m_pc = new_pc;
}
INLINE void PM_WRITE16(tms32051_state *cpustate, UINT16 address, UINT16 data)
UINT16 tms32051_device::PM_READ16(UINT16 address)
{
cpustate->program->write_word(address << 1, data);
return m_program->read_word(address << 1);
}
INLINE UINT16 DM_READ16(tms32051_state *cpustate, UINT16 address)
void tms32051_device::PM_WRITE16(UINT16 address, UINT16 data)
{
return cpustate->data->read_word(address << 1);
m_program->write_word(address << 1, data);
}
INLINE void DM_WRITE16(tms32051_state *cpustate, UINT16 address, UINT16 data)
UINT16 tms32051_device::DM_READ16(UINT16 address)
{
cpustate->data->write_word(address << 1, data);
return m_data->read_word(address << 1);
}
void tms32051_device::DM_WRITE16(UINT16 address, UINT16 data)
{
m_data->write_word(address << 1, data);
}
#include "32051ops.c"
#include "32051ops.h"
static void op_group_be(tms32051_state *cpustate)
void tms32051_device::op_group_be()
{
tms32051_opcode_table_be[cpustate->op & 0xff](cpustate);
(this->*s_opcode_table_be[m_op & 0xff])();
}
static void op_group_bf(tms32051_state *cpustate)
void tms32051_device::op_group_bf()
{
tms32051_opcode_table_bf[cpustate->op & 0xff](cpustate);
(this->*s_opcode_table_bf[m_op & 0xff])();
}
static void delay_slot(tms32051_state *cpustate, UINT16 startpc)
void tms32051_device::delay_slot(UINT16 startpc)
{
cpustate->op = ROPCODE(cpustate);
tms32051_opcode_table[cpustate->op >> 8](cpustate);
m_op = ROPCODE();
(this->*s_opcode_table[m_op >> 8])();
while (cpustate->pc - startpc < 2)
while (m_pc - startpc < 2)
{
cpustate->op = ROPCODE(cpustate);
tms32051_opcode_table[cpustate->op >> 8](cpustate);
m_op = ROPCODE();
(this->*s_opcode_table[m_op >> 8])();
}
}
/*****************************************************************************/
static CPU_INIT( tms )
void tms32051_device::device_start()
{
tms32051_state *cpustate = get_safe_token(device);
m_program = &space(AS_PROGRAM);
m_direct = &m_program->direct();
m_data = &space(AS_DATA);
cpustate->device = device;
cpustate->program = &device->space(AS_PROGRAM);
cpustate->direct = &cpustate->program->direct();
cpustate->data = &device->space(AS_DATA);
m_pcstack_ptr = 0;
m_op = 0;
m_acc = 0;
m_accb = 0;
m_preg = 0;
m_treg0 = 0;
m_treg1 = 0;
m_treg2 = 0;
memset(m_ar, 0, sizeof(m_ar));
m_bmar = 0;
m_brcr = 0;
m_paer = 0;
m_pasr = 0;
m_indx = 0;
m_dbmr = 0;
m_arcr = 0;
memset(&m_st0, 0, sizeof(m_st0));
memset(&m_st1, 0, sizeof(m_st1));
memset(&m_pmst, 0, sizeof(m_pmst));
memset(m_pcstack, 0, sizeof(m_pcstack));
m_imr = 0;
m_cbsr1 = 0;
m_cber1 = 0;
m_cbsr2 = 0;
m_cber2 = 0;
memset(&m_timer, 0, sizeof(m_timer));
cpustate->pcstack_ptr = 0;
state_add( TMS32051_PC, "PC", m_pc).formatstr("%04X");
state_add( TMS32051_ACC, "ACC", m_acc).formatstr("%08X");
state_add( TMS32051_ACCB, "ACCB", m_accb).formatstr("%08X");
state_add( TMS32051_PREG, "PREG", m_preg).formatstr("%08X");
state_add( TMS32051_TREG0, "TREG0", m_treg0).formatstr("%04X");
state_add( TMS32051_TREG1, "TREG1", m_treg1).formatstr("%04X");
state_add( TMS32051_TREG2, "TREG2", m_treg2).formatstr("%04X");
state_add( TMS32051_BMAR, "BMAR", m_bmar).formatstr("%08X");
state_add( TMS32051_RPTC, "RPTC", m_rptc).formatstr("%08X");
state_add( TMS32051_BRCR, "BRCR", m_brcr).formatstr("%08X");
state_add( TMS32051_INDX, "INDX", m_indx).formatstr("%04X");
state_add( TMS32051_DBMR, "DBMR", m_dbmr).formatstr("%04X");
state_add( TMS32051_ARCR, "ARCR", m_arcr).formatstr("%04X");
state_add( TMS32051_DP, "DP", m_st0.dp).formatstr("%04X");
state_add( TMS32051_ARP, "ARP", m_st0.arp).formatstr("%04X");
state_add( TMS32051_ARB, "ARB", m_st1.arb).formatstr("%04X");
state_add( TMS32051_AR0, "AR0", m_ar[0]).formatstr("%04X");
state_add( TMS32051_AR1, "AR1", m_ar[1]).formatstr("%04X");
state_add( TMS32051_AR2, "AR2", m_ar[2]).formatstr("%04X");
state_add( TMS32051_AR3, "AR3", m_ar[3]).formatstr("%04X");
state_add( TMS32051_AR4, "AR4", m_ar[4]).formatstr("%04X");
state_add( TMS32051_AR5, "AR5", m_ar[5]).formatstr("%04X");
state_add( TMS32051_AR6, "AR6", m_ar[6]).formatstr("%04X");
state_add( TMS32051_AR7, "AR7", m_ar[7]).formatstr("%04X");
state_add(STATE_GENPC, "GENPC", m_pc).formatstr("%04X").noshow();
m_icountptr = &m_icount;
}
static CPU_RESET( tms )
void tms32051_device::device_reset()
{
tms32051_state *cpustate = get_safe_token(device);
// reset registers
cpustate->st0.intm = 1;
cpustate->st0.ov = 0;
cpustate->st1.c = 1;
cpustate->st1.cnf = 0;
cpustate->st1.hm = 1;
cpustate->st1.pm = 0;
cpustate->st1.sxm = 1;
cpustate->st1.xf = 1;
cpustate->pmst.avis = 0;
cpustate->pmst.braf = 0;
cpustate->pmst.iptr = 0;
cpustate->pmst.ndx = 0;
cpustate->pmst.ovly = 0;
cpustate->pmst.ram = 0;
cpustate->pmst.mpmc = 0; // TODO: this is set to logical pin state at reset
cpustate->pmst.trm = 0;
cpustate->ifr = 0;
cpustate->cbcr = 0;
cpustate->rptc = -1;
m_st0.intm = 1;
m_st0.ov = 0;
m_st1.c = 1;
m_st1.cnf = 0;
m_st1.hm = 1;
m_st1.pm = 0;
m_st1.sxm = 1;
m_st1.xf = 1;
m_pmst.avis = 0;
m_pmst.braf = 0;
m_pmst.iptr = 0;
m_pmst.ndx = 0;
m_pmst.ovly = 0;
m_pmst.ram = 0;
m_pmst.mpmc = 0; // TODO: this is set to logical pin state at reset
m_pmst.trm = 0;
m_ifr = 0;
m_cbcr = 0;
m_rptc = -1;
// simulate internal rom boot loader (can be removed when the dsp rom(s) is dumped)
cpustate->st0.intm = 1;
cpustate->st1.cnf = 1;
cpustate->pmst.ram = 1;
cpustate->pmst.ovly = 0;
m_st0.intm = 1;
m_st1.cnf = 1;
m_pmst.ram = 1;
m_pmst.ovly = 0;
int i;
UINT16 src, dst, length;
src = 0x7800;
dst = DM_READ16(cpustate, src++);
length = DM_READ16(cpustate, src++);
dst = DM_READ16(src++);
length = DM_READ16(src++);
CHANGE_PC(cpustate, dst);
CHANGE_PC(dst);
/* TODO: if you soft reset on Taito JC it tries to do a 0x7802->0x9007 (0xff00) transfer. */
for (i=0; i < (length & 0x7ff); i++)
{
UINT16 data = DM_READ16(cpustate, src++);
PM_WRITE16(cpustate, dst++, data);
UINT16 data = DM_READ16(src++);
PM_WRITE16(dst++, data);
}
}
static void check_interrupts(tms32051_state *cpustate)
void tms32051_device::check_interrupts()
{
int i;
if (cpustate->st0.intm == 0 && cpustate->ifr != 0)
if (m_st0.intm == 0 && m_ifr != 0)
{
for (i=0; i < 16; i++)
{
if (cpustate->ifr & (1 << i))
if (m_ifr & (1 << i))
{
cpustate->st0.intm = 1;
PUSH_STACK(cpustate, cpustate->pc);
m_st0.intm = 1;
PUSH_STACK(m_pc);
cpustate->pc = (cpustate->pmst.iptr << 11) | ((i+1) << 1);
cpustate->ifr &= ~(1 << i);
m_pc = (m_pmst.iptr << 11) | ((i+1) << 1);
m_ifr &= ~(1 << i);
save_interrupt_context(cpustate);
save_interrupt_context();
break;
}
}
}
}
static void save_interrupt_context(tms32051_state *cpustate)
void tms32051_device::save_interrupt_context()
{
cpustate->shadow.acc = cpustate->acc;
cpustate->shadow.accb = cpustate->accb;
cpustate->shadow.arcr = cpustate->arcr;
cpustate->shadow.indx = cpustate->indx;
cpustate->shadow.preg = cpustate->preg;
cpustate->shadow.treg0 = cpustate->treg0;
cpustate->shadow.treg1 = cpustate->treg1;
cpustate->shadow.treg2 = cpustate->treg2;
memcpy(&cpustate->shadow.pmst, &cpustate->pmst, sizeof(PMST));
memcpy(&cpustate->shadow.st0, &cpustate->st0, sizeof(ST0));
memcpy(&cpustate->shadow.st1, &cpustate->st1, sizeof(ST1));
m_shadow.acc = m_acc;
m_shadow.accb = m_accb;
m_shadow.arcr = m_arcr;
m_shadow.indx = m_indx;
m_shadow.preg = m_preg;
m_shadow.treg0 = m_treg0;
m_shadow.treg1 = m_treg1;
m_shadow.treg2 = m_treg2;
memcpy(&m_shadow.pmst, &m_pmst, sizeof(TMS32051_PMST));
memcpy(&m_shadow.st0, &m_st0, sizeof(TMS32051_ST0));
memcpy(&m_shadow.st1, &m_st1, sizeof(TMS32051_ST1));
}
static void restore_interrupt_context(tms32051_state *cpustate)
void tms32051_device::restore_interrupt_context()
{
cpustate->acc = cpustate->shadow.acc;
cpustate->accb = cpustate->shadow.accb;
cpustate->arcr = cpustate->shadow.arcr;
cpustate->indx = cpustate->shadow.indx;
cpustate->preg = cpustate->shadow.preg;
cpustate->treg0 = cpustate->shadow.treg0;
cpustate->treg1 = cpustate->shadow.treg1;
cpustate->treg2 = cpustate->shadow.treg2;
memcpy(&cpustate->pmst, &cpustate->shadow.pmst, sizeof(PMST));
memcpy(&cpustate->st0, &cpustate->shadow.st0, sizeof(ST0));
memcpy(&cpustate->st1, &cpustate->shadow.st1, sizeof(ST1));
m_acc = m_shadow.acc;
m_accb = m_shadow.accb;
m_arcr = m_shadow.arcr;
m_indx = m_shadow.indx;
m_preg = m_shadow.preg;
m_treg0 = m_shadow.treg0;
m_treg1 = m_shadow.treg1;
m_treg2 = m_shadow.treg2;
memcpy(&m_pmst, &m_shadow.pmst, sizeof(TMS32051_PMST));
memcpy(&m_st0, &m_shadow.st0, sizeof(TMS32051_ST0));
memcpy(&m_st1, &m_shadow.st1, sizeof(TMS32051_ST1));
}
static void tms_interrupt(tms32051_state *cpustate, int irq)
void tms32051_device::execute_set_input(int irq, int state)
{
if ((cpustate->imr & (1 << irq)) != 0)
if ( state == ASSERT_LINE )
{
cpustate->ifr |= 1 << irq;
if ((m_imr & (1 << irq)) != 0)
{
m_ifr |= 1 << irq;
}
check_interrupts();
}
check_interrupts(cpustate);
}
static CPU_EXIT( tms )
{
/* TODO */
}
static CPU_EXECUTE( tms )
void tms32051_device::execute_run()
{
tms32051_state *cpustate = get_safe_token(device);
while(cpustate->icount > 0)
while(m_icount > 0)
{
UINT16 ppc;
// handle block repeat
if (cpustate->pmst.braf)
if (m_pmst.braf)
{
if (cpustate->pc == cpustate->paer)
if (m_pc == m_paer)
{
if (cpustate->brcr > 0)
if (m_brcr > 0)
{
CHANGE_PC(cpustate, cpustate->pasr);
CHANGE_PC(m_pasr);
}
cpustate->brcr--;
if (cpustate->brcr <= 0)
m_brcr--;
if (m_brcr <= 0)
{
cpustate->pmst.braf = 0;
m_pmst.braf = 0;
}
}
}
ppc = cpustate->pc;
debugger_instruction_hook(device, cpustate->pc);
ppc = m_pc;
debugger_instruction_hook(this, m_pc);
cpustate->op = ROPCODE(cpustate);
tms32051_opcode_table[cpustate->op >> 8](cpustate);
m_op = ROPCODE();
(this->*s_opcode_table[m_op >> 8])();
// handle single repeat
if (cpustate->rptc > 0)
if (m_rptc > 0)
{
if (ppc == cpustate->rpt_end)
if (ppc == m_rpt_end)
{
CHANGE_PC(cpustate, cpustate->rpt_start);
cpustate->rptc--;
CHANGE_PC(m_rpt_start);
m_rptc--;
}
}
else
{
cpustate->rptc = 0;
m_rptc = 0;
}
cpustate->timer.psc--;
if (cpustate->timer.psc <= 0)
m_timer.psc--;
if (m_timer.psc <= 0)
{
cpustate->timer.psc = cpustate->timer.tddr;
cpustate->timer.tim--;
if (cpustate->timer.tim <= 0)
m_timer.psc = m_timer.tddr;
m_timer.tim--;
if (m_timer.tim <= 0)
{
// reset timer
cpustate->timer.tim = cpustate->timer.prd;
m_timer.tim = m_timer.prd;
tms_interrupt(cpustate, INTERRUPT_TINT);
execute_set_input(INTERRUPT_TINT, ASSERT_LINE);
}
}
}
@ -410,68 +379,64 @@ static CPU_EXECUTE( tms )
/*****************************************************************************/
static READ16_HANDLER( cpuregs_r )
READ16_MEMBER( tms32051_device::cpuregs_r )
{
tms32051_state *cpustate = get_safe_token(&space.device());
switch (offset)
{
case 0x04: return cpustate->imr;
case 0x06: return cpustate->ifr;
case 0x04: return m_imr;
case 0x06: return m_ifr;
case 0x07: // PMST
{
UINT16 r = 0;
r |= cpustate->pmst.iptr << 11;
r |= cpustate->pmst.avis << 7;
r |= cpustate->pmst.ovly << 5;
r |= cpustate->pmst.ram << 4;
r |= cpustate->pmst.mpmc << 3;
r |= cpustate->pmst.ndx << 2;
r |= cpustate->pmst.trm << 1;
r |= cpustate->pmst.braf << 0;
r |= m_pmst.iptr << 11;
r |= m_pmst.avis << 7;
r |= m_pmst.ovly << 5;
r |= m_pmst.ram << 4;
r |= m_pmst.mpmc << 3;
r |= m_pmst.ndx << 2;
r |= m_pmst.trm << 1;
r |= m_pmst.braf << 0;
return r;
}
case 0x09: return cpustate->brcr;
case 0x10: return cpustate->ar[0];
case 0x11: return cpustate->ar[1];
case 0x12: return cpustate->ar[2];
case 0x13: return cpustate->ar[3];
case 0x14: return cpustate->ar[4];
case 0x15: return cpustate->ar[5];
case 0x16: return cpustate->ar[6];
case 0x17: return cpustate->ar[7];
case 0x1e: return cpustate->cbcr;
case 0x1f: return cpustate->bmar;
case 0x24: return cpustate->timer.tim;
case 0x25: return cpustate->timer.prd;
case 0x09: return m_brcr;
case 0x10: return m_ar[0];
case 0x11: return m_ar[1];
case 0x12: return m_ar[2];
case 0x13: return m_ar[3];
case 0x14: return m_ar[4];
case 0x15: return m_ar[5];
case 0x16: return m_ar[6];
case 0x17: return m_ar[7];
case 0x1e: return m_cbcr;
case 0x1f: return m_bmar;
case 0x24: return m_timer.tim;
case 0x25: return m_timer.prd;
case 0x26: // TCR
{
UINT16 r = 0;
r |= (cpustate->timer.psc & 0xf) << 6;
r |= (cpustate->timer.tddr & 0xf);
r |= (m_timer.psc & 0xf) << 6;
r |= (m_timer.tddr & 0xf);
return r;
}
case 0x28: return 0; // PDWSR
default:
if(!space.debugger_access())
fatalerror("32051: cpuregs_r: unimplemented memory-mapped register %02X at %04X\n", offset, cpustate->pc-1);
fatalerror("32051: cpuregs_r: unimplemented memory-mapped register %02X at %04X\n", offset, m_pc-1);
}
return 0;
}
static WRITE16_HANDLER( cpuregs_w )
WRITE16_MEMBER( tms32051_device::cpuregs_w )
{
tms32051_state *cpustate = get_safe_token(&space.device());
switch (offset)
{
case 0x00: break;
case 0x04: cpustate->imr = data; break;
case 0x04: m_imr = data; break;
case 0x06: // IFR
{
int i;
@ -479,7 +444,7 @@ static WRITE16_HANDLER( cpuregs_w )
{
if (data & (1 << i))
{
cpustate->ifr &= ~(1 << i);
m_ifr &= ~(1 << i);
}
}
break;
@ -487,48 +452,48 @@ static WRITE16_HANDLER( cpuregs_w )
case 0x07: // PMST
{
cpustate->pmst.iptr = (data >> 11) & 0x1f;
cpustate->pmst.avis = (data & 0x80) ? 1 : 0;
cpustate->pmst.ovly = (data & 0x20) ? 1 : 0;
cpustate->pmst.ram = (data & 0x10) ? 1 : 0;
cpustate->pmst.mpmc = (data & 0x08) ? 1 : 0;
cpustate->pmst.ndx = (data & 0x04) ? 1 : 0;
cpustate->pmst.trm = (data & 0x02) ? 1 : 0;
cpustate->pmst.braf = (data & 0x01) ? 1 : 0;
m_pmst.iptr = (data >> 11) & 0x1f;
m_pmst.avis = (data & 0x80) ? 1 : 0;
m_pmst.ovly = (data & 0x20) ? 1 : 0;
m_pmst.ram = (data & 0x10) ? 1 : 0;
m_pmst.mpmc = (data & 0x08) ? 1 : 0;
m_pmst.ndx = (data & 0x04) ? 1 : 0;
m_pmst.trm = (data & 0x02) ? 1 : 0;
m_pmst.braf = (data & 0x01) ? 1 : 0;
break;
}
case 0x09: cpustate->brcr = data; break;
case 0x0e: cpustate->treg2 = data; break;
case 0x0f: cpustate->dbmr = data; break;
case 0x10: cpustate->ar[0] = data; break;
case 0x11: cpustate->ar[1] = data; break;
case 0x12: cpustate->ar[2] = data; break;
case 0x13: cpustate->ar[3] = data; break;
case 0x14: cpustate->ar[4] = data; break;
case 0x15: cpustate->ar[5] = data; break;
case 0x16: cpustate->ar[6] = data; break;
case 0x17: cpustate->ar[7] = data; break;
case 0x18: cpustate->indx = data; break;
case 0x19: cpustate->arcr = data; break;
case 0x1a: cpustate->cbsr1 = data; break;
case 0x1b: cpustate->cber1 = data; break;
case 0x1c: cpustate->cbsr2 = data; break;
case 0x1d: cpustate->cber2 = data; break;
case 0x1e: cpustate->cbcr = data; break;
case 0x1f: cpustate->bmar = data; break;
case 0x24: cpustate->timer.tim = data; break;
case 0x25: cpustate->timer.prd = data; break;
case 0x09: m_brcr = data; break;
case 0x0e: m_treg2 = data; break;
case 0x0f: m_dbmr = data; break;
case 0x10: m_ar[0] = data; break;
case 0x11: m_ar[1] = data; break;
case 0x12: m_ar[2] = data; break;
case 0x13: m_ar[3] = data; break;
case 0x14: m_ar[4] = data; break;
case 0x15: m_ar[5] = data; break;
case 0x16: m_ar[6] = data; break;
case 0x17: m_ar[7] = data; break;
case 0x18: m_indx = data; break;
case 0x19: m_arcr = data; break;
case 0x1a: m_cbsr1 = data; break;
case 0x1b: m_cber1 = data; break;
case 0x1c: m_cbsr2 = data; break;
case 0x1d: m_cber2 = data; break;
case 0x1e: m_cbcr = data; break;
case 0x1f: m_bmar = data; break;
case 0x24: m_timer.tim = data; break;
case 0x25: m_timer.prd = data; break;
case 0x26: // TCR
{
cpustate->timer.tddr = data & 0xf;
cpustate->timer.psc = (data >> 6) & 0xf;
m_timer.tddr = data & 0xf;
m_timer.psc = (data >> 6) & 0xf;
if (data & 0x20)
{
cpustate->timer.tim = cpustate->timer.prd;
cpustate->timer.psc = cpustate->timer.tddr;
m_timer.tim = m_timer.prd;
m_timer.psc = m_timer.tddr;
}
break;
}
@ -536,215 +501,23 @@ static WRITE16_HANDLER( cpuregs_w )
case 0x28: break; // PDWSR
default:
if(!space.debugger_access())
fatalerror("32051: cpuregs_w: unimplemented memory-mapped register %02X, data %04X at %04X\n", offset, data, cpustate->pc-1);
fatalerror("32051: cpuregs_w: unimplemented memory-mapped register %02X, data %04X at %04X\n", offset, data, m_pc-1);
}
}
/**************************************************************************
* Internal memory map
**************************************************************************/
static ADDRESS_MAP_START( internal_pgm, AS_PROGRAM, 16, legacy_cpu_device )
AM_RANGE(0x0000, 0x1fff) AM_ROM // ROM TODO: is off-chip if MP/_MC = 0
AM_RANGE(0x2000, 0x23ff) AM_RAM AM_SHARE("saram") // SARAM TODO: is off-chip if RAM bit = 0
AM_RANGE(0xfe00, 0xffff) AM_RAM AM_SHARE("daram_b0") // DARAM B0 TODO: is off-chip if CNF = 0
ADDRESS_MAP_END
bool tms32051_device::memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value)
static ADDRESS_MAP_START( internal_data, AS_DATA, 16, legacy_cpu_device )
AM_RANGE(0x0000, 0x005f) AM_READWRITE_LEGACY(cpuregs_r, cpuregs_w)
AM_RANGE(0x0060, 0x007f) AM_RAM // DARAM B2
AM_RANGE(0x0100, 0x02ff) AM_RAM AM_SHARE("daram_b0") // DARAM B0 TODO: is unconnected if CNF = 1
AM_RANGE(0x0300, 0x04ff) AM_RAM // DARAM B1
AM_RANGE(0x0800, 0x0bff) AM_RAM AM_SHARE("saram") // SARAM TODO: is off-chip if OVLY = 0
ADDRESS_MAP_END
/**************************************************************************
* Generic set_info
**************************************************************************/
static CPU_SET_INFO( tms )
{
tms32051_state *cpustate = get_safe_token(device);
switch (state)
{
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + TMS32051_PC: cpustate->pc = info->i; break;
}
}
static CPU_READ( tms )
{
tms32051_state *cpustate = get_safe_token(device);
/* TODO: alignment if offset is odd */
if (space == AS_PROGRAM)
if (spacenum == AS_PROGRAM)
{
*value = (PM_READ16(cpustate, offset>>1));
value = (PM_READ16(offset>>1));
}
else if (space == AS_DATA)
else if (spacenum == AS_DATA)
{
*value = (DM_READ16(cpustate, offset>>1));
value = (DM_READ16(offset>>1));
}
return 1;
}
static CPU_GET_INFO( tms )
{
tms32051_state *cpustate = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL;
switch(state)
{
/* --- the following bits of info are returned as 64-bit signed integers --- */
case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(tms32051_state); break;
case CPUINFO_INT_INPUT_LINES: info->i = 6; break;
case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break;
case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break;
case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break;
case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break;
case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break;
case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 4; break;
case CPUINFO_INT_MIN_CYCLES: info->i = 1; break;
case CPUINFO_INT_MAX_CYCLES: info->i = 5; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = -1; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 16; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = -1; break;
case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 0; break;
case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break;
case CPUINFO_INT_INPUT_STATE: info->i = CLEAR_LINE; break;
case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break;
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + TMS32051_PC: info->i = cpustate->pc; break;
case CPUINFO_INT_REGISTER + TMS32051_ACC: info->i = cpustate->acc; break;
case CPUINFO_INT_REGISTER + TMS32051_ACCB: info->i = cpustate->accb; break;
case CPUINFO_INT_REGISTER + TMS32051_PREG: info->i = cpustate->preg; break;
case CPUINFO_INT_REGISTER + TMS32051_TREG0: info->i = cpustate->treg0; break;
case CPUINFO_INT_REGISTER + TMS32051_TREG1: info->i = cpustate->treg1; break;
case CPUINFO_INT_REGISTER + TMS32051_TREG2: info->i = cpustate->treg2; break;
case CPUINFO_INT_REGISTER + TMS32051_BMAR: info->i = cpustate->bmar; break;
case CPUINFO_INT_REGISTER + TMS32051_RPTC: info->i = cpustate->rptc; break;
case CPUINFO_INT_REGISTER + TMS32051_BRCR: info->i = cpustate->brcr; break;
case CPUINFO_INT_REGISTER + TMS32051_INDX: info->i = cpustate->indx; break;
case CPUINFO_INT_REGISTER + TMS32051_DBMR: info->i = cpustate->dbmr; break;
case CPUINFO_INT_REGISTER + TMS32051_ARCR: info->i = cpustate->arcr; break;
case CPUINFO_INT_REGISTER + TMS32051_DP: info->i = cpustate->st0.dp; break;
case CPUINFO_INT_REGISTER + TMS32051_ARP: info->i = cpustate->st0.arp; break;
case CPUINFO_INT_REGISTER + TMS32051_ARB: info->i = cpustate->st1.arb; break;
case CPUINFO_INT_REGISTER + TMS32051_AR0: info->i = cpustate->ar[0]; break;
case CPUINFO_INT_REGISTER + TMS32051_AR1: info->i = cpustate->ar[1]; break;
case CPUINFO_INT_REGISTER + TMS32051_AR2: info->i = cpustate->ar[2]; break;
case CPUINFO_INT_REGISTER + TMS32051_AR3: info->i = cpustate->ar[3]; break;
case CPUINFO_INT_REGISTER + TMS32051_AR4: info->i = cpustate->ar[4]; break;
case CPUINFO_INT_REGISTER + TMS32051_AR5: info->i = cpustate->ar[5]; break;
case CPUINFO_INT_REGISTER + TMS32051_AR6: info->i = cpustate->ar[6]; break;
case CPUINFO_INT_REGISTER + TMS32051_AR7: info->i = cpustate->ar[7]; break;
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(tms); break;
case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(tms); break;
case CPUINFO_FCT_EXIT: info->exit = CPU_EXIT_NAME(tms); break;
case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(tms); break;
case CPUINFO_FCT_BURN: info->burn = NULL; break;
case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(tms32051); break;
case CPUINFO_FCT_READ: info->read = CPU_READ_NAME(tms); break;
case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break;
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map16 = ADDRESS_MAP_NAME(internal_pgm); break;
case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_DATA: info->internal_map16 = ADDRESS_MAP_NAME(internal_data); break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_FAMILY: strcpy(info->s, "TMS3205x"); break;
case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break;
case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break;
case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright Ville Linde"); break;
case CPUINFO_STR_FLAGS: strcpy(info->s, " "); break;
case CPUINFO_STR_REGISTER + TMS32051_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break;
case CPUINFO_STR_REGISTER + TMS32051_ACC: sprintf(info->s, "ACC: %08X", cpustate->acc); break;
case CPUINFO_STR_REGISTER + TMS32051_ACCB: sprintf(info->s, "ACCB: %08X", cpustate->accb); break;
case CPUINFO_STR_REGISTER + TMS32051_PREG: sprintf(info->s, "PREG: %08X", cpustate->preg); break;
case CPUINFO_STR_REGISTER + TMS32051_TREG0: sprintf(info->s, "TREG0: %04X", cpustate->treg0); break;
case CPUINFO_STR_REGISTER + TMS32051_TREG1: sprintf(info->s, "TREG1: %04X", cpustate->treg1); break;
case CPUINFO_STR_REGISTER + TMS32051_TREG2: sprintf(info->s, "TREG2: %04X", cpustate->treg2); break;
case CPUINFO_STR_REGISTER + TMS32051_BMAR: sprintf(info->s, "BMAR: %08X", cpustate->bmar); break;
case CPUINFO_STR_REGISTER + TMS32051_RPTC: sprintf(info->s, "RPTC: %08X", cpustate->rptc); break;
case CPUINFO_STR_REGISTER + TMS32051_BRCR: sprintf(info->s, "BRCR: %08X", cpustate->brcr); break;
case CPUINFO_STR_REGISTER + TMS32051_INDX: sprintf(info->s, "INDX: %04X", cpustate->indx); break;
case CPUINFO_STR_REGISTER + TMS32051_DBMR: sprintf(info->s, "DBMR: %04X", cpustate->dbmr); break;
case CPUINFO_STR_REGISTER + TMS32051_ARCR: sprintf(info->s, "ARCR: %04X", cpustate->arcr); break;
case CPUINFO_STR_REGISTER + TMS32051_DP: sprintf(info->s, "DP: %04X", cpustate->st0.dp); break;
case CPUINFO_STR_REGISTER + TMS32051_ARP: sprintf(info->s, "ARP: %04X", cpustate->st0.arp); break;
case CPUINFO_STR_REGISTER + TMS32051_ARB: sprintf(info->s, "ARB: %04X", cpustate->st1.arb); break;
case CPUINFO_STR_REGISTER + TMS32051_AR0: sprintf(info->s, "AR0: %04X", cpustate->ar[0]); break;
case CPUINFO_STR_REGISTER + TMS32051_AR1: sprintf(info->s, "AR1: %04X", cpustate->ar[1]); break;
case CPUINFO_STR_REGISTER + TMS32051_AR2: sprintf(info->s, "AR2: %04X", cpustate->ar[2]); break;
case CPUINFO_STR_REGISTER + TMS32051_AR3: sprintf(info->s, "AR3: %04X", cpustate->ar[3]); break;
case CPUINFO_STR_REGISTER + TMS32051_AR4: sprintf(info->s, "AR4: %04X", cpustate->ar[4]); break;
case CPUINFO_STR_REGISTER + TMS32051_AR5: sprintf(info->s, "AR5: %04X", cpustate->ar[5]); break;
case CPUINFO_STR_REGISTER + TMS32051_AR6: sprintf(info->s, "AR6: %04X", cpustate->ar[6]); break;
case CPUINFO_STR_REGISTER + TMS32051_AR7: sprintf(info->s, "AR7: %04X", cpustate->ar[7]); break;
}
}
static CPU_SET_INFO( tms32051 )
{
tms32051_state *cpustate = get_safe_token(device);
if (state >= CPUINFO_INT_INPUT_STATE && state <= CPUINFO_INT_INPUT_STATE + 5)
{
return;
}
switch(state)
{
case CPUINFO_INT_PC:
case CPUINFO_INT_REGISTER + TMS32051_PC: cpustate->pc = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_ACC: cpustate->acc = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_ACCB: cpustate->accb = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_PREG: cpustate->preg = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_TREG0: cpustate->treg0 = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_TREG1: cpustate->treg1 = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_TREG2: cpustate->treg2 = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_BMAR: cpustate->bmar = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_BRCR: cpustate->brcr = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_INDX: cpustate->indx = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_DBMR: cpustate->dbmr = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_ARCR: cpustate->arcr = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_DP: cpustate->st0.dp = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_ARP: cpustate->st0.arp = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_ARB: cpustate->st1.arb = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_AR0: cpustate->ar[0] = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_AR1: cpustate->ar[1] = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_AR2: cpustate->ar[2] = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_AR3: cpustate->ar[3] = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_AR4: cpustate->ar[4] = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_AR5: cpustate->ar[5] = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_AR6: cpustate->ar[6] = info->i; break;
case CPUINFO_INT_REGISTER + TMS32051_AR7: cpustate->ar[7] = info->i; break;
default: CPU_SET_INFO_CALL(tms); break;
}
}
CPU_GET_INFO( tms32051 )
{
switch(state)
{
/* --- the following bits of info are returned as pointers to data or functions --- */
case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(tms32051); break;
/* --- the following bits of info are returned as NULL-terminated strings --- */
case CPUINFO_STR_NAME: strcpy(info->s, "TMS32051"); break;
case CPUINFO_STR_SHORTNAME: strcpy(info->s, "tms32051"); break;
default: CPU_GET_INFO_CALL(tms); break;
}
}
DEFINE_LEGACY_CPU_DEVICE(TMS32051, tms32051);

343
src/emu/cpu/tms32051/tms32051.h
View File

@ -3,8 +3,347 @@
#ifndef __TMS32051_H__
#define __TMS32051_H__
DECLARE_LEGACY_CPU_DEVICE(TMS32051, tms32051);
CPU_DISASSEMBLE( tms32051 );
struct TMS32051_PMST
{
UINT16 iptr;
UINT16 avis;
UINT16 ovly;
UINT16 ram;
UINT16 mpmc;
UINT16 ndx;
UINT16 trm;
UINT16 braf;
};
struct TMS32051_ST0
{
UINT16 dp;
UINT16 intm;
UINT16 ovm;
UINT16 ov;
UINT16 arp;
};
struct TMS32051_ST1
{
UINT16 arb;
UINT16 cnf;
UINT16 tc;
UINT16 sxm;
UINT16 c;
UINT16 hm;
UINT16 xf;
UINT16 pm;
};
class tms32051_device : public cpu_device
{
public:
// construction/destruction
tms32051_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
DECLARE_READ16_MEMBER( cpuregs_r );
DECLARE_WRITE16_MEMBER( cpuregs_w );
protected:
// device-level overrides
virtual void device_start();
virtual void device_reset();
// device_execute_interface overrides
virtual UINT32 execute_min_cycles() const { return 1; }
virtual UINT32 execute_max_cycles() const { return 5; }
virtual UINT32 execute_input_lines() const { return 6; }
virtual void execute_run();
virtual void execute_set_input(int inputnum, int state);
// device_memory_interface overrides
virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ); }
virtual bool memory_read(address_spacenum spacenum, offs_t offset, int size, UINT64 &value);
// device_disasm_interface overrides
virtual UINT32 disasm_min_opcode_bytes() const { return 2; }
virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
private:
address_space_config m_program_config;
address_space_config m_data_config;
typedef void ( tms32051_device::*opcode_func )();
static const opcode_func s_opcode_table[256];
static const opcode_func s_opcode_table_be[256];
static const opcode_func s_opcode_table_bf[256];
UINT16 m_pc;
UINT16 m_op;
INT32 m_acc;
INT32 m_accb;
INT32 m_preg;
UINT16 m_treg0;
UINT16 m_treg1;
UINT16 m_treg2;
UINT16 m_ar[8];
INT32 m_rptc;
UINT16 m_bmar;
INT32 m_brcr;
UINT16 m_paer;
UINT16 m_pasr;
UINT16 m_indx;
UINT16 m_dbmr;
UINT16 m_arcr;
TMS32051_ST0 m_st0;
TMS32051_ST1 m_st1;
TMS32051_PMST m_pmst;
UINT16 m_ifr;
UINT16 m_imr;
UINT16 m_pcstack[8];
int m_pcstack_ptr;
UINT16 m_rpt_start, m_rpt_end;
UINT16 m_cbcr;
UINT16 m_cbsr1;
UINT16 m_cber1;
UINT16 m_cbsr2;
UINT16 m_cber2;
struct
{
int tddr;
int psc;
UINT16 tim;
UINT16 prd;
} m_timer;
struct
{
INT32 acc;
INT32 accb;
UINT16 arcr;
UINT16 indx;
TMS32051_PMST pmst;
INT32 preg;
TMS32051_ST0 st0;
TMS32051_ST1 st1;
INT32 treg0;
INT32 treg1;
INT32 treg2;
} m_shadow;
address_space *m_program;
direct_read_data *m_direct;
address_space *m_data;
int m_icount;
inline void CHANGE_PC(UINT16 new_pc);
inline UINT16 PM_READ16(UINT16 address);
inline void PM_WRITE16(UINT16 address, UINT16 data);
inline UINT16 DM_READ16(UINT16 address);
inline void DM_WRITE16(UINT16 address, UINT16 data);
inline void PUSH_STACK(UINT16 pc);
inline UINT16 POP_STACK();
inline INT32 SUB(UINT32 a, UINT32 b);
inline INT32 ADD(UINT32 a, UINT32 b);
inline void UPDATE_AR(int ar, int step);
inline void UPDATE_ARP(int nar);
UINT16 GET_ADDRESS();
inline int GET_ZLVC_CONDITION(int zlvc, int zlvc_mask);
inline int GET_TP_CONDITION(int tp);
inline INT32 PREG_PSCALER(INT32 preg);
void op_invalid();
void op_abs();
void op_adcb();
void op_add_mem();
void op_add_simm();
void op_add_limm();
void op_add_s16_mem();
void op_addb();
void op_addc();
void op_adds();
void op_addt();
void op_and_mem();
void op_and_limm();
void op_and_s16_limm();
void op_andb();
void op_bsar();
void op_cmpl();
void op_crgt();
void op_crlt();
void op_exar();
void op_lacb();
void op_lacc_mem();
void op_lacc_limm();
void op_lacc_s16_mem();
void op_lacl_simm();
void op_lacl_mem();
void op_lact();
void op_lamm();
void op_neg();
void op_norm();
void op_or_mem();
void op_or_limm();
void op_or_s16_limm();
void op_orb();
void op_rol();
void op_rolb();
void op_ror();
void op_rorb();
void op_sacb();
void op_sach();
void op_sacl();
void op_samm();
void op_sath();
void op_satl();
void op_sbb();
void op_sbbb();
void op_sfl();
void op_sflb();
void op_sfr();
void op_sfrb();
void op_sub_mem();
void op_sub_s16_mem();
void op_sub_simm();
void op_sub_limm();
void op_subb();
void op_subc();
void op_subs();
void op_subt();
void op_xor_mem();
void op_xor_limm();
void op_xor_s16_limm();
void op_xorb();
void op_zalr();
void op_zap();
void op_adrk();
void op_cmpr();
void op_lar_mem();
void op_lar_simm();
void op_lar_limm();
void op_ldp_mem();
void op_ldp_imm();
void op_mar();
void op_sar();
void op_sbrk();
void op_b();
void op_bacc();
void op_baccd();
void op_banz();
void op_banzd();
void op_bcnd();
void op_bcndd();
void op_bd();
void op_cala();
void op_calad();
void op_call();
void op_calld();
void op_cc();
void op_ccd();
void op_intr();
void op_nmi();
void op_retc();
void op_retcd();
void op_rete();
void op_reti();
void op_trap();
void op_xc();
void op_bldd_slimm();
void op_bldd_dlimm();
void op_bldd_sbmar();
void op_bldd_dbmar();
void op_bldp();
void op_blpd_bmar();
void op_blpd_imm();
void op_dmov();
void op_in();
void op_lmmr();
void op_out();
void op_smmr();
void op_tblr();
void op_tblw();
void op_apl_dbmr();
void op_apl_imm();
void op_cpl_dbmr();
void op_cpl_imm();
void op_opl_dbmr();
void op_opl_imm();
void op_splk();
void op_xpl_dbmr();
void op_xpl_imm();
void op_apac();
void op_lph();
void op_lt();
void op_lta();
void op_ltd();
void op_ltp();
void op_lts();
void op_mac();
void op_macd();
void op_madd();
void op_mads();
void op_mpy_mem();
void op_mpy_simm();
void op_mpy_limm();
void op_mpya();
void op_mpys();
void op_mpyu();
void op_pac();
void op_spac();
void op_sph();
void op_spl();
void op_spm();
void op_sqra();
void op_sqrs();
void op_zpr();
void op_bit();
void op_bitt();
void op_clrc_ov();
void op_clrc_ext();
void op_clrc_hold();
void op_clrc_tc();
void op_clrc_carry();
void op_clrc_cnf();
void op_clrc_intm();
void op_clrc_xf();
void op_idle();
void op_idle2();
void op_lst_st0();
void op_lst_st1();
void op_pop();
void op_popd();
void op_pshd();
void op_push();
void op_rpt_mem();
void op_rpt_limm();
void op_rpt_simm();
void op_rptb();
void op_rptz();
void op_setc_ov();
void op_setc_ext();
void op_setc_hold();
void op_setc_tc();
void op_setc_carry();
void op_setc_xf();
void op_setc_cnf();
void op_setc_intm();
void op_sst_st0();
void op_sst_st1();
void op_group_be();
void op_group_bf();
void delay_slot(UINT16 startpc);
void check_interrupts();
void save_interrupt_context();
void restore_interrupt_context();
};
extern const device_type TMS32051;
#endif /* __TMS32051_H__ */