From aefabca2f9be46b764d0f49f7ccfe3356c4627db Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C3=ABl=20Banaan=20Ananas?= Date: Sun, 15 Jul 2012 16:35:50 +0000 Subject: [PATCH] on 'C2x-compatible opcodes that set treg(0), treg1/2 are set too if TRM=0 --- src/emu/cpu/tms32051/32051ops.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/src/emu/cpu/tms32051/32051ops.c b/src/emu/cpu/tms32051/32051ops.c index 6127c637bc6..f6c9b06390d 100644 --- a/src/emu/cpu/tms32051/32051ops.c +++ b/src/emu/cpu/tms32051/32051ops.c @@ -1493,6 +1493,11 @@ static void op_lt(tms32051_state *cpustate) UINT16 data = DM_READ16(cpustate, ea); cpustate->treg0 = data; + if (cpustate->pmst.trm == 0) + { + cpustate->treg1 = data; + cpustate->treg2 = data; + } CYCLES(1); } @@ -1506,6 +1511,11 @@ static void op_lta(tms32051_state *cpustate) cpustate->treg0 = data; spreg = PREG_PSCALER(cpustate, cpustate->preg); cpustate->acc = ADD(cpustate, cpustate->acc, spreg, 0); + if (cpustate->pmst.trm == 0) + { + cpustate->treg1 = data; + cpustate->treg2 = data; + } CYCLES(1); }