Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-06-05 04:16:28 +03:00
Code Issues Actions 5 Packages Projects Releases Wiki Activity

From: Atari Ace [atari_ace@verizon.net]

Browse Source 
Sent: Friday, December 12, 2008 9:28 AM
To: submit@mamedev.org
Cc: atariace@hotmail.com
Subject: [patch] yet another small Machine cleanup

Hi mamedev,

This patch modifies the tms34010.h, pc16552.h, and tms34061.h
interfaces to eliminate some more global Machine variables.  Six more
deprecat.h includes eliminated.

FYI, 128u5 had 523 deprecat.h includes and ~1400 Machine variables,
now were down to 374 and ~420 respectively, so progress is being made.

~aa
This commit is contained in:
Aaron Giles 2008-12-14 08:15:01 +00:00
parent 9acb30bcbe
commit af1273c18d
32 changed files with 103 additions and 109 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/emu/cpu/tms34010/34010gfx.c
View File

@ -205,7 +205,7 @@ static void shiftreg_w(const address_space *space, offs_t offset,UINT16 data)
{
tms34010_state *tms = space->cpu->token;
if (tms->config->from_shiftreg)
(*tms->config->from_shiftreg)((UINT32)(offset << 3) & ~15, &tms->shiftreg[0]);
(*tms->config->from_shiftreg)(space, (UINT32)(offset << 3) & ~15, &tms->shiftreg[0]);
else
logerror("From ShiftReg function not set. PC = %08X\n", tms->pc);
}
@ -214,7 +214,7 @@ static UINT16 shiftreg_r(const address_space *space, offs_t offset)
{
tms34010_state *tms = space->cpu->token;
if (tms->config->to_shiftreg)
(*tms->config->to_shiftreg)((UINT32)(offset << 3) & ~15, &tms->shiftreg[0]);
(*tms->config->to_shiftreg)(space, (UINT32)(offset << 3) & ~15, &tms->shiftreg[0]);
else
logerror("To ShiftReg function not set. PC = %08X\n", tms->pc);
return tms->shiftreg[0];

12
src/emu/cpu/tms34010/tms34010.c
View File

@ -313,7 +313,7 @@ static UINT32 read_pixel_32(tms34010_state *tms, offs_t offset)
static UINT32 read_pixel_shiftreg(tms34010_state *tms, offs_t offset)
{
if (tms->config->to_shiftreg)
tms->config->to_shiftreg(offset, &tms->shiftreg[0]);
tms->config->to_shiftreg(tms->program, offset, &tms->shiftreg[0]);
else
fatalerror("To ShiftReg function not set. PC = %08X\n", tms->pc);
return tms->shiftreg[0];
@ -457,7 +457,7 @@ static void write_pixel_r_t_32(tms34010_state *tms, offs_t offset, UINT32 data)
static void write_pixel_shiftreg(tms34010_state *tms, offs_t offset, UINT32 data)
{
if (tms->config->from_shiftreg)
tms->config->from_shiftreg(offset, &tms->shiftreg[0]);
tms->config->from_shiftreg(tms->program, offset, &tms->shiftreg[0]);
else
fatalerror("From ShiftReg function not set. PC = %08X\n", tms->pc);
}
@ -1214,12 +1214,12 @@ WRITE16_HANDLER( tms34010_io_register_w )
if (!(oldreg & 0x0080) && (newreg & 0x0080))
{
if (tms->config->output_int)
(*tms->config->output_int)(1);
(*tms->config->output_int)(space->cpu, 1);
}
else if ((oldreg & 0x0080) && !(newreg & 0x0080))
{
if (tms->config->output_int)
(*tms->config->output_int)(0);
(*tms->config->output_int)(space->cpu, 0);
}
/* input interrupt? (should really be state-based, but the functions don't exist!) */
@ -1365,12 +1365,12 @@ WRITE16_HANDLER( tms34020_io_register_w )
if (!(oldreg & 0x0080) && (newreg & 0x0080))
{
if (tms->config->output_int)
(*tms->config->output_int)(1);
(*tms->config->output_int)(space->cpu, 1);
}
else if ((oldreg & 0x0080) && !(newreg & 0x0080))
{
if (tms->config->output_int)
(*tms->config->output_int)(0);
(*tms->config->output_int)(space->cpu, 0);
}
/* input interrupt? (should really be state-based, but the functions don't exist!) */

6
src/emu/cpu/tms34010/tms34010.h
View File

@ -196,9 +196,9 @@ struct _tms34010_config
UINT32 pixclock; /* the pixel clock (0 means don't adjust screen size) */
int pixperclock; /* pixels per clock */
void (*scanline_callback)(const device_config *screen, bitmap_t *bitmap, int scanline, const tms34010_display_params *params);
void (*output_int)(int state); /* output interrupt callback */
void (*to_shiftreg)(offs_t, UINT16 *); /* shift register write */
void (*from_shiftreg)(offs_t, UINT16 *); /* shift register read */
void (*output_int)(const device_config *device, int state); /* output interrupt callback */
void (*to_shiftreg)(const address_space *space, offs_t, UINT16 *); /* shift register write */
void (*from_shiftreg)(const address_space *space, offs_t, UINT16 *); /* shift register read */
};

7
src/emu/machine/pc16552d.c
View File

@ -6,7 +6,6 @@
*/
#include "driver.h"
#include "deprecat.h"
#include "pc16552d.h"
#define REG_RECV_BUFFER 0x0 // Read
@ -388,7 +387,7 @@ static void duart_w(running_machine *machine, int chip, int reg, UINT8 data)
/*****************************************************************************/
void pc16552d_init(int chip, int frequency, void (* irq_handler)(running_machine *machine, int channel, int value), void (* tx_callback)(int channel, int count, UINT8* data))
void pc16552d_init(running_machine *machine, int chip, int frequency, void (* irq_handler)(running_machine *machine, int channel, int value), void (* tx_callback)(int channel, int count, UINT8* data))
{
memset(&duart[chip], 0, sizeof(PC16552D_REGS));
@ -401,10 +400,10 @@ void pc16552d_init(int chip, int frequency, void (* irq_handler)(running_machine
duart[chip].ch[1].pending_interrupt = 0;
// allocate transmit timers
duart[chip].ch[0].tx_fifo_timer = timer_alloc(Machine, tx_fifo_timer_callback, NULL);
duart[chip].ch[0].tx_fifo_timer = timer_alloc(machine, tx_fifo_timer_callback, NULL);
timer_adjust_oneshot(duart[chip].ch[0].tx_fifo_timer, attotime_never, (chip * 2) + 0);
duart[chip].ch[1].tx_fifo_timer = timer_alloc(Machine, tx_fifo_timer_callback, NULL);
duart[chip].ch[1].tx_fifo_timer = timer_alloc(machine, tx_fifo_timer_callback, NULL);
timer_adjust_oneshot(duart[chip].ch[1].tx_fifo_timer, attotime_never, (chip * 2) + 1);
}

2
src/emu/machine/pc16552d.h
View File

@ -1,7 +1,7 @@
#ifndef PC16552D_H
#define PC16552D_H
void pc16552d_init(int chip, int frequency, void (* irq_handler)(running_machine *machine, int channel, int value), void (* tx_callback)(int channel, int count, UINT8* data));
void pc16552d_init(running_machine *machine, int chip, int frequency, void (* irq_handler)(running_machine *machine, int channel, int value), void (* tx_callback)(int channel, int count, UINT8* data));
void pc16552d_rx_data(running_machine *machine, int chip, int channel, UINT8 data);
READ8_HANDLER(pc16552d_0_r);

37
src/emu/video/tms34061.c
View File

@ -11,7 +11,6 @@
****************************************************************************/
#include "driver.h"
#include "deprecat.h"
#include "tms34061.h"
@ -167,7 +166,7 @@ static TIMER_CALLBACK( tms34061_interrupt )
*
*************************************/
static void register_w(offs_t offset, UINT8 data)
static void register_w(const address_space *space, offs_t offset, UINT8 data)
{
int scanline;
int regnum = offset >> 2;
@ -187,7 +186,7 @@ static void register_w(offs_t offset, UINT8 data)
}
/* log it */
if (VERBOSE) logerror("%s:tms34061 %s = %04x\n", cpuexec_describe_context(Machine), regnames[regnum], tms34061.regs[regnum]);
if (VERBOSE) logerror("%s:tms34061 %s = %04x\n", cpuexec_describe_context(space->machine), regnames[regnum], tms34061.regs[regnum]);
/* update the state of things */
switch (regnum)
@ -238,7 +237,7 @@ static void register_w(offs_t offset, UINT8 data)
*
*************************************/
static UINT8 register_r(offs_t offset)
static UINT8 register_r(const address_space *space, offs_t offset)
{
int regnum = offset >> 2;
UINT16 result;
@ -265,7 +264,7 @@ static UINT8 register_r(offs_t offset)
}
/* log it */
if (VERBOSE) logerror("%s:tms34061 %s read = %04X\n", cpuexec_describe_context(Machine), regnames[regnum], result);
if (VERBOSE) logerror("%s:tms34061 %s read = %04X\n", cpuexec_describe_context(space->machine), regnames[regnum], result);
return (offset & 0x02) ? (result >> 8) : result;
}
@ -360,7 +359,7 @@ INLINE void adjust_xyaddress(int offset)
}
static void xypixel_w(int offset, UINT8 data)
static void xypixel_w(const address_space *space, int offset, UINT8 data)
{
/* determine the offset, then adjust it */
offs_t pixeloffs = tms34061.regs[TMS34061_XYADDRESS];
@ -372,7 +371,7 @@ static void xypixel_w(int offset, UINT8 data)
/* mask to the VRAM size */
pixeloffs &= tms34061.vrammask;
if (VERBOSE) logerror("%s:tms34061 xy (%04x) = %02x/%02x\n", cpuexec_describe_context(Machine), pixeloffs, data, tms34061.latchdata);
if (VERBOSE) logerror("%s:tms34061 xy (%04x) = %02x/%02x\n", cpuexec_describe_context(space->machine), pixeloffs, data, tms34061.latchdata);
/* set the pixel data */
tms34061.vram[pixeloffs] = data;
@ -380,7 +379,7 @@ static void xypixel_w(int offset, UINT8 data)
}
static UINT8 xypixel_r(int offset)
static UINT8 xypixel_r(const address_space *space, int offset)
{
/* determine the offset, then adjust it */
offs_t pixeloffs = tms34061.regs[TMS34061_XYADDRESS];
@ -405,7 +404,7 @@ static UINT8 xypixel_r(int offset)
*
*************************************/
void tms34061_w(int col, int row, int func, UINT8 data)
void tms34061_w(const address_space *space, int col, int row, int func, UINT8 data)
{
offs_t offs;
@ -415,12 +414,12 @@ void tms34061_w(int col, int row, int func, UINT8 data)
/* both 0 and 2 map to register access */
case 0:
case 2:
register_w(col, data);
register_w(space, col, data);
break;
/* function 1 maps to XY access; col is the address adjustment */
case 1:
xypixel_w(col, data);
xypixel_w(space, col, data);
break;
/* function 3 maps to direct access */
@ -428,7 +427,7 @@ void tms34061_w(int col, int row, int func, UINT8 data)
offs = ((row << tms34061.intf.rowshift) | col) & tms34061.vrammask;
if (tms34061.regs[TMS34061_CONTROL2] & 0x0040)
offs |= (tms34061.regs[TMS34061_CONTROL2] & 3) << 16;
if (VERBOSE) logerror("%s:tms34061 direct (%04x) = %02x/%02x\n", cpuexec_describe_context(Machine), offs, data, tms34061.latchdata);
if (VERBOSE) logerror("%s:tms34061 direct (%04x) = %02x/%02x\n", cpuexec_describe_context(space->machine), offs, data, tms34061.latchdata);
if (tms34061.vram[offs] != data || tms34061.latchram[offs] != tms34061.latchdata)
{
tms34061.vram[offs] = data;
@ -442,7 +441,7 @@ void tms34061_w(int col, int row, int func, UINT8 data)
if (tms34061.regs[TMS34061_CONTROL2] & 0x0040)
offs |= (tms34061.regs[TMS34061_CONTROL2] & 3) << 16;
offs &= tms34061.vrammask;
if (VERBOSE) logerror("%s:tms34061 shiftreg write (%04x)\n", cpuexec_describe_context(Machine), offs);
if (VERBOSE) logerror("%s:tms34061 shiftreg write (%04x)\n", cpuexec_describe_context(space->machine), offs);
memcpy(&tms34061.vram[offs], tms34061.shiftreg, (size_t)1 << tms34061.intf.rowshift);
memset(&tms34061.latchram[offs], tms34061.latchdata, (size_t)1 << tms34061.intf.rowshift);
@ -454,20 +453,20 @@ void tms34061_w(int col, int row, int func, UINT8 data)
if (tms34061.regs[TMS34061_CONTROL2] & 0x0040)
offs |= (tms34061.regs[TMS34061_CONTROL2] & 3) << 16;
offs &= tms34061.vrammask;
if (VERBOSE) logerror("%s:tms34061 shiftreg read (%04x)\n", cpuexec_describe_context(Machine), offs);
if (VERBOSE) logerror("%s:tms34061 shiftreg read (%04x)\n", cpuexec_describe_context(space->machine), offs);
tms34061.shiftreg = &tms34061.vram[offs];
break;
/* log anything else */
default:
logerror("%s:Unsupported TMS34061 function %d\n", cpuexec_describe_context(Machine), func);
logerror("%s:Unsupported TMS34061 function %d\n", cpuexec_describe_context(space->machine), func);
break;
}
}
UINT8 tms34061_r(int col, int row, int func)
UINT8 tms34061_r(const address_space *space, int col, int row, int func)
{
int result = 0;
offs_t offs;
@ -478,12 +477,12 @@ UINT8 tms34061_r(int col, int row, int func)
/* both 0 and 2 map to register access */
case 0:
case 2:
result = register_r(col);
result = register_r(space, col);
break;
/* function 1 maps to XY access; col is the address adjustment */
case 1:
result = xypixel_r(col);
result = xypixel_r(space, col);
break;
/* funtion 3 maps to direct access */
@ -515,7 +514,7 @@ UINT8 tms34061_r(int col, int row, int func)
/* log anything else */
default:
logerror("%s:Unsupported TMS34061 function %d\n", cpuexec_describe_context(Machine),
logerror("%s:Unsupported TMS34061 function %d\n", cpuexec_describe_context(space->machine),
func);
break;
}

4
src/emu/video/tms34061.h
View File

@ -59,8 +59,8 @@ struct tms34061_display
void tms34061_start(running_machine *machine, const struct tms34061_interface *interface);
/* reads/writes to the 34061 */
UINT8 tms34061_r(int col, int row, int func);
void tms34061_w(int col, int row, int func, UINT8 data);
UINT8 tms34061_r(const address_space *space, int col, int row, int func);
void tms34061_w(const address_space *space, int col, int row, int func, UINT8 data);
/* latch settings */
READ8_HANDLER( tms34061_latch_r );

5
src/mame/drivers/artmagic.c
View File

@ -22,7 +22,6 @@
***************************************************************************/
#include "driver.h"
#include "deprecat.h"
#include "cpu/tms34010/tms34010.h"
#include "video/tlc34076.h"
#include "artmagic.h"
@ -62,10 +61,10 @@ static void update_irq_state(running_machine *machine)
}
static void m68k_gen_int(int state)
static void m68k_gen_int(const device_config *device, int state)
{
tms_irq = state;
update_irq_state(Machine);
update_irq_state(device->machine);
}

4
src/mame/drivers/coolpool.c
View File

@ -125,13 +125,13 @@ static void coolpool_scanline(const device_config *screen, bitmap_t *bitmap, int
*
*************************************/
static void coolpool_to_shiftreg(UINT32 address, UINT16 *shiftreg)
static void coolpool_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(shiftreg, &vram_base[TOWORD(address) & ~TOWORD(0xfff)], TOBYTE(0x1000));
}
static void coolpool_from_shiftreg(UINT32 address, UINT16 *shiftreg)
static void coolpool_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(&vram_base[TOWORD(address) & ~TOWORD(0xfff)], shiftreg, TOBYTE(0x1000));
}

4
src/mame/drivers/firebeat.c
View File

@ -2283,8 +2283,8 @@ static void init_firebeat(running_machine *machine)
rtc65271_init(machine, xram, NULL);
pc16552d_init(0, 19660800, comm_uart_irq_callback, 0); // Network UART
pc16552d_init(1, 24000000, midi_uart_irq_callback, 0); // MIDI UART
pc16552d_init(machine, 0, 19660800, comm_uart_irq_callback, 0); // Network UART
pc16552d_init(machine, 1, 24000000, midi_uart_irq_callback, 0); // MIDI UART
extend_board_irq_enable = 0x3f;
extend_board_irq_active = 0x00;

8
src/mame/drivers/guab.c
View File

@ -103,10 +103,10 @@ static WRITE16_HANDLER( guab_tms34061_w )
col = offset <<= 1;
if (ACCESSING_BITS_8_15)
tms34061_w(col, row, func, data >> 8);
tms34061_w(space, col, row, func, data >> 8);
if (ACCESSING_BITS_0_7)
tms34061_w(col | 1, row, func, data & 0xff);
tms34061_w(space, col | 1, row, func, data & 0xff);
}
@ -123,10 +123,10 @@ static READ16_HANDLER( guab_tms34061_r )
col = offset <<= 1;
if (ACCESSING_BITS_8_15)
data |= tms34061_r(col, row, func) << 8;
data |= tms34061_r(space, col, row, func) << 8;
if (ACCESSING_BITS_0_7)
data |= tms34061_r(col | 1, row, func);
data |= tms34061_r(space, col | 1, row, func);
return data;
}

5
src/mame/drivers/jpmimpct.c
View File

@ -78,7 +78,6 @@
****************************************************************************/
#include "driver.h"
#include "deprecat.h"
#include "cpu/tms34010/tms34010.h"
#include "sound/upd7759.h"
#include "jpmimpct.h"
@ -818,10 +817,10 @@ INPUT_PORTS_END
*
*************************************/
static void jpmimpct_tms_irq(int state)
static void jpmimpct_tms_irq(const device_config *device, int state)
{
tms_irq = state;
update_irqs(Machine);
update_irqs(device->machine);
}
static const tms34010_config tms_config =

2
src/mame/drivers/meritm.c
View File

@ -872,7 +872,7 @@ static MACHINE_START(meritm_crt260)
meritm_psd_a15 = 0;
meritm_switch_banks();
MACHINE_START_CALL(merit_common);
pc16552d_init(0, UART_CLK, NULL, pc16650d_tx_callback);
pc16552d_init(machine, 0, UART_CLK, NULL, pc16650d_tx_callback);
microtouch_init(machine, meritm_microtouch_tx_callback, meritm_touch_coord_transform);
state_save_register_global(machine, meritm_bank);
state_save_register_global(machine, meritm_psd_a15);

4
src/mame/drivers/micro3d.c
View File

@ -396,9 +396,9 @@ static INPUT_PORTS_START( f15se )
INPUT_PORTS_END
static void tms_interrupt(int state)
static void tms_interrupt(const device_config *device, int state)
{
m68901_int_gen(Machine, GPIP4);
m68901_int_gen(device->machine, GPIP4);
}
static INTERRUPT_GEN( micro3d_vblank )

9
src/mame/drivers/xtheball.c
View File

@ -7,7 +7,6 @@
**************************************************************************/
#include "driver.h"
#include "deprecat.h"
#include "cpu/tms34010/tms34010.h"
#include "video/tlc34076.h"
#include "machine/ticket.h"
@ -95,25 +94,25 @@ static void xtheball_scanline_update(const device_config *screen, bitmap_t *bitm
*
*************************************/
static void xtheball_to_shiftreg(UINT32 address, UINT16 *shiftreg)
static void xtheball_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
if (address >= 0x01000000 && address <= 0x010fffff)
memcpy(shiftreg, &vram_bg[TOWORD(address & 0xff000)], TOBYTE(0x1000));
else if (address >= 0x02000000 && address <= 0x020fffff)
memcpy(shiftreg, &vram_fg[TOWORD(address & 0xff000)], TOBYTE(0x1000));
else
logerror("%s:xtheball_to_shiftreg(%08X)\n", cpuexec_describe_context(Machine), address);
logerror("%s:xtheball_to_shiftreg(%08X)\n", cpuexec_describe_context(space->machine), address);
}
static void xtheball_from_shiftreg(UINT32 address, UINT16 *shiftreg)
static void xtheball_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
if (address >= 0x01000000 && address <= 0x010fffff)
memcpy(&vram_bg[TOWORD(address & 0xff000)], shiftreg, TOBYTE(0x1000));
else if (address >= 0x02000000 && address <= 0x020fffff)
memcpy(&vram_fg[TOWORD(address & 0xff000)], shiftreg, TOBYTE(0x1000));
else
logerror("%s:xtheball_from_shiftreg(%08X)\n", cpuexec_describe_context(Machine), address);
logerror("%s:xtheball_from_shiftreg(%08X)\n", cpuexec_describe_context(space->machine), address);
}

4
src/mame/includes/artmagic.h
View File

@ -13,8 +13,8 @@ extern int artmagic_xor[16], artmagic_is_stoneball;
VIDEO_START( artmagic );
void artmagic_to_shiftreg(offs_t address, UINT16 *data);
void artmagic_from_shiftreg(offs_t address, UINT16 *data);
void artmagic_to_shiftreg(const address_space *space, offs_t address, UINT16 *data);
void artmagic_from_shiftreg(const address_space *space, offs_t address, UINT16 *data);
READ16_HANDLER( artmagic_blitter_r );
WRITE16_HANDLER( artmagic_blitter_w );

4
src/mame/includes/btoads.h
View File

@ -34,7 +34,7 @@ WRITE16_HANDLER( btoads_vram_fg_draw_w );
READ16_HANDLER( btoads_vram_fg_display_r );
READ16_HANDLER( btoads_vram_fg_draw_r );
void btoads_to_shiftreg(UINT32 address, UINT16 *shiftreg);
void btoads_from_shiftreg(UINT32 address, UINT16 *shiftreg);
void btoads_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg);
void btoads_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg);
void btoads_scanline_update(const device_config *screen, bitmap_t *bitmap, int scanline, const tms34010_display_params *params);

8
src/mame/includes/exterm.h
View File

@ -12,7 +12,7 @@ extern UINT16 *exterm_slave_videoram;
PALETTE_INIT( exterm );
void exterm_scanline_update(const device_config *screen, bitmap_t *bitmap, int scanline, const tms34010_display_params *params);
void exterm_to_shiftreg_master(UINT32 address, UINT16* shiftreg);
void exterm_from_shiftreg_master(UINT32 address, UINT16* shiftreg);
void exterm_to_shiftreg_slave(UINT32 address, UINT16* shiftreg);
void exterm_from_shiftreg_slave(UINT32 address, UINT16* shiftreg);
void exterm_to_shiftreg_master(const address_space *space, UINT32 address, UINT16* shiftreg);
void exterm_from_shiftreg_master(const address_space *space, UINT32 address, UINT16* shiftreg);
void exterm_to_shiftreg_slave(const address_space *space, UINT32 address, UINT16* shiftreg);
void exterm_from_shiftreg_slave(const address_space *space, UINT32 address, UINT16* shiftreg);

8
src/mame/includes/harddriv.h
View File

@ -55,8 +55,8 @@ MACHINE_RESET( harddriv );
INTERRUPT_GEN( hd68k_irq_gen );
WRITE16_HANDLER( hd68k_irq_ack_w );
void hdgsp_irq_gen(int state);
void hdmsp_irq_gen(int state);
void hdgsp_irq_gen(const device_config *device, int state);
void hdmsp_irq_gen(const device_config *device, int state);
READ16_HANDLER( hd68k_gsp_io_r );
WRITE16_HANDLER( hd68k_gsp_io_w );
@ -224,8 +224,8 @@ extern UINT16 *hdgsp_paletteram_hi;
extern size_t hdgsp_vram_size;
VIDEO_START( harddriv );
void hdgsp_write_to_shiftreg(UINT32 address, UINT16 *shiftreg);
void hdgsp_read_from_shiftreg(UINT32 address, UINT16 *shiftreg);
void hdgsp_write_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg);
void hdgsp_read_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg);
READ16_HANDLER( hdgsp_control_lo_r );
WRITE16_HANDLER( hdgsp_control_lo_w );

4
src/mame/includes/jpmimpct.h
View File

@ -11,8 +11,8 @@ extern UINT16 *tms_vram;
READ16_HANDLER( bt477_r );
WRITE16_HANDLER( bt477_w );
void jpmimpct_to_shiftreg(UINT32 address, UINT16 *shiftreg);
void jpmimpct_from_shiftreg(UINT32 address, UINT16 *shiftreg);
void jpmimpct_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg);
void jpmimpct_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg);
void jpmimpct_scanline_update(const device_config *screen, bitmap_t *bitmap, int scanline, const tms34010_display_params *params);
VIDEO_START( jpmimpct );

4
src/mame/includes/midtunit.h
View File

@ -46,8 +46,8 @@ READ16_HANDLER( midtunit_vram_r );
READ16_HANDLER( midtunit_vram_data_r );
READ16_HANDLER( midtunit_vram_color_r );
void midtunit_to_shiftreg(UINT32 address, UINT16 *shiftreg);
void midtunit_from_shiftreg(UINT32 address, UINT16 *shiftreg);
void midtunit_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg);
void midtunit_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg);
WRITE16_HANDLER( midtunit_control_w );
WRITE16_HANDLER( midwunit_control_w );

4
src/mame/includes/midyunit.h
View File

@ -52,8 +52,8 @@ READ16_HANDLER( midyunit_gfxrom_r );
WRITE16_HANDLER( midyunit_vram_w );
READ16_HANDLER( midyunit_vram_r );
void midyunit_to_shiftreg(UINT32 address, UINT16 *shiftreg);
void midyunit_from_shiftreg(UINT32 address, UINT16 *shiftreg);
void midyunit_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg);
void midyunit_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg);
WRITE16_HANDLER( midyunit_control_w );
WRITE16_HANDLER( midyunit_paletteram_w );

18
src/mame/machine/harddriv.c
View File

@ -232,17 +232,17 @@ WRITE16_HANDLER( hd68k_irq_ack_w )
}
void hdgsp_irq_gen(int state)
void hdgsp_irq_gen(const device_config *device, int state)
{
gsp_irq_state = state;
atarigen_update_interrupts(Machine);
atarigen_update_interrupts(device->machine);
}
void hdmsp_irq_gen(int state)
void hdmsp_irq_gen(const device_config *device, int state)
{
msp_irq_state = state;
atarigen_update_interrupts(Machine);
atarigen_update_interrupts(device->machine);
}
@ -757,14 +757,14 @@ static TIMER_CALLBACK( stmsp_sync_update )
}
INLINE void stmsp_sync_w(int which, offs_t offset, UINT16 data, UINT16 mem_mask)
INLINE void stmsp_sync_w(const address_space *space, offs_t offset, UINT16 data, UINT16 mem_mask, int which)
{
UINT16 newdata = stmsp_sync[which][offset];
COMBINE_DATA(&newdata);
/* if being written from the 68000, synchronize on it */
if (hd34010_host_access)
timer_call_after_resynch(Machine, NULL, newdata | (offset << 16) | (which << 28), stmsp_sync_update);
timer_call_after_resynch(space->machine, NULL, newdata | (offset << 16) | (which << 28), stmsp_sync_update);
/* otherwise, just update */
else
@ -774,19 +774,19 @@ INLINE void stmsp_sync_w(int which, offs_t offset, UINT16 data, UINT16 mem_mask)
WRITE16_HANDLER( stmsp_sync0_w )
{
stmsp_sync_w(0, offset, data, mem_mask);
stmsp_sync_w(space, offset, data, mem_mask, 0);
}
WRITE16_HANDLER( stmsp_sync1_w )
{
stmsp_sync_w(1, offset, data, mem_mask);
stmsp_sync_w(space, offset, data, mem_mask, 1);
}
WRITE16_HANDLER( stmsp_sync2_w )
{
stmsp_sync_w(2, offset, data, mem_mask);
stmsp_sync_w(space, offset, data, mem_mask, 2);
}

4
src/mame/video/artmagic.c
View File

@ -70,7 +70,7 @@ VIDEO_START( artmagic )
*
*************************************/
void artmagic_to_shiftreg(offs_t address, UINT16 *data)
void artmagic_to_shiftreg(const address_space *space, offs_t address, UINT16 *data)
{
UINT16 *vram = address_to_vram(&address);
if (vram)
@ -78,7 +78,7 @@ void artmagic_to_shiftreg(offs_t address, UINT16 *data)
}
void artmagic_from_shiftreg(offs_t address, UINT16 *data)
void artmagic_from_shiftreg(const address_space *space, offs_t address, UINT16 *data)
{
UINT16 *vram = address_to_vram(&address);
if (vram)

9
src/mame/video/btoads.c
View File

@ -7,7 +7,6 @@
**************************************************************************/
#include "driver.h"
#include "deprecat.h"
#include "cpu/tms34010/tms34010.h"
#include "video/tlc34076.h"
#include "btoads.h"
@ -285,7 +284,7 @@ static void render_sprite_row(UINT16 *sprite_source, UINT32 address)
*
*************************************/
void btoads_to_shiftreg(UINT32 address, UINT16 *shiftreg)
void btoads_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
address &= ~0x40000000;
@ -308,11 +307,11 @@ void btoads_to_shiftreg(UINT32 address, UINT16 *shiftreg)
}
else
logerror("%s:btoads_to_shiftreg(%08X)\n", cpuexec_describe_context(Machine), address);
logerror("%s:btoads_to_shiftreg(%08X)\n", cpuexec_describe_context(space->machine), address);
}
void btoads_from_shiftreg(UINT32 address, UINT16 *shiftreg)
void btoads_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
address &= ~0x40000000;
@ -333,7 +332,7 @@ void btoads_from_shiftreg(UINT32 address, UINT16 *shiftreg)
render_sprite_row(shiftreg, address);
else
logerror("%s:btoads_from_shiftreg(%08X)\n", cpuexec_describe_context(Machine), address);
logerror("%s:btoads_from_shiftreg(%08X)\n", cpuexec_describe_context(space->machine), address);
}

4
src/mame/video/capbowl.c
View File

@ -67,7 +67,7 @@ WRITE8_HANDLER( capbowl_tms34061_w )
col ^= 2;
/* Row address (RA0-RA8) is not dependent on the offset */
tms34061_w(col, *capbowl_rowaddress, func, data);
tms34061_w(space, col, *capbowl_rowaddress, func, data);
}
@ -82,7 +82,7 @@ READ8_HANDLER( capbowl_tms34061_r )
col ^= 2;
/* Row address (RA0-RA8) is not dependent on the offset */
return tms34061_r(col, *capbowl_rowaddress, func);
return tms34061_r(space, col, *capbowl_rowaddress, func);
}

8
src/mame/video/exterm.c
View File

@ -36,25 +36,25 @@ PALETTE_INIT( exterm )
*
*************************************/
void exterm_to_shiftreg_master(UINT32 address, UINT16 *shiftreg)
void exterm_to_shiftreg_master(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(shiftreg, &exterm_master_videoram[TOWORD(address)], 256 * sizeof(UINT16));
}
void exterm_from_shiftreg_master(UINT32 address, UINT16 *shiftreg)
void exterm_from_shiftreg_master(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(&exterm_master_videoram[TOWORD(address)], shiftreg, 256 * sizeof(UINT16));
}
void exterm_to_shiftreg_slave(UINT32 address, UINT16 *shiftreg)
void exterm_to_shiftreg_slave(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(shiftreg, &exterm_slave_videoram[TOWORD(address)], 256 * 2 * sizeof(UINT8));
}
void exterm_from_shiftreg_slave(UINT32 address, UINT16 *shiftreg)
void exterm_from_shiftreg_slave(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(&exterm_slave_videoram[TOWORD(address)], shiftreg, 256 * 2 * sizeof(UINT8));
}

4
src/mame/video/harddriv.c
View File

@ -145,7 +145,7 @@ VIDEO_START( harddriv )
*
*************************************/
void hdgsp_write_to_shiftreg(UINT32 address, UINT16 *shiftreg)
void hdgsp_write_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
/* access to the 1bpp/2bpp area */
if (address >= 0x02000000 && address <= 0x020fffff)
@ -171,7 +171,7 @@ void hdgsp_write_to_shiftreg(UINT32 address, UINT16 *shiftreg)
}
void hdgsp_read_from_shiftreg(UINT32 address, UINT16 *shiftreg)
void hdgsp_read_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
if (!shiftreg_enable)
return;

4
src/mame/video/itech8.c
View File

@ -549,7 +549,7 @@ WRITE8_HANDLER( itech8_tms34061_w )
col ^= 2;
/* Row address (RA0-RA8) is not dependent on the offset */
tms34061_w(col, 0xff, func, data);
tms34061_w(space, col, 0xff, func, data);
}
@ -564,7 +564,7 @@ READ8_HANDLER( itech8_tms34061_r )
col ^= 2;
/* Row address (RA0-RA8) is not dependent on the offset */
return tms34061_r(col, 0xff, func);
return tms34061_r(space, col, 0xff, func);
}

4
src/mame/video/jpmimpct.c
View File

@ -98,12 +98,12 @@ READ16_HANDLER( bt477_r )
*
*************************************/
void jpmimpct_to_shiftreg(UINT32 address, UINT16 *shiftreg)
void jpmimpct_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(shiftreg, &tms_vram[TOWORD(address)], 512 * sizeof(UINT16));
}
void jpmimpct_from_shiftreg(UINT32 address, UINT16 *shiftreg)
void jpmimpct_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(&tms_vram[TOWORD(address)], shiftreg, 512 * sizeof(UINT16));
}

4
src/mame/video/midtunit.c
View File

@ -220,13 +220,13 @@ READ16_HANDLER( midtunit_vram_color_r )
*
*************************************/
void midtunit_to_shiftreg(UINT32 address, UINT16 *shiftreg)
void midtunit_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(shiftreg, &local_videoram[address >> 3], 2 * 512 * sizeof(UINT16));
}
void midtunit_from_shiftreg(UINT32 address, UINT16 *shiftreg)
void midtunit_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(&local_videoram[address >> 3], shiftreg, 2 * 512 * sizeof(UINT16));
}

4
src/mame/video/midyunit.c
View File

@ -203,13 +203,13 @@ READ16_HANDLER( midyunit_vram_r )
*
*************************************/
void midyunit_to_shiftreg(UINT32 address, UINT16 *shiftreg)
void midyunit_to_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(shiftreg, &local_videoram[address >> 3], 2 * 512 * sizeof(UINT16));
}
void midyunit_from_shiftreg(UINT32 address, UINT16 *shiftreg)
void midyunit_from_shiftreg(const address_space *space, UINT32 address, UINT16 *shiftreg)
{
memcpy(&local_videoram[address >> 3], shiftreg, 2 * 512 * sizeof(UINT16));
}