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sh4drc: UML implementations of FADD, FSUB, FMUL, and FDIV. [R. Belmont]

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This commit is contained in:
arbee 2018-04-14 22:01:33 -04:00
parent 0c0a05f108
commit afa6aa8b58
5 changed files with 357 additions and 323 deletions
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17
src/devices/cpu/sh/sh.h
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@ -139,6 +139,23 @@ public:
uint32_t vbr;
uint32_t m_delay;
// SH3/4 additional DRC "near" state
uint32_t m_ppc;
uint32_t m_spc;
uint32_t m_ssr;
uint32_t m_rbnk[2][8];
uint32_t m_sgr;
uint32_t m_fr[16];
uint32_t m_xf[16];
uint32_t m_cpu_off;
uint32_t m_pending_irq;
uint32_t m_test_irq;
uint32_t m_fpscr;
uint32_t m_fpul;
uint32_t m_dbr;
int m_frt_input;
};
internal_sh2_state *m_sh2_state;

570
src/devices/cpu/sh/sh4.cpp
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File diff suppressed because it is too large Load Diff

20
src/devices/cpu/sh/sh4.h
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@ -240,6 +240,8 @@ public:
void func_LDCMRBANK();
void func_PREFM();
void func_FADD();
void func_FADD_spre();
void func_FADD_spost();
void func_FSUB();
void func_FMUL();
void func_FDIV();
@ -322,6 +324,9 @@ protected:
address_space_config m_program_config;
address_space_config m_io_config;
uml::parameter m_fs_regmap[16];
uml::parameter m_fd_regmap[16];
int c_md2;
int c_md1;
int c_md0;
@ -336,20 +341,6 @@ protected:
// hack 1 = Naomi hack, hack 2 = Work in Progress implementation
int m_mmuhack;
uint32_t m_ppc;
uint32_t m_spc;
uint32_t m_ssr;
uint32_t m_rbnk[2][8];
uint32_t m_sgr;
uint32_t m_fr[16];
uint32_t m_xf[16];
uint32_t m_cpu_off;
uint32_t m_pending_irq;
uint32_t m_test_irq;
uint32_t m_fpscr;
uint32_t m_fpul;
uint32_t m_dbr;
uint32_t m_exception_priority[128];
int m_exception_requesting[128];
@ -405,7 +396,6 @@ protected:
int8_t m_nmi_line_state;
int m_frt_input;
int m_irln;
int m_internal_irq_level;
int m_internal_irq_vector;

50
src/devices/cpu/sh/sh4comn.cpp
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@ -240,9 +240,9 @@ void sh34_base_device::sh4_swap_fp_registers()
for (s = 0;s <= 15;s++)
{
z = m_fr[s];
m_fr[s] = m_xf[s];
m_xf[s] = z;
z = m_sh2_state->m_fr[s];
m_sh2_state->m_fr[s] = m_sh2_state->m_xf[s];
m_sh2_state->m_xf[s] = z;
}
}
@ -253,12 +253,12 @@ void sh34_base_device::sh4_swap_fp_couples()
for (s = 0;s <= 15;s = s+2)
{
z = m_fr[s];
m_fr[s] = m_fr[s + 1];
m_fr[s + 1] = z;
z = m_xf[s];
m_xf[s] = m_xf[s + 1];
m_xf[s + 1] = z;
z = m_sh2_state->m_fr[s];
m_sh2_state->m_fr[s] = m_sh2_state->m_fr[s + 1];
m_sh2_state->m_fr[s + 1] = z;
z = m_sh2_state->m_xf[s];
m_sh2_state->m_xf[s] = m_sh2_state->m_xf[s + 1];
m_sh2_state->m_xf[s + 1] = z;
}
}
@ -271,16 +271,16 @@ void sh34_base_device::sh4_change_register_bank(int to)
{
for (s = 0;s < 8;s++)
{
m_rbnk[0][s] = m_sh2_state->r[s];
m_sh2_state->r[s] = m_rbnk[1][s];
m_sh2_state->m_rbnk[0][s] = m_sh2_state->r[s];
m_sh2_state->r[s] = m_sh2_state->m_rbnk[1][s];
}
}
else // 1 -> 0
{
for (s = 0;s < 8;s++)
{
m_rbnk[1][s] = m_sh2_state->r[s];
m_sh2_state->r[s] = m_rbnk[0][s];
m_sh2_state->m_rbnk[1][s] = m_sh2_state->r[s];
m_sh2_state->r[s] = m_sh2_state->m_rbnk[0][s];
}
}
}
@ -291,7 +291,7 @@ void sh34_base_device::sh4_syncronize_register_bank(int to)
for (s = 0;s < 8;s++)
{
m_rbnk[to][s] = m_sh2_state->r[s];
m_sh2_state->m_rbnk[to][s] = m_sh2_state->r[s];
}
}
@ -315,8 +315,8 @@ void sh34_base_device::sh4_exception_recompute() // checks if there is any inter
{
int a,z;
m_test_irq = 0;
if ((!m_pending_irq) || ((m_sh2_state->sr & BL) && (m_exception_requesting[SH4_INTC_NMI] == 0)))
m_sh2_state->m_test_irq = 0;
if ((!m_sh2_state->m_pending_irq) || ((m_sh2_state->sr & BL) && (m_exception_requesting[SH4_INTC_NMI] == 0)))
return;
z = (m_sh2_state->sr >> 4) & 15;
for (a=0;a <= SH4_INTC_ROVI;a++)
@ -328,7 +328,7 @@ void sh34_base_device::sh4_exception_recompute() // checks if there is any inter
if (pri > z)
{
//logerror("will test\n");
m_test_irq = 1; // will check for exception at end of instructions
m_sh2_state->m_test_irq = 1; // will check for exception at end of instructions
break;
}
}
@ -342,7 +342,7 @@ void sh34_base_device::sh4_exception_request(int exception) // start requesting
{
//logerror("sh4_exception_request b\n");
m_exception_requesting[exception] = 1;
m_pending_irq++;
m_sh2_state->m_pending_irq++;
sh4_exception_recompute();
}
}
@ -352,7 +352,7 @@ void sh34_base_device::sh4_exception_unrequest(int exception) // stop requesting
if (m_exception_requesting[exception])
{
m_exception_requesting[exception] = 0;
m_pending_irq--;
m_sh2_state->m_pending_irq--;
sh4_exception_recompute();
}
}
@ -371,9 +371,9 @@ void sh34_base_device::sh4_exception_process(int exception, uint32_t vector)
{
sh4_exception_checkunrequest(exception);
m_spc = m_sh2_state->pc;
m_ssr = m_sh2_state->sr;
m_sgr = m_sh2_state->r[15];
m_sh2_state->m_spc = m_sh2_state->pc;
m_sh2_state->m_ssr = m_sh2_state->sr;
m_sh2_state->m_sgr = m_sh2_state->r[15];
//printf("stored m_spc %08x m_ssr %08x m_sgr %08x\n", m_spc, m_ssr, m_sgr);
@ -1078,11 +1078,11 @@ void sh34_base_device::sh4_set_frt_input(int state)
return;
}
if(m_frt_input == state) {
if(m_sh2_state->m_frt_input == state) {
return;
}
m_frt_input = state;
m_sh2_state->m_frt_input = state;
if (m_cpu_type == CPU_TYPE_SH4)
{
@ -1218,7 +1218,7 @@ void sh34_base_device::execute_set_input(int irqline, int state) // set state of
LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", tag(), m_irln));
}
}
if (m_test_irq && (!m_sh2_state->m_delay))
if (m_sh2_state->m_test_irq && (!m_sh2_state->m_delay))
sh4_check_pending_irq("sh4_set_irq_line");
}
}

23
src/devices/cpu/sh/sh4comn.h
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@ -23,19 +23,22 @@
#define NMIPRI() EXPPRI(3,0,16,SH4_INTC_NMI)
#define INTPRI(p,n) EXPPRI(4,2,p,n)
#define FP_RS(r) m_fr[(r)] // binary representation of single precision floating point register r
#define FP_RFS(r) *( (float *)(m_fr+(r)) ) // single precision floating point register r
#define FP_RFD(r) *( (double *)(m_fr+(r)) ) // double precision floating point register r
#define FP_XS(r) m_xf[(r)] // binary representation of extended single precision floating point register r
#define FP_XFS(r) *( (float *)(m_xf+(r)) ) // single precision extended floating point register r
#define FP_XFD(r) *( (double *)(m_xf+(r)) ) // double precision extended floating point register r
#define FP_RS(r) m_sh2_state->m_fr[(r)] // binary representation of single precision floating point register r
#define FP_RFS(r) *( (float *)(m_sh2_state->m_fr+(r)) ) // single precision floating point register r
#define FP_RFD(r) *( (double *)(m_sh2_state->m_fr+(r)) ) // double precision floating point register r
#define FP_XS(r) m_sh2_state->m_xf[(r)] // binary representation of extended single precision floating point register r
#define FP_XFS(r) *( (float *)(m_sh2_state->m_xf+(r)) ) // single precision extended floating point register r
#define FP_XFD(r) *( (double *)(m_sh2_state->m_xf+(r)) ) // double precision extended floating point register r
#ifdef LSB_FIRST
#define FP_RS2(r) m_fr[(r) ^ m_fpu_pr]
#define FP_RFS2(r) *( (float *)(m_fr+((r) ^ m_fpu_pr)) )
#define FP_XS2(r) m_xf[(r) ^ m_fpu_pr]
#define FP_XFS2(r) *( (float *)(m_xf+((r) ^ m_fpu_pr)) )
#define FP_RS2(r) m_sh2_state->m_fr[(r) ^ m_sh2_state->m_fpu_pr]
#define FP_RFS2(r) *( (float *)(m_sh2_state->m_fr+((r) ^ m_sh2_state->m_fpu_pr)) )
#define FP_XS2(r) m_sh2_state->m_xf[(r) ^ m_sh2_state->m_fpu_pr]
#define FP_XFS2(r) *( (float *)(m_sh2_state->m_xf+((r) ^ m_sh2_state->m_fpu_pr)) )
#endif
#define FPSCR mem(&m_sh2_state->m_fpscr)
#define FPS32(reg) m_fs_regmap[reg]
#define FPD32(reg) m_fd_regmap[reg & 14]
enum
{
ICF = 0x00800000,