From b0136c995293a1eafa68f8e0ccdde3a03c67283e Mon Sep 17 00:00:00 2001 From: Aaron Giles Date: Wed, 10 Dec 2008 17:16:04 +0000 Subject: [PATCH] Pointer-ified the MC68HC11 core. --- src/emu/cpu/mc68hc11/hc11ops.c | 1834 +++++++++++++++---------------- src/emu/cpu/mc68hc11/hc11ops.h | 2 +- src/emu/cpu/mc68hc11/mc68hc11.c | 239 ++-- 3 files changed, 1034 insertions(+), 1041 deletions(-) diff --git a/src/emu/cpu/mc68hc11/hc11ops.c b/src/emu/cpu/mc68hc11/hc11ops.c index 50b73726595..7393369a365 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.c +++ b/src/emu/cpu/mc68hc11/hc11ops.c @@ -1,58 +1,58 @@ -#define SET_Z8(r) (hc11.ccr |= ((UINT8)r == 0) ? CC_Z : 0) -#define SET_Z16(r) (hc11.ccr |= ((UINT16)r == 0) ? CC_Z : 0) -#define SET_N8(r) (hc11.ccr |= (r & 0x80) ? CC_N : 0) -#define SET_N16(r) (hc11.ccr |= (r & 0x80) ? CC_N : 0) -#define SET_V_ADD8(r,s,d) (hc11.ccr |= (((r) ^ (s)) & ((r) ^ (d)) & 0x80) ? CC_V : 0) -#define SET_V_SUB8(r,s,d) (hc11.ccr |= (((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? CC_V : 0) -#define SET_V_ADD16(r,s,d) (hc11.ccr |= (((r) ^ (s)) & ((r) ^ (d)) & 0x8000) ? CC_V : 0) -#define SET_V_SUB16(r,s,d) (hc11.ccr |= (((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? CC_V : 0) -#define SET_H(r,s,d) (hc11.ccr |= ((((s) & (d)) | ((d) & (r)) | ((r) & (s))) & 0x10) ? CC_H : 0) -#define SET_C8(x) (hc11.ccr |= ((x) & 0x100) ? CC_C : 0) -#define SET_C16(x) (hc11.ccr |= ((x) & 0x10000) ? CC_C : 0) -#define CLEAR_Z() (hc11.ccr &= ~(CC_Z)) -#define CLEAR_NZV() (hc11.ccr &= ~(CC_N | CC_Z | CC_V)) -#define CLEAR_NZVC() (hc11.ccr &= ~(CC_N | CC_Z | CC_V | CC_C)) -#define CLEAR_HNZVC() (hc11.ccr &= ~(CC_H | CC_N | CC_Z | CC_V | CC_C)) +#define SET_Z8(r) (cpustate->ccr |= ((UINT8)r == 0) ? CC_Z : 0) +#define SET_Z16(r) (cpustate->ccr |= ((UINT16)r == 0) ? CC_Z : 0) +#define SET_N8(r) (cpustate->ccr |= (r & 0x80) ? CC_N : 0) +#define SET_N16(r) (cpustate->ccr |= (r & 0x80) ? CC_N : 0) +#define SET_V_ADD8(r,s,d) (cpustate->ccr |= (((r) ^ (s)) & ((r) ^ (d)) & 0x80) ? CC_V : 0) +#define SET_V_SUB8(r,s,d) (cpustate->ccr |= (((d) ^ (s)) & ((d) ^ (r)) & 0x80) ? CC_V : 0) +#define SET_V_ADD16(r,s,d) (cpustate->ccr |= (((r) ^ (s)) & ((r) ^ (d)) & 0x8000) ? CC_V : 0) +#define SET_V_SUB16(r,s,d) (cpustate->ccr |= (((d) ^ (s)) & ((d) ^ (r)) & 0x8000) ? CC_V : 0) +#define SET_H(r,s,d) (cpustate->ccr |= ((((s) & (d)) | ((d) & (r)) | ((r) & (s))) & 0x10) ? CC_H : 0) +#define SET_C8(x) (cpustate->ccr |= ((x) & 0x100) ? CC_C : 0) +#define SET_C16(x) (cpustate->ccr |= ((x) & 0x10000) ? CC_C : 0) +#define CLEAR_Z(cpustate) (cpustate->ccr &= ~(CC_Z)) +#define CLEAR_NZV(cpustate) (cpustate->ccr &= ~(CC_N | CC_Z | CC_V)) +#define CLEAR_NZVC(cpustate) (cpustate->ccr &= ~(CC_N | CC_Z | CC_V | CC_C)) +#define CLEAR_HNZVC(cpustate) (cpustate->ccr &= ~(CC_H | CC_N | CC_Z | CC_V | CC_C)) -#define SET_ZFLAG() (hc11.ccr |= CC_Z) -#define SET_NFLAG() (hc11.ccr |= CC_N) -#define SET_VFLAG() (hc11.ccr |= CC_V) +#define SET_ZFLAG(cpustate) (cpustate->ccr |= CC_Z) +#define SET_NFLAG(cpustate) (cpustate->ccr |= CC_N) +#define SET_VFLAG(cpustate) (cpustate->ccr |= CC_V) -#define REG_A hc11.d.d8.a -#define REG_B hc11.d.d8.b -#define REG_D hc11.d.d16 +#define REG_A cpustate->d.d8.a +#define REG_B cpustate->d.d8.b +#define REG_D cpustate->d.d16 -INLINE void CYCLES(int cycles) +INLINE void CYCLES(hc11_state *cpustate, int cycles) { - hc11.icount -= cycles; + cpustate->icount -= cycles; } -INLINE void SET_PC(int pc) +INLINE void SET_PC(hc11_state *cpustate, int pc) { - hc11.pc = pc; + cpustate->pc = pc; } -INLINE void PUSH8(UINT8 value) +INLINE void PUSH8(hc11_state *cpustate, UINT8 value) { - WRITE8(hc11.sp--, value); + WRITE8(cpustate, cpustate->sp--, value); } -INLINE void PUSH16(UINT16 value) +INLINE void PUSH16(hc11_state *cpustate, UINT16 value) { - WRITE8(hc11.sp--, (value >> 0) & 0xff); - WRITE8(hc11.sp--, (value >> 8) & 0xff); + WRITE8(cpustate, cpustate->sp--, (value >> 0) & 0xff); + WRITE8(cpustate, cpustate->sp--, (value >> 8) & 0xff); } -INLINE UINT8 POP8(void) +INLINE UINT8 POP8(hc11_state *cpustate) { - return READ8(++hc11.sp); + return READ8(cpustate, ++cpustate->sp); } -INLINE UINT16 POP16(void) +INLINE UINT16 POP16(hc11_state *cpustate) { UINT16 r = 0; - r |= (READ8(++hc11.sp) << 8); - r |= (READ8(++hc11.sp) << 0); + r |= (READ8(cpustate, ++cpustate->sp) << 8); + r |= (READ8(cpustate, ++cpustate->sp) << 0); return r; } @@ -61,2140 +61,2140 @@ INLINE UINT16 POP16(void) /*****************************************************************************/ /* ABA 0x1B */ -static void HC11OP(aba)(void) +static void HC11OP(aba)(hc11_state *cpustate) { UINT16 r = REG_A + REG_B; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, REG_B, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, REG_B, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(2); + CYCLES(cpustate, 2); } /* ABX 0x3A */ -static void HC11OP(abx)(void) +static void HC11OP(abx)(hc11_state *cpustate) { - hc11.ix += REG_B; - CYCLES(3); + cpustate->ix += REG_B; + CYCLES(cpustate, 3); } /* ABY 0x18, 0x3A */ -static void HC11OP(aby)(void) +static void HC11OP(aby)(hc11_state *cpustate) { - hc11.iy += REG_B; - CYCLES(4); + cpustate->iy += REG_B; + CYCLES(cpustate, 4); } /* ADCA IMM 0x89 */ -static void HC11OP(adca_imm)(void) +static void HC11OP(adca_imm)(hc11_state *cpustate) { - int c = (hc11.ccr & CC_C) ? 1 : 0; - UINT8 i = FETCH(); + int c = (cpustate->ccr & CC_C) ? 1 : 0; + UINT8 i = FETCH(cpustate); UINT16 r = REG_A + i + c; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i+c, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i+c, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(2); + CYCLES(cpustate, 2); } /* ADCA DIR 0x99 */ -static void HC11OP(adca_dir)(void) +static void HC11OP(adca_dir)(hc11_state *cpustate) { - int c = (hc11.ccr & CC_C) ? 1 : 0; - UINT8 d = FETCH(); - UINT8 i = READ8(d); + int c = (cpustate->ccr & CC_C) ? 1 : 0; + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); UINT16 r = REG_A + i + c; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i+c, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i+c, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(3); + CYCLES(cpustate, 3); } /* ADCA EXT 0xB9 */ -static void HC11OP(adca_ext)(void) +static void HC11OP(adca_ext)(hc11_state *cpustate) { - int c = (hc11.ccr & CC_C) ? 1 : 0; - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); + int c = (cpustate->ccr & CC_C) ? 1 : 0; + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); UINT16 r = REG_A + i + c; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i+c, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i+c, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(4); + CYCLES(cpustate, 4); } /* ADCA IND, X 0xA9 */ -static void HC11OP(adca_indx)(void) +static void HC11OP(adca_indx)(hc11_state *cpustate) { - int c = (hc11.ccr & CC_C) ? 1 : 0; - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); + int c = (cpustate->ccr & CC_C) ? 1 : 0; + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); UINT16 r = REG_A + i + c; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i+c, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i+c, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(4); + CYCLES(cpustate, 4); } /* ADCA IND, Y 0x18, 0xA9 */ -static void HC11OP(adca_indy)(void) +static void HC11OP(adca_indy)(hc11_state *cpustate) { - int c = (hc11.ccr & CC_C) ? 1 : 0; - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); + int c = (cpustate->ccr & CC_C) ? 1 : 0; + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); UINT16 r = REG_A + i + c; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i+c, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i+c, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(5); + CYCLES(cpustate, 5); } /* ADCB IMM 0xC9 */ -static void HC11OP(adcb_imm)(void) +static void HC11OP(adcb_imm)(hc11_state *cpustate) { - int c = (hc11.ccr & CC_C) ? 1 : 0; - UINT8 i = FETCH(); + int c = (cpustate->ccr & CC_C) ? 1 : 0; + UINT8 i = FETCH(cpustate); UINT16 r = REG_B + i + c; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i+c, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i+c, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(2); + CYCLES(cpustate, 2); } /* ADCB DIR 0xD9 */ -static void HC11OP(adcb_dir)(void) +static void HC11OP(adcb_dir)(hc11_state *cpustate) { - int c = (hc11.ccr & CC_C) ? 1 : 0; - UINT8 d = FETCH(); - UINT8 i = READ8(d); + int c = (cpustate->ccr & CC_C) ? 1 : 0; + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); UINT16 r = REG_B + i + c; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i+c, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i+c, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(3); + CYCLES(cpustate, 3); } /* ADCB EXT 0xF9 */ -static void HC11OP(adcb_ext)(void) +static void HC11OP(adcb_ext)(hc11_state *cpustate) { - int c = (hc11.ccr & CC_C) ? 1 : 0; - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); + int c = (cpustate->ccr & CC_C) ? 1 : 0; + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); UINT16 r = REG_B + i + c; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i+c, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i+c, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(4); + CYCLES(cpustate, 4); } /* ADCB IND, X 0xE9 */ -static void HC11OP(adcb_indx)(void) +static void HC11OP(adcb_indx)(hc11_state *cpustate) { - int c = (hc11.ccr & CC_C) ? 1 : 0; - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); + int c = (cpustate->ccr & CC_C) ? 1 : 0; + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); UINT16 r = REG_B + i + c; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i+c, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i+c, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(4); + CYCLES(cpustate, 4); } /* ADCB IND, Y 0x18, 0xE9 */ -static void HC11OP(adcb_indy)(void) +static void HC11OP(adcb_indy)(hc11_state *cpustate) { - int c = (hc11.ccr & CC_C) ? 1 : 0; - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); + int c = (cpustate->ccr & CC_C) ? 1 : 0; + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); UINT16 r = REG_B + i + c; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i+c, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i+c, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(5); + CYCLES(cpustate, 5); } /* ADDA IMM 0x8B */ -static void HC11OP(adda_imm)(void) +static void HC11OP(adda_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); + UINT8 i = FETCH(cpustate); UINT16 r = REG_A + i; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(2); + CYCLES(cpustate, 2); } /* ADDA DIR 0x9B */ -static void HC11OP(adda_dir)(void) +static void HC11OP(adda_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); UINT16 r = REG_A + i; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(3); + CYCLES(cpustate, 3); } /* ADDA EXT 0xBB */ -static void HC11OP(adda_ext)(void) +static void HC11OP(adda_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); UINT16 r = REG_A + i; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(4); + CYCLES(cpustate, 4); } /* ADDA IND, X 0xAB */ -static void HC11OP(adda_indx)(void) +static void HC11OP(adda_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); UINT16 r = REG_A + i; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(4); + CYCLES(cpustate, 4); } /* ADDA IND, Y 0x18, 0xAB */ -static void HC11OP(adda_indy)(void) +static void HC11OP(adda_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); UINT16 r = REG_A + i; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i, REG_A); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_A); SET_C8(r); REG_A = (UINT8)r; - CYCLES(5); + CYCLES(cpustate, 5); } /* ADDB IMM 0xCB */ -static void HC11OP(addb_imm)(void) +static void HC11OP(addb_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); + UINT8 i = FETCH(cpustate); UINT16 r = REG_B + i; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(2); + CYCLES(cpustate, 2); } /* ADDB DIR 0xDB */ -static void HC11OP(addb_dir)(void) +static void HC11OP(addb_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); UINT16 r = REG_B + i; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(3); + CYCLES(cpustate, 3); } /* ADDB EXT 0xFB */ -static void HC11OP(addb_ext)(void) +static void HC11OP(addb_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); UINT16 r = REG_B + i; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(4); + CYCLES(cpustate, 4); } /* ADDB IND, X 0xEB */ -static void HC11OP(addb_indx)(void) +static void HC11OP(addb_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); UINT16 r = REG_B + i; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(4); + CYCLES(cpustate, 4); } /* ADDB IND, Y 0x18, 0xEB */ -static void HC11OP(addb_indy)(void) +static void HC11OP(addb_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); UINT16 r = REG_B + i; - CLEAR_HNZVC(); + CLEAR_HNZVC(cpustate); SET_H(r, i, REG_B); SET_N8(r); SET_Z8(r); SET_V_ADD8(r, i, REG_B); SET_C8(r); REG_B = (UINT8)r; - CYCLES(5); + CYCLES(cpustate, 5); } /* ADDD IMM 0xC3 */ -static void HC11OP(addd_imm)(void) +static void HC11OP(addd_imm)(hc11_state *cpustate) { - UINT16 i = FETCH16(); + UINT16 i = FETCH16(cpustate); UINT32 r = REG_D + i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); SET_V_ADD16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(4); + CYCLES(cpustate, 4); } /* ADDD DIR 0xD3 */ -static void HC11OP(addd_dir)(void) +static void HC11OP(addd_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT16 i = READ16(d); + UINT8 d = FETCH(cpustate); + UINT16 i = READ16(cpustate, d); UINT32 r = REG_D + i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); SET_V_ADD16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(5); + CYCLES(cpustate, 5); } /* ADDD EXT 0xF3 */ -static void HC11OP(addd_ext)(void) +static void HC11OP(addd_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT16 i = READ16(adr); + UINT16 adr = FETCH16(cpustate); + UINT16 i = READ16(cpustate, adr); UINT32 r = REG_D + i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); SET_V_ADD16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(6); + CYCLES(cpustate, 6); } /* ADDD IND, X 0xE3 */ -static void HC11OP(addd_indx)(void) +static void HC11OP(addd_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT16 i = READ16(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + UINT16 i = READ16(cpustate, cpustate->ix + offset); UINT32 r = REG_D + i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); SET_V_ADD16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(6); + CYCLES(cpustate, 6); } /* ADDD IND, Y 0x18, 0xE3 */ -static void HC11OP(addd_indy)(void) +static void HC11OP(addd_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT16 i = READ16(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + UINT16 i = READ16(cpustate, cpustate->iy + offset); UINT32 r = REG_D + i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); SET_V_ADD16(r, i, REG_D); SET_C16(r); REG_D = (UINT16)r; - CYCLES(7); + CYCLES(cpustate, 7); } /* ANDA IMM 0x84 */ -static void HC11OP(anda_imm)(void) +static void HC11OP(anda_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); - CLEAR_NZV(); + UINT8 i = FETCH(cpustate); + CLEAR_NZV(cpustate); REG_A &= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(2); + CYCLES(cpustate, 2); } /* ANDA DIR 0x94 */ -static void HC11OP(anda_dir)(void) +static void HC11OP(anda_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); - CLEAR_NZV(); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); + CLEAR_NZV(cpustate); REG_A &= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(3); + CYCLES(cpustate, 3); } /* ANDA EXT 0xB4 */ -static void HC11OP(anda_ext)(void) +static void HC11OP(anda_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); - CLEAR_NZV(); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); + CLEAR_NZV(cpustate); REG_A &= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(4); + CYCLES(cpustate, 4); } /* ANDA IND, X 0xA4 */ -static void HC11OP(anda_indx)(void) +static void HC11OP(anda_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); + CLEAR_NZV(cpustate); REG_A &= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(4); + CYCLES(cpustate, 4); } /* ANDA IND, Y 0x18, 0xA4 */ -static void HC11OP(anda_indy)(void) +static void HC11OP(anda_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); + CLEAR_NZV(cpustate); REG_A &= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(5); + CYCLES(cpustate, 5); } /* ANDB IMM 0xC4 */ -static void HC11OP(andb_imm)(void) +static void HC11OP(andb_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); - CLEAR_NZV(); + UINT8 i = FETCH(cpustate); + CLEAR_NZV(cpustate); REG_B &= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(2); + CYCLES(cpustate, 2); } /* ANDB DIR 0xD4 */ -static void HC11OP(andb_dir)(void) +static void HC11OP(andb_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); - CLEAR_NZV(); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); + CLEAR_NZV(cpustate); REG_B &= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(3); + CYCLES(cpustate, 3); } /* ANDB EXT 0xF4 */ -static void HC11OP(andb_ext)(void) +static void HC11OP(andb_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); - CLEAR_NZV(); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); + CLEAR_NZV(cpustate); REG_B &= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(4); + CYCLES(cpustate, 4); } /* ANDB IND, X 0xE4 */ -static void HC11OP(andb_indx)(void) +static void HC11OP(andb_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); + CLEAR_NZV(cpustate); REG_B &= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(4); + CYCLES(cpustate, 4); } /* ANDB IND, Y 0x18, 0xE4 */ -static void HC11OP(andb_indy)(void) +static void HC11OP(andb_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); + CLEAR_NZV(cpustate); REG_B &= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(5); + CYCLES(cpustate, 5); } /* BITA IMM 0x85 */ -static void HC11OP(bita_imm)(void) +static void HC11OP(bita_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); + UINT8 i = FETCH(cpustate); UINT8 r = REG_A & i; - CLEAR_NZV(); + CLEAR_NZV(cpustate); SET_N8(r); SET_Z8(r); - CYCLES(2); + CYCLES(cpustate, 2); } /* BITA DIR 0x95 */ -static void HC11OP(bita_dir)(void) +static void HC11OP(bita_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); UINT8 r = REG_A & i; - CLEAR_NZV(); + CLEAR_NZV(cpustate); SET_N8(r); SET_Z8(r); - CYCLES(3); + CYCLES(cpustate, 3); } /* BITA EXT 0xB5 */ -static void HC11OP(bita_ext)(void) +static void HC11OP(bita_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); UINT8 r = REG_A & i; - CLEAR_NZV(); + CLEAR_NZV(cpustate); SET_N8(r); SET_Z8(r); - CYCLES(4); + CYCLES(cpustate, 4); } /* BITA IND, X 0xA5 */ -static void HC11OP(bita_indx)(void) +static void HC11OP(bita_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); UINT8 r = REG_A & i; - CLEAR_NZV(); + CLEAR_NZV(cpustate); SET_N8(r); SET_Z8(r); - CYCLES(4); + CYCLES(cpustate, 4); } /* BITA IND, Y 0x18, 0xA5 */ -static void HC11OP(bita_indy)(void) +static void HC11OP(bita_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); UINT8 r = REG_A & i; - CLEAR_NZV(); + CLEAR_NZV(cpustate); SET_N8(r); SET_Z8(r); - CYCLES(5); + CYCLES(cpustate, 5); } /* BITB IMM 0xC5 */ -static void HC11OP(bitb_imm)(void) +static void HC11OP(bitb_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); + UINT8 i = FETCH(cpustate); UINT8 r = REG_B & i; - CLEAR_NZV(); + CLEAR_NZV(cpustate); SET_N8(r); SET_Z8(r); - CYCLES(2); + CYCLES(cpustate, 2); } /* BITB DIR 0xD5 */ -static void HC11OP(bitb_dir)(void) +static void HC11OP(bitb_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); UINT8 r = REG_B & i; - CLEAR_NZV(); + CLEAR_NZV(cpustate); SET_N8(r); SET_Z8(r); - CYCLES(3); + CYCLES(cpustate, 3); } /* BITB EXT 0xF5 */ -static void HC11OP(bitb_ext)(void) +static void HC11OP(bitb_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); UINT8 r = REG_B & i; - CLEAR_NZV(); + CLEAR_NZV(cpustate); SET_N8(r); SET_Z8(r); - CYCLES(4); + CYCLES(cpustate, 4); } /* BITB IND, X 0xE5 */ -static void HC11OP(bitb_indx)(void) +static void HC11OP(bitb_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); UINT8 r = REG_B & i; - CLEAR_NZV(); + CLEAR_NZV(cpustate); SET_N8(r); SET_Z8(r); - CYCLES(4); + CYCLES(cpustate, 4); } /* BITB IND, Y 0x18, 0xE5 */ -static void HC11OP(bitb_indy)(void) +static void HC11OP(bitb_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); UINT8 r = REG_B & i; - CLEAR_NZV(); + CLEAR_NZV(cpustate); SET_N8(r); SET_Z8(r); - CYCLES(5); + CYCLES(cpustate, 5); } /* BCS 0x25 */ -static void HC11OP(bcs)(void) +static void HC11OP(bcs)(hc11_state *cpustate) { - INT8 rel = FETCH(); - if (hc11.ccr & CC_C) /* Branch if C flag set */ + INT8 rel = FETCH(cpustate); + if (cpustate->ccr & CC_C) /* Branch if C flag set */ { - SET_PC(hc11.ppc + rel + 2); + SET_PC(cpustate, cpustate->ppc + rel + 2); } - CYCLES(3); + CYCLES(cpustate, 3); } /* BEQ 0x27 */ -static void HC11OP(beq)(void) +static void HC11OP(beq)(hc11_state *cpustate) { - INT8 rel = FETCH(); - if (hc11.ccr & CC_Z) /* Branch if Z flag set */ + INT8 rel = FETCH(cpustate); + if (cpustate->ccr & CC_Z) /* Branch if Z flag set */ { - SET_PC(hc11.ppc + rel + 2); + SET_PC(cpustate, cpustate->ppc + rel + 2); } - CYCLES(3); + CYCLES(cpustate, 3); } /* BNE 0x26 */ -static void HC11OP(bne)(void) +static void HC11OP(bne)(hc11_state *cpustate) { - INT8 rel = FETCH(); - if ((hc11.ccr & CC_Z) == 0) /* Branch if Z flag clear */ + INT8 rel = FETCH(cpustate); + if ((cpustate->ccr & CC_Z) == 0) /* Branch if Z flag clear */ { - SET_PC(hc11.ppc + rel + 2); + SET_PC(cpustate, cpustate->ppc + rel + 2); } - CYCLES(3); + CYCLES(cpustate, 3); } /* BLE 0x2F */ -static void HC11OP(ble)(void) +static void HC11OP(ble)(hc11_state *cpustate) { - UINT8 n = (hc11.ccr & CC_N) ? 1 : 0; - UINT8 v = (hc11.ccr & CC_V) ? 1 : 0; - INT8 rel = FETCH(); - if ((hc11.ccr & CC_Z) || (n ^ v)) /* Branch if Z flag set or (N ^ V) */ + UINT8 n = (cpustate->ccr & CC_N) ? 1 : 0; + UINT8 v = (cpustate->ccr & CC_V) ? 1 : 0; + INT8 rel = FETCH(cpustate); + if ((cpustate->ccr & CC_Z) || (n ^ v)) /* Branch if Z flag set or (N ^ V) */ { - SET_PC(hc11.ppc + rel + 2); + SET_PC(cpustate, cpustate->ppc + rel + 2); } - CYCLES(3); + CYCLES(cpustate, 3); } /* BPL 0x2A */ -static void HC11OP(bpl)(void) +static void HC11OP(bpl)(hc11_state *cpustate) { - INT8 rel = FETCH(); - if ((hc11.ccr & CC_N) == 0) /* Branch if N flag clear */ + INT8 rel = FETCH(cpustate); + if ((cpustate->ccr & CC_N) == 0) /* Branch if N flag clear */ { - SET_PC(hc11.ppc + rel + 2); + SET_PC(cpustate, cpustate->ppc + rel + 2); } - CYCLES(3); + CYCLES(cpustate, 3); } /* BRA 0x20 */ -static void HC11OP(bra)(void) +static void HC11OP(bra)(hc11_state *cpustate) { - INT8 rel = FETCH(); - SET_PC(hc11.ppc + rel + 2); - CYCLES(3); + INT8 rel = FETCH(cpustate); + SET_PC(cpustate, cpustate->ppc + rel + 2); + CYCLES(cpustate, 3); } /* BSR 0x8D */ -static void HC11OP(bsr)(void) +static void HC11OP(bsr)(hc11_state *cpustate) { - INT8 rel = FETCH(); - UINT16 rt_adr = hc11.pc; - PUSH16(rt_adr); - SET_PC(hc11.ppc + rel + 2); - CYCLES(6); + INT8 rel = FETCH(cpustate); + UINT16 rt_adr = cpustate->pc; + PUSH16(cpustate, rt_adr); + SET_PC(cpustate, cpustate->ppc + rel + 2); + CYCLES(cpustate, 6); } /* CLI 0x0E */ -static void HC11OP(cli)(void) +static void HC11OP(cli)(hc11_state *cpustate) { - hc11.ccr &= ~CC_I; - CYCLES(2); + cpustate->ccr &= ~CC_I; + CYCLES(cpustate, 2); } /* CLRA 0x4F */ -static void HC11OP(clra)(void) +static void HC11OP(clra)(hc11_state *cpustate) { REG_A = 0; - CLEAR_NZVC(); - SET_ZFLAG(); - CYCLES(2); + CLEAR_NZVC(cpustate); + SET_ZFLAG(cpustate); + CYCLES(cpustate, 2); } /* CLRB 0x5F */ -static void HC11OP(clrb)(void) +static void HC11OP(clrb)(hc11_state *cpustate) { REG_B = 0; - CLEAR_NZVC(); - SET_ZFLAG(); - CYCLES(2); + CLEAR_NZVC(cpustate); + SET_ZFLAG(cpustate); + CYCLES(cpustate, 2); } /* CLR EXT 0x7F */ -static void HC11OP(clr_ext)(void) +static void HC11OP(clr_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - WRITE8(adr, 0); - CLEAR_NZVC(); - SET_ZFLAG(); - CYCLES(6); + UINT16 adr = FETCH16(cpustate); + WRITE8(cpustate, adr, 0); + CLEAR_NZVC(cpustate); + SET_ZFLAG(cpustate); + CYCLES(cpustate, 6); } /* CLR IND, X 0x6F */ -static void HC11OP(clr_indx)(void) +static void HC11OP(clr_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - WRITE8(hc11.ix + offset, 0); - CLEAR_NZVC(); - SET_ZFLAG(); - CYCLES(6); + UINT8 offset = FETCH(cpustate); + WRITE8(cpustate, cpustate->ix + offset, 0); + CLEAR_NZVC(cpustate); + SET_ZFLAG(cpustate); + CYCLES(cpustate, 6); } /* CLR IND, Y 0x18, 0x6F */ -static void HC11OP(clr_indy)(void) +static void HC11OP(clr_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - WRITE8(hc11.iy + offset, 0); - CLEAR_NZVC(); - SET_ZFLAG(); - CYCLES(7); + UINT8 offset = FETCH(cpustate); + WRITE8(cpustate, cpustate->iy + offset, 0); + CLEAR_NZVC(cpustate); + SET_ZFLAG(cpustate); + CYCLES(cpustate, 7); } /* CMPA IMM 0x81 */ -static void HC11OP(cmpa_imm)(void) +static void HC11OP(cmpa_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); + UINT8 i = FETCH(cpustate); UINT16 r = REG_A - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); - CYCLES(2); + CYCLES(cpustate, 2); } /* CMPA DIR 0x91 */ -static void HC11OP(cmpa_dir)(void) +static void HC11OP(cmpa_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); UINT16 r = REG_A - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); - CYCLES(3); + CYCLES(cpustate, 3); } /* CMPA EXT 0xB1 */ -static void HC11OP(cmpa_ext)(void) +static void HC11OP(cmpa_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); UINT16 r = REG_A - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); - CYCLES(4); + CYCLES(cpustate, 4); } /* CMPA IND, X 0xA1 */ -static void HC11OP(cmpa_indx)(void) +static void HC11OP(cmpa_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); UINT16 r = REG_A - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); - CYCLES(4); + CYCLES(cpustate, 4); } /* CMPA IND, Y 0x18, 0xA1 */ -static void HC11OP(cmpa_indy)(void) +static void HC11OP(cmpa_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); UINT16 r = REG_A - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_A); SET_C8(r); - CYCLES(5); + CYCLES(cpustate, 5); } /* CMPB IMM 0xC1 */ -static void HC11OP(cmpb_imm)(void) +static void HC11OP(cmpb_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); + UINT8 i = FETCH(cpustate); UINT16 r = REG_B - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); - CYCLES(2); + CYCLES(cpustate, 2); } /* CMPB DIR 0xD1 */ -static void HC11OP(cmpb_dir)(void) +static void HC11OP(cmpb_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); UINT16 r = REG_B - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); - CYCLES(3); + CYCLES(cpustate, 3); } /* CMPB EXT 0xF1 */ -static void HC11OP(cmpb_ext)(void) +static void HC11OP(cmpb_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); UINT16 r = REG_B - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); - CYCLES(4); + CYCLES(cpustate, 4); } /* CMPB IND, X 0xE1 */ -static void HC11OP(cmpb_indx)(void) +static void HC11OP(cmpb_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); UINT16 r = REG_B - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); - CYCLES(4); + CYCLES(cpustate, 4); } /* CMPB IND, Y 0x18, 0xE1 */ -static void HC11OP(cmpb_indy)(void) +static void HC11OP(cmpb_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); UINT16 r = REG_B - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(r); SET_Z8(r); SET_V_SUB8(r, i, REG_B); SET_C8(r); - CYCLES(5); + CYCLES(cpustate, 5); } /* CPD IMM 0x1A, 0x83 */ -static void HC11OP(cpd_imm)(void) +static void HC11OP(cpd_imm)(hc11_state *cpustate) { - UINT16 i = FETCH16(); + UINT16 i = FETCH16(cpustate); UINT32 r = REG_D - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); - CYCLES(5); + CYCLES(cpustate, 5); } /* CPD DIR 0x1A, 0x93 */ -static void HC11OP(cpd_dir)(void) +static void HC11OP(cpd_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT16 i = READ16(d); + UINT8 d = FETCH(cpustate); + UINT16 i = READ16(cpustate, d); UINT32 r = REG_D - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); - CYCLES(6); + CYCLES(cpustate, 6); } /* CPD EXT 0x1A, 0xB3 */ -static void HC11OP(cpd_ext)(void) +static void HC11OP(cpd_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT16 i = READ16(adr); + UINT16 adr = FETCH16(cpustate); + UINT16 i = READ16(cpustate, adr); UINT32 r = REG_D - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); - CYCLES(7); + CYCLES(cpustate, 7); } /* CPD IND, X 0x1A, 0xA3 */ -static void HC11OP(cpd_indx)(void) +static void HC11OP(cpd_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT16 i = READ16(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + UINT16 i = READ16(cpustate, cpustate->ix + offset); UINT32 r = REG_D - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); - CYCLES(7); + CYCLES(cpustate, 7); } /* CPD IND, Y 0xCD, 0xA3 */ -static void HC11OP(cpd_indy)(void) +static void HC11OP(cpd_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT16 i = READ16(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + UINT16 i = READ16(cpustate, cpustate->iy + offset); UINT32 r = REG_D - i; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); SET_V_SUB16(r, i, REG_D); SET_C16(r); - CYCLES(7); + CYCLES(cpustate, 7); } /* CPX IMM 0x8C */ -static void HC11OP(cpx_imm)(void) +static void HC11OP(cpx_imm)(hc11_state *cpustate) { - UINT16 i = FETCH16(); - UINT32 r = hc11.ix - i; - CLEAR_NZVC(); + UINT16 i = FETCH16(cpustate); + UINT32 r = cpustate->ix - i; + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, hc11.ix); + SET_V_SUB16(r, i, cpustate->ix); SET_C16(r); - CYCLES(4); + CYCLES(cpustate, 4); } /* CPX DIR 0x9C */ -static void HC11OP(cpx_dir)(void) +static void HC11OP(cpx_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT16 i = READ16(d); - UINT32 r = hc11.ix - i; - CLEAR_NZVC(); + UINT8 d = FETCH(cpustate); + UINT16 i = READ16(cpustate, d); + UINT32 r = cpustate->ix - i; + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, hc11.ix); + SET_V_SUB16(r, i, cpustate->ix); SET_C16(r); - CYCLES(5); + CYCLES(cpustate, 5); } /* CPX EXT 0xBC */ -static void HC11OP(cpx_ext)(void) +static void HC11OP(cpx_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT16 i = READ16(adr); - UINT32 r = hc11.ix - i; - CLEAR_NZVC(); + UINT16 adr = FETCH16(cpustate); + UINT16 i = READ16(cpustate, adr); + UINT32 r = cpustate->ix - i; + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, hc11.ix); + SET_V_SUB16(r, i, cpustate->ix); SET_C16(r); - CYCLES(6); + CYCLES(cpustate, 6); } /* CPX IND, X 0xAC */ -static void HC11OP(cpx_indx)(void) +static void HC11OP(cpx_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT16 i = READ16(hc11.ix + offset); - UINT32 r = hc11.ix - i; - CLEAR_NZVC(); + UINT8 offset = FETCH(cpustate); + UINT16 i = READ16(cpustate, cpustate->ix + offset); + UINT32 r = cpustate->ix - i; + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, hc11.ix); + SET_V_SUB16(r, i, cpustate->ix); SET_C16(r); - CYCLES(6); + CYCLES(cpustate, 6); } /* CPX IND, Y 0xCD, 0xAC */ -static void HC11OP(cpx_indy)(void) +static void HC11OP(cpx_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT16 i = READ16(hc11.iy + offset); - UINT32 r = hc11.ix - i; - CLEAR_NZVC(); + UINT8 offset = FETCH(cpustate); + UINT16 i = READ16(cpustate, cpustate->iy + offset); + UINT32 r = cpustate->ix - i; + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, hc11.ix); + SET_V_SUB16(r, i, cpustate->ix); SET_C16(r); - CYCLES(7); + CYCLES(cpustate, 7); } /* CPY IMM 0x18, 0x8C */ -static void HC11OP(cpy_imm)(void) +static void HC11OP(cpy_imm)(hc11_state *cpustate) { - UINT16 i = FETCH16(); - UINT32 r = hc11.iy - i; - CLEAR_NZVC(); + UINT16 i = FETCH16(cpustate); + UINT32 r = cpustate->iy - i; + CLEAR_NZVC(cpustate); SET_N16(r); SET_Z16(r); - SET_V_SUB16(r, i, hc11.iy); + SET_V_SUB16(r, i, cpustate->iy); SET_C16(r); - CYCLES(5); + CYCLES(cpustate, 5); } /* DEX 0x09 */ -static void HC11OP(dex)(void) +static void HC11OP(dex)(hc11_state *cpustate) { - CLEAR_Z(); - hc11.ix--; - SET_Z16(hc11.ix); - CYCLES(3); + CLEAR_Z(cpustate); + cpustate->ix--; + SET_Z16(cpustate->ix); + CYCLES(cpustate, 3); } /* DEY 0x18, 0x09 */ -static void HC11OP(dey)(void) +static void HC11OP(dey)(hc11_state *cpustate) { - CLEAR_Z(); - hc11.iy--; - SET_Z16(hc11.iy); - CYCLES(4); + CLEAR_Z(cpustate); + cpustate->iy--; + SET_Z16(cpustate->iy); + CYCLES(cpustate, 4); } /* EORA IMM 0x88 */ -static void HC11OP(eora_imm)(void) +static void HC11OP(eora_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); - CLEAR_NZV(); + UINT8 i = FETCH(cpustate); + CLEAR_NZV(cpustate); REG_A ^= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(2); + CYCLES(cpustate, 2); } /* EORA DIR 0x98 */ -static void HC11OP(eora_dir)(void) +static void HC11OP(eora_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); - CLEAR_NZV(); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); + CLEAR_NZV(cpustate); REG_A ^= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(3); + CYCLES(cpustate, 3); } /* EORA EXT 0xB8 */ -static void HC11OP(eora_ext)(void) +static void HC11OP(eora_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); - CLEAR_NZV(); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); + CLEAR_NZV(cpustate); REG_A ^= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(4); + CYCLES(cpustate, 4); } /* EORA IND, X 0xA8 */ -static void HC11OP(eora_indx)(void) +static void HC11OP(eora_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); + CLEAR_NZV(cpustate); REG_A ^= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(4); + CYCLES(cpustate, 4); } /* EORA IND, Y 0x18, 0xA8 */ -static void HC11OP(eora_indy)(void) +static void HC11OP(eora_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); + CLEAR_NZV(cpustate); REG_A ^= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(5); + CYCLES(cpustate, 5); } /* EORB IMM 0xC8 */ -static void HC11OP(eorb_imm)(void) +static void HC11OP(eorb_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); - CLEAR_NZV(); + UINT8 i = FETCH(cpustate); + CLEAR_NZV(cpustate); REG_B ^= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(2); + CYCLES(cpustate, 2); } /* EORB DIR 0xD8 */ -static void HC11OP(eorb_dir)(void) +static void HC11OP(eorb_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); - CLEAR_NZV(); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); + CLEAR_NZV(cpustate); REG_B ^= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(3); + CYCLES(cpustate, 3); } /* EORB EXT 0xF8 */ -static void HC11OP(eorb_ext)(void) +static void HC11OP(eorb_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); - CLEAR_NZV(); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); + CLEAR_NZV(cpustate); REG_B ^= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(4); + CYCLES(cpustate, 4); } /* EORB IND, X 0xE8 */ -static void HC11OP(eorb_indx)(void) +static void HC11OP(eorb_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); + CLEAR_NZV(cpustate); REG_B ^= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(4); + CYCLES(cpustate, 4); } /* EORB IND, Y 0x18, 0xE8 */ -static void HC11OP(eorb_indy)(void) +static void HC11OP(eorb_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); + CLEAR_NZV(cpustate); REG_B ^= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(5); + CYCLES(cpustate, 5); } /* INCA 0x4C */ -static void HC11OP(inca)(void) +static void HC11OP(inca)(hc11_state *cpustate) { - CLEAR_NZV(); + CLEAR_NZV(cpustate); if (REG_A == 0x7f) - SET_VFLAG(); + SET_VFLAG(cpustate); REG_A++; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(2); + CYCLES(cpustate, 2); } /* INX 0x08 */ -static void HC11OP(inx)(void) +static void HC11OP(inx)(hc11_state *cpustate) { - CLEAR_Z(); - hc11.ix++; - SET_Z16(hc11.ix); - CYCLES(3); + CLEAR_Z(cpustate); + cpustate->ix++; + SET_Z16(cpustate->ix); + CYCLES(cpustate, 3); } /* INY 0x18, 0x08 */ -static void HC11OP(iny)(void) +static void HC11OP(iny)(hc11_state *cpustate) { - CLEAR_Z(); - hc11.iy++; - SET_Z16(hc11.iy); - CYCLES(4); + CLEAR_Z(cpustate); + cpustate->iy++; + SET_Z16(cpustate->iy); + CYCLES(cpustate, 4); } /* JMP EXT 0x7E */ -static void HC11OP(jmp_ext)(void) +static void HC11OP(jmp_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - SET_PC(adr); - CYCLES(3); + UINT16 adr = FETCH16(cpustate); + SET_PC(cpustate, adr); + CYCLES(cpustate, 3); } /* JSR DIR 0x9D */ -static void HC11OP(jsr_dir)(void) +static void HC11OP(jsr_dir)(hc11_state *cpustate) { - UINT8 i = FETCH(); - UINT16 rt_adr = hc11.pc; - PUSH16(rt_adr); - SET_PC(i); - CYCLES(5); + UINT8 i = FETCH(cpustate); + UINT16 rt_adr = cpustate->pc; + PUSH16(cpustate, rt_adr); + SET_PC(cpustate, i); + CYCLES(cpustate, 5); } /* JSR EXT 0xBD */ -static void HC11OP(jsr_ext)(void) +static void HC11OP(jsr_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT16 rt_adr = hc11.pc; - PUSH16(rt_adr); - SET_PC(adr); - CYCLES(6); + UINT16 adr = FETCH16(cpustate); + UINT16 rt_adr = cpustate->pc; + PUSH16(cpustate, rt_adr); + SET_PC(cpustate, adr); + CYCLES(cpustate, 6); } /* JSR IND, X 0xAD */ -static void HC11OP(jsr_indx)(void) +static void HC11OP(jsr_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT16 rt_adr = hc11.pc; - PUSH16(rt_adr); - SET_PC(hc11.ix + offset); - CYCLES(6); + UINT8 offset = FETCH(cpustate); + UINT16 rt_adr = cpustate->pc; + PUSH16(cpustate, rt_adr); + SET_PC(cpustate, cpustate->ix + offset); + CYCLES(cpustate, 6); } /* JSR IND, Y 0x18, 0xAD */ -static void HC11OP(jsr_indy)(void) +static void HC11OP(jsr_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT16 rt_adr = hc11.pc; - PUSH16(rt_adr); - SET_PC(hc11.iy + offset); - CYCLES(6); + UINT8 offset = FETCH(cpustate); + UINT16 rt_adr = cpustate->pc; + PUSH16(cpustate, rt_adr); + SET_PC(cpustate, cpustate->iy + offset); + CYCLES(cpustate, 6); } /* LDAA IMM 0x86 */ -static void HC11OP(ldaa_imm)(void) +static void HC11OP(ldaa_imm)(hc11_state *cpustate) { - CLEAR_NZV(); - REG_A = FETCH(); + CLEAR_NZV(cpustate); + REG_A = FETCH(cpustate); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(2); + CYCLES(cpustate, 2); } /* LDAA DIR 0x96 */ -static void HC11OP(ldaa_dir)(void) +static void HC11OP(ldaa_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - CLEAR_NZV(); - REG_A = READ8(d); + UINT8 d = FETCH(cpustate); + CLEAR_NZV(cpustate); + REG_A = READ8(cpustate, d); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(3); + CYCLES(cpustate, 3); } /* LDAA EXT 0xB6 */ -static void HC11OP(ldaa_ext)(void) +static void HC11OP(ldaa_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - CLEAR_NZV(); - REG_A = READ8(adr); + UINT16 adr = FETCH16(cpustate); + CLEAR_NZV(cpustate); + REG_A = READ8(cpustate, adr); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(4); + CYCLES(cpustate, 4); } /* LDAA IND, X 0xA6 */ -static void HC11OP(ldaa_indx)(void) +static void HC11OP(ldaa_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - REG_A = READ8(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + REG_A = READ8(cpustate, cpustate->ix + offset); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(4); + CYCLES(cpustate, 4); } /* LDAA IND, Y 0x18, 0xA6 */ -static void HC11OP(ldaa_indy)(void) +static void HC11OP(ldaa_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - REG_A = READ8(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + REG_A = READ8(cpustate, cpustate->iy + offset); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(5); + CYCLES(cpustate, 5); } /* LDAB IMM 0xC6 */ -static void HC11OP(ldab_imm)(void) +static void HC11OP(ldab_imm)(hc11_state *cpustate) { - CLEAR_NZV(); - REG_B = FETCH(); + CLEAR_NZV(cpustate); + REG_B = FETCH(cpustate); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(2); + CYCLES(cpustate, 2); } /* LDAB DIR 0xD6 */ -static void HC11OP(ldab_dir)(void) +static void HC11OP(ldab_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - CLEAR_NZV(); - REG_B = READ8(d); + UINT8 d = FETCH(cpustate); + CLEAR_NZV(cpustate); + REG_B = READ8(cpustate, d); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(3); + CYCLES(cpustate, 3); } /* LDAB EXT 0xF6 */ -static void HC11OP(ldab_ext)(void) +static void HC11OP(ldab_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - CLEAR_NZV(); - REG_B = READ8(adr); + UINT16 adr = FETCH16(cpustate); + CLEAR_NZV(cpustate); + REG_B = READ8(cpustate, adr); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(4); + CYCLES(cpustate, 4); } /* LDAB IND, X 0xE6 */ -static void HC11OP(ldab_indx)(void) +static void HC11OP(ldab_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - REG_B = READ8(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + REG_B = READ8(cpustate, cpustate->ix + offset); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(4); + CYCLES(cpustate, 4); } /* LDAB IND, Y 0x18, 0xE6 */ -static void HC11OP(ldab_indy)(void) +static void HC11OP(ldab_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - REG_B = READ8(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + REG_B = READ8(cpustate, cpustate->iy + offset); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(5); + CYCLES(cpustate, 5); } /* LDD IMM 0xCC */ -static void HC11OP(ldd_imm)(void) +static void HC11OP(ldd_imm)(hc11_state *cpustate) { - CLEAR_NZV(); - REG_D = FETCH16(); + CLEAR_NZV(cpustate); + REG_D = FETCH16(cpustate); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(3); + CYCLES(cpustate, 3); } /* LDD DIR 0xDC */ -static void HC11OP(ldd_dir)(void) +static void HC11OP(ldd_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - CLEAR_NZV(); - REG_D = READ16(d); + UINT8 d = FETCH(cpustate); + CLEAR_NZV(cpustate); + REG_D = READ16(cpustate, d); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(4); + CYCLES(cpustate, 4); } /* LDD EXT 0xFC */ -static void HC11OP(ldd_ext)(void) +static void HC11OP(ldd_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - CLEAR_NZV(); - REG_D = READ16(adr); + UINT16 adr = FETCH16(cpustate); + CLEAR_NZV(cpustate); + REG_D = READ16(cpustate, adr); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(5); + CYCLES(cpustate, 5); } /* LDD IND, X 0xEC */ -static void HC11OP(ldd_indx)(void) +static void HC11OP(ldd_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - REG_D = READ16(hc11.ix + offset); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + REG_D = READ16(cpustate, cpustate->ix + offset); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(5); + CYCLES(cpustate, 5); } /* LDD IND, Y 0x18, 0xEC */ -static void HC11OP(ldd_indy)(void) +static void HC11OP(ldd_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - REG_D = READ16(hc11.iy + offset); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + REG_D = READ16(cpustate, cpustate->iy + offset); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(6); + CYCLES(cpustate, 6); } /* LDS IMM 0x8E */ -static void HC11OP(lds_imm)(void) +static void HC11OP(lds_imm)(hc11_state *cpustate) { - CLEAR_NZV(); - hc11.sp = FETCH16(); - SET_N16(hc11.sp); - SET_Z16(hc11.sp); - CYCLES(3); + CLEAR_NZV(cpustate); + cpustate->sp = FETCH16(cpustate); + SET_N16(cpustate->sp); + SET_Z16(cpustate->sp); + CYCLES(cpustate, 3); } /* LDS DIR 0x9E */ -static void HC11OP(lds_dir)(void) +static void HC11OP(lds_dir)(hc11_state *cpustate) { - UINT8 i = FETCH(); - CLEAR_NZV(); - hc11.sp = READ16(i); - SET_N16(hc11.sp); - SET_Z16(hc11.sp); - CYCLES(4); + UINT8 i = FETCH(cpustate); + CLEAR_NZV(cpustate); + cpustate->sp = READ16(cpustate, i); + SET_N16(cpustate->sp); + SET_Z16(cpustate->sp); + CYCLES(cpustate, 4); } /* LDS EXT 0xBE */ -static void HC11OP(lds_ext)(void) +static void HC11OP(lds_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - CLEAR_NZV(); - hc11.sp = READ16(adr); - SET_N16(hc11.sp); - SET_Z16(hc11.sp); - CYCLES(5); + UINT16 adr = FETCH16(cpustate); + CLEAR_NZV(cpustate); + cpustate->sp = READ16(cpustate, adr); + SET_N16(cpustate->sp); + SET_Z16(cpustate->sp); + CYCLES(cpustate, 5); } /* LDS IND, X 0xAE */ -static void HC11OP(lds_indx)(void) +static void HC11OP(lds_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - hc11.sp = READ16(hc11.ix + offset); - SET_N16(hc11.sp); - SET_Z16(hc11.sp); - CYCLES(5); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + cpustate->sp = READ16(cpustate, cpustate->ix + offset); + SET_N16(cpustate->sp); + SET_Z16(cpustate->sp); + CYCLES(cpustate, 5); } /* LDS IND, Y 0x18, 0xAE */ -static void HC11OP(lds_indy)(void) +static void HC11OP(lds_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - hc11.sp = READ16(hc11.iy + offset); - SET_N16(hc11.sp); - SET_Z16(hc11.sp); - CYCLES(6); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + cpustate->sp = READ16(cpustate, cpustate->iy + offset); + SET_N16(cpustate->sp); + SET_Z16(cpustate->sp); + CYCLES(cpustate, 6); } /* LDX IMM 0xCE */ -static void HC11OP(ldx_imm)(void) +static void HC11OP(ldx_imm)(hc11_state *cpustate) { - CLEAR_NZV(); - hc11.ix = FETCH16(); - SET_N16(hc11.ix); - SET_Z16(hc11.ix); - CYCLES(3); + CLEAR_NZV(cpustate); + cpustate->ix = FETCH16(cpustate); + SET_N16(cpustate->ix); + SET_Z16(cpustate->ix); + CYCLES(cpustate, 3); } /* LDX DIR 0xDE */ -static void HC11OP(ldx_dir)(void) +static void HC11OP(ldx_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - CLEAR_NZV(); - hc11.ix = READ16(d); - SET_N16(hc11.ix); - SET_Z16(hc11.ix); - CYCLES(4); + UINT8 d = FETCH(cpustate); + CLEAR_NZV(cpustate); + cpustate->ix = READ16(cpustate, d); + SET_N16(cpustate->ix); + SET_Z16(cpustate->ix); + CYCLES(cpustate, 4); } /* LDX EXT 0xFE */ -static void HC11OP(ldx_ext)(void) +static void HC11OP(ldx_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - CLEAR_NZV(); - hc11.ix = READ16(adr); - SET_N16(hc11.ix); - SET_Z16(hc11.ix); - CYCLES(5); + UINT16 adr = FETCH16(cpustate); + CLEAR_NZV(cpustate); + cpustate->ix = READ16(cpustate, adr); + SET_N16(cpustate->ix); + SET_Z16(cpustate->ix); + CYCLES(cpustate, 5); } /* LDX IND, X 0xEE */ -static void HC11OP(ldx_indx)(void) +static void HC11OP(ldx_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - hc11.ix = READ16(hc11.ix + offset); - SET_N16(hc11.ix); - SET_Z16(hc11.ix); - CYCLES(5); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + cpustate->ix = READ16(cpustate, cpustate->ix + offset); + SET_N16(cpustate->ix); + SET_Z16(cpustate->ix); + CYCLES(cpustate, 5); } /* LDX IND, Y 0xCD, 0xEE */ -static void HC11OP(ldx_indy)(void) +static void HC11OP(ldx_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - hc11.ix = READ16(hc11.iy + offset); - SET_N16(hc11.ix); - SET_Z16(hc11.ix); - CYCLES(6); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + cpustate->ix = READ16(cpustate, cpustate->iy + offset); + SET_N16(cpustate->ix); + SET_Z16(cpustate->ix); + CYCLES(cpustate, 6); } /* LDY IMM 0x18, 0xCE */ -static void HC11OP(ldy_imm)(void) +static void HC11OP(ldy_imm)(hc11_state *cpustate) { - CLEAR_NZV(); - hc11.iy = FETCH16(); - SET_N16(hc11.iy); - SET_Z16(hc11.iy); - CYCLES(4); + CLEAR_NZV(cpustate); + cpustate->iy = FETCH16(cpustate); + SET_N16(cpustate->iy); + SET_Z16(cpustate->iy); + CYCLES(cpustate, 4); } /* LDY DIR 0x18, 0xDE */ -static void HC11OP(ldy_dir)(void) +static void HC11OP(ldy_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - CLEAR_NZV(); - hc11.iy = READ16(d); - SET_N16(hc11.iy); - SET_Z16(hc11.iy); - CYCLES(5); + UINT8 d = FETCH(cpustate); + CLEAR_NZV(cpustate); + cpustate->iy = READ16(cpustate, d); + SET_N16(cpustate->iy); + SET_Z16(cpustate->iy); + CYCLES(cpustate, 5); } /* LDY EXT 0x18, 0xFE */ -static void HC11OP(ldy_ext)(void) +static void HC11OP(ldy_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - CLEAR_NZV(); - hc11.iy = READ16(adr); - SET_N16(hc11.iy); - SET_Z16(hc11.iy); - CYCLES(6); + UINT16 adr = FETCH16(cpustate); + CLEAR_NZV(cpustate); + cpustate->iy = READ16(cpustate, adr); + SET_N16(cpustate->iy); + SET_Z16(cpustate->iy); + CYCLES(cpustate, 6); } /* LDY IND, X 0x1A, 0xEE */ -static void HC11OP(ldy_indx)(void) +static void HC11OP(ldy_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - hc11.iy = READ16(hc11.ix + offset); - SET_N16(hc11.iy); - SET_Z16(hc11.iy); - CYCLES(6); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + cpustate->iy = READ16(cpustate, cpustate->ix + offset); + SET_N16(cpustate->iy); + SET_Z16(cpustate->iy); + CYCLES(cpustate, 6); } /* LDY IND, Y 0x18, 0xEE */ -static void HC11OP(ldy_indy)(void) +static void HC11OP(ldy_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - hc11.iy = READ16(hc11.iy + offset); - SET_N16(hc11.iy); - SET_Z16(hc11.iy); - CYCLES(6); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + cpustate->iy = READ16(cpustate, cpustate->iy + offset); + SET_N16(cpustate->iy); + SET_Z16(cpustate->iy); + CYCLES(cpustate, 6); } /* LSLD 0x05 */ -static void HC11OP(lsld)(void) +static void HC11OP(lsld)(hc11_state *cpustate) { UINT32 r = REG_D << 1; - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_C16(r); REG_D = (UINT16)(r); SET_N16(REG_D); SET_Z16(REG_D); - if (((hc11.ccr & CC_N) == CC_N && (hc11.ccr & CC_C) == 0) || - ((hc11.ccr & CC_N) == 0 && (hc11.ccr & CC_C) == CC_C)) + if (((cpustate->ccr & CC_N) == CC_N && (cpustate->ccr & CC_C) == 0) || + ((cpustate->ccr & CC_N) == 0 && (cpustate->ccr & CC_C) == CC_C)) { - hc11.ccr |= CC_V; + cpustate->ccr |= CC_V; } - CYCLES(3); + CYCLES(cpustate, 3); } /* PSHA 0x36 */ -static void HC11OP(psha)(void) +static void HC11OP(psha)(hc11_state *cpustate) { - PUSH8(REG_A); - CYCLES(3); + PUSH8(cpustate, REG_A); + CYCLES(cpustate, 3); } /* ORAA IMM 0x8A */ -static void HC11OP(oraa_imm)(void) +static void HC11OP(oraa_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); - CLEAR_NZV(); + UINT8 i = FETCH(cpustate); + CLEAR_NZV(cpustate); REG_A |= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(2); + CYCLES(cpustate, 2); } /* ORAA DIR 0x9A */ -static void HC11OP(oraa_dir)(void) +static void HC11OP(oraa_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); - CLEAR_NZV(); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); + CLEAR_NZV(cpustate); REG_A |= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(3); + CYCLES(cpustate, 3); } /* ORAA EXT 0xBA */ -static void HC11OP(oraa_ext)(void) +static void HC11OP(oraa_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); - CLEAR_NZV(); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); + CLEAR_NZV(cpustate); REG_A |= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(4); + CYCLES(cpustate, 4); } /* ORAA IND, X 0xAA */ -static void HC11OP(oraa_indx)(void) +static void HC11OP(oraa_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); + CLEAR_NZV(cpustate); REG_A |= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(4); + CYCLES(cpustate, 4); } /* ORAA IND, Y 0x18, 0xAA */ -static void HC11OP(oraa_indy)(void) +static void HC11OP(oraa_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); + CLEAR_NZV(cpustate); REG_A |= i; SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(5); + CYCLES(cpustate, 5); } /* ORAB IMM 0xCA */ -static void HC11OP(orab_imm)(void) +static void HC11OP(orab_imm)(hc11_state *cpustate) { - UINT8 i = FETCH(); - CLEAR_NZV(); + UINT8 i = FETCH(cpustate); + CLEAR_NZV(cpustate); REG_B |= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(2); + CYCLES(cpustate, 2); } /* ORAB DIR 0xDA */ -static void HC11OP(orab_dir)(void) +static void HC11OP(orab_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - UINT8 i = READ8(d); - CLEAR_NZV(); + UINT8 d = FETCH(cpustate); + UINT8 i = READ8(cpustate, d); + CLEAR_NZV(cpustate); REG_B |= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(3); + CYCLES(cpustate, 3); } /* ORAB EXT 0xFA */ -static void HC11OP(orab_ext)(void) +static void HC11OP(orab_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); - CLEAR_NZV(); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); + CLEAR_NZV(cpustate); REG_B |= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(4); + CYCLES(cpustate, 4); } /* ORAB IND, X 0xEA */ -static void HC11OP(orab_indx)(void) +static void HC11OP(orab_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); + CLEAR_NZV(cpustate); REG_B |= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(4); + CYCLES(cpustate, 4); } /* ORAB IND, Y 0x18, 0xEA */ -static void HC11OP(orab_indy)(void) +static void HC11OP(orab_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); + CLEAR_NZV(cpustate); REG_B |= i; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(5); + CYCLES(cpustate, 5); } /* PSHB 0x37 */ -static void HC11OP(pshb)(void) +static void HC11OP(pshb)(hc11_state *cpustate) { - PUSH8(REG_B); - CYCLES(3); + PUSH8(cpustate, REG_B); + CYCLES(cpustate, 3); } /* PSHX 0x3C */ -static void HC11OP(pshx)(void) +static void HC11OP(pshx)(hc11_state *cpustate) { - PUSH16(hc11.ix); - CYCLES(4); + PUSH16(cpustate, cpustate->ix); + CYCLES(cpustate, 4); } /* PSHY 0x18, 0x3C */ -static void HC11OP(pshy)(void) +static void HC11OP(pshy)(hc11_state *cpustate) { - PUSH16(hc11.iy); - CYCLES(5); + PUSH16(cpustate, cpustate->iy); + CYCLES(cpustate, 5); } /* PULA 0x32 */ -static void HC11OP(pula)(void) +static void HC11OP(pula)(hc11_state *cpustate) { - REG_A = POP8(); - CYCLES(4); + REG_A = POP8(cpustate); + CYCLES(cpustate, 4); } /* PULB 0x33 */ -static void HC11OP(pulb)(void) +static void HC11OP(pulb)(hc11_state *cpustate) { - REG_B = POP8(); - CYCLES(4); + REG_B = POP8(cpustate); + CYCLES(cpustate, 4); } /* PULX 0x38 */ -static void HC11OP(pulx)(void) +static void HC11OP(pulx)(hc11_state *cpustate) { - hc11.ix = POP16(); - CYCLES(5); + cpustate->ix = POP16(cpustate); + CYCLES(cpustate, 5); } /* PULY 0x18, 0x38 */ -static void HC11OP(puly)(void) +static void HC11OP(puly)(hc11_state *cpustate) { - hc11.iy = POP16(); - CYCLES(6); + cpustate->iy = POP16(cpustate); + CYCLES(cpustate, 6); } /* RTS 0x39 */ -static void HC11OP(rts)(void) +static void HC11OP(rts)(hc11_state *cpustate) { - UINT16 rt_adr = POP16(); - SET_PC(rt_adr); - CYCLES(5); + UINT16 rt_adr = POP16(cpustate); + SET_PC(cpustate, rt_adr); + CYCLES(cpustate, 5); } /* SEI 0x0F */ -static void HC11OP(sei)(void) +static void HC11OP(sei)(hc11_state *cpustate) { - hc11.ccr |= CC_I; - CYCLES(2); + cpustate->ccr |= CC_I; + CYCLES(cpustate, 2); } /* STAA DIR 0x97 */ -static void HC11OP(staa_dir)(void) +static void HC11OP(staa_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - CLEAR_NZV(); + UINT8 d = FETCH(cpustate); + CLEAR_NZV(cpustate); SET_N8(REG_A); SET_Z8(REG_A); - WRITE8(d, REG_A); - CYCLES(3); + WRITE8(cpustate, d, REG_A); + CYCLES(cpustate, 3); } /* STAA EXT 0xB7 */ -static void HC11OP(staa_ext)(void) +static void HC11OP(staa_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - CLEAR_NZV(); + UINT16 adr = FETCH16(cpustate); + CLEAR_NZV(cpustate); SET_N8(REG_A); SET_Z8(REG_A); - WRITE8(adr, REG_A); - CYCLES(4); + WRITE8(cpustate, adr, REG_A); + CYCLES(cpustate, 4); } /* STAA IND, X 0xA7 */ -static void HC11OP(staa_indx)(void) +static void HC11OP(staa_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); SET_N8(REG_A); SET_Z8(REG_A); - WRITE8(hc11.ix + offset, REG_A); - CYCLES(4); + WRITE8(cpustate, cpustate->ix + offset, REG_A); + CYCLES(cpustate, 4); } /* STAA IND, Y 0x18, 0xA7 */ -static void HC11OP(staa_indy)(void) +static void HC11OP(staa_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); SET_N8(REG_A); SET_Z8(REG_A); - WRITE8(hc11.iy + offset, REG_A); - CYCLES(5); + WRITE8(cpustate, cpustate->iy + offset, REG_A); + CYCLES(cpustate, 5); } /* STAB DIR 0xD7 */ -static void HC11OP(stab_dir)(void) +static void HC11OP(stab_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - CLEAR_NZV(); + UINT8 d = FETCH(cpustate); + CLEAR_NZV(cpustate); SET_N8(REG_B); SET_Z8(REG_B); - WRITE8(d, REG_B); - CYCLES(3); + WRITE8(cpustate, d, REG_B); + CYCLES(cpustate, 3); } /* STAB EXT 0xF7 */ -static void HC11OP(stab_ext)(void) +static void HC11OP(stab_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - CLEAR_NZV(); + UINT16 adr = FETCH16(cpustate); + CLEAR_NZV(cpustate); SET_N8(REG_B); SET_Z8(REG_B); - WRITE8(adr, REG_B); - CYCLES(4); + WRITE8(cpustate, adr, REG_B); + CYCLES(cpustate, 4); } /* STAB IND, X 0xE7 */ -static void HC11OP(stab_indx)(void) +static void HC11OP(stab_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); SET_N8(REG_B); SET_Z8(REG_B); - WRITE8(hc11.ix + offset, REG_B); - CYCLES(4); + WRITE8(cpustate, cpustate->ix + offset, REG_B); + CYCLES(cpustate, 4); } /* STAB IND, Y 0x18, 0xE7 */ -static void HC11OP(stab_indy)(void) +static void HC11OP(stab_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); SET_N8(REG_B); SET_Z8(REG_B); - WRITE8(hc11.iy + offset, REG_B); - CYCLES(5); + WRITE8(cpustate, cpustate->iy + offset, REG_B); + CYCLES(cpustate, 5); } /* STD DIR 0xDD */ -static void HC11OP(std_dir)(void) +static void HC11OP(std_dir)(hc11_state *cpustate) { - UINT8 d = FETCH(); - CLEAR_NZV(); - WRITE16(d, REG_D); + UINT8 d = FETCH(cpustate); + CLEAR_NZV(cpustate); + WRITE16(cpustate, d, REG_D); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(4); + CYCLES(cpustate, 4); } /* STD EXT 0xFD */ -static void HC11OP(std_ext)(void) +static void HC11OP(std_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - CLEAR_NZV(); - WRITE16(adr, REG_D); + UINT16 adr = FETCH16(cpustate); + CLEAR_NZV(cpustate); + WRITE16(cpustate, adr, REG_D); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(5); + CYCLES(cpustate, 5); } /* STD IND, X 0xED */ -static void HC11OP(std_indx)(void) +static void HC11OP(std_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - WRITE16(hc11.ix + offset, REG_D); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + WRITE16(cpustate, cpustate->ix + offset, REG_D); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(5); + CYCLES(cpustate, 5); } /* STD IND, Y 0x18, 0xED */ -static void HC11OP(std_indy)(void) +static void HC11OP(std_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - CLEAR_NZV(); - WRITE16(hc11.iy + offset, REG_D); + UINT8 offset = FETCH(cpustate); + CLEAR_NZV(cpustate); + WRITE16(cpustate, cpustate->iy + offset, REG_D); SET_N16(REG_D); SET_Z16(REG_D); - CYCLES(6); + CYCLES(cpustate, 6); } /* TAB 0x16 */ -static void HC11OP(tab)(void) +static void HC11OP(tab)(hc11_state *cpustate) { - CLEAR_NZV(); + CLEAR_NZV(cpustate); REG_B = REG_A; SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(2); + CYCLES(cpustate, 2); } /* TAP 0x06 */ -static void HC11OP(tap)(void) +static void HC11OP(tap)(hc11_state *cpustate) { - UINT8 ccr = hc11.ccr; - hc11.ccr = (REG_A & 0xbf) | (ccr & 0x40); - CYCLES(2); + UINT8 ccr = cpustate->ccr; + cpustate->ccr = (REG_A & 0xbf) | (ccr & 0x40); + CYCLES(cpustate, 2); } /* TPA 0x07 */ -static void HC11OP(tpa)(void) +static void HC11OP(tpa)(hc11_state *cpustate) { - REG_A = hc11.ccr; - CYCLES(2); + REG_A = cpustate->ccr; + CYCLES(cpustate, 2); } /* TSTA 0x4D */ -static void HC11OP(tsta)(void) +static void HC11OP(tsta)(hc11_state *cpustate) { - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(REG_A); SET_Z8(REG_A); - CYCLES(2); + CYCLES(cpustate, 2); } /* TSTB 0x5D */ -static void HC11OP(tstb)(void) +static void HC11OP(tstb)(hc11_state *cpustate) { - CLEAR_NZVC(); + CLEAR_NZVC(cpustate); SET_N8(REG_B); SET_Z8(REG_B); - CYCLES(2); + CYCLES(cpustate, 2); } /* TST EXT 0x7D */ -static void HC11OP(tst_ext)(void) +static void HC11OP(tst_ext)(hc11_state *cpustate) { - UINT16 adr = FETCH16(); - UINT8 i = READ8(adr); - CLEAR_NZVC(); + UINT16 adr = FETCH16(cpustate); + UINT8 i = READ8(cpustate, adr); + CLEAR_NZVC(cpustate); SET_N8(i); SET_Z8(i); - CYCLES(6); + CYCLES(cpustate, 6); } /* TST IND, X 0x6D */ -static void HC11OP(tst_indx)(void) +static void HC11OP(tst_indx)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.ix + offset); - CLEAR_NZVC(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->ix + offset); + CLEAR_NZVC(cpustate); SET_N8(i); SET_Z8(i); - CYCLES(6); + CYCLES(cpustate, 6); } /* TST IND, Y 0x18, 0x6D */ -static void HC11OP(tst_indy)(void) +static void HC11OP(tst_indy)(hc11_state *cpustate) { - UINT8 offset = FETCH(); - UINT8 i = READ8(hc11.iy + offset); - CLEAR_NZVC(); + UINT8 offset = FETCH(cpustate); + UINT8 i = READ8(cpustate, cpustate->iy + offset); + CLEAR_NZVC(cpustate); SET_N8(i); SET_Z8(i); - CYCLES(6); + CYCLES(cpustate, 6); } /* XGDX 0x8F */ -static void HC11OP(xgdx)(void) +static void HC11OP(xgdx)(hc11_state *cpustate) { UINT16 tmp = REG_D; - REG_D = hc11.ix; - hc11.ix = tmp; - CYCLES(3); + REG_D = cpustate->ix; + cpustate->ix = tmp; + CYCLES(cpustate, 3); } /* XGDY 0x18, 0x8F */ -static void HC11OP(xgdy)(void) +static void HC11OP(xgdy)(hc11_state *cpustate) { UINT16 tmp = REG_D; - REG_D = hc11.iy; - hc11.iy = tmp; - CYCLES(4); + REG_D = cpustate->iy; + cpustate->iy = tmp; + CYCLES(cpustate, 4); } /*****************************************************************************/ -static void HC11OP(page2)(void) +static void HC11OP(page2)(hc11_state *cpustate) { - UINT8 op2 = FETCH(); - hc11_optable_page2[op2](); + UINT8 op2 = FETCH(cpustate); + hc11_optable_page2[op2](cpustate); } -static void HC11OP(page3)(void) +static void HC11OP(page3)(hc11_state *cpustate) { - UINT8 op2 = FETCH(); - hc11_optable_page3[op2](); + UINT8 op2 = FETCH(cpustate); + hc11_optable_page3[op2](cpustate); } -static void HC11OP(page4)(void) +static void HC11OP(page4)(hc11_state *cpustate) { - UINT8 op2 = FETCH(); - hc11_optable_page4[op2](); + UINT8 op2 = FETCH(cpustate); + hc11_optable_page4[op2](cpustate); } -static void HC11OP(invalid)(void) +static void HC11OP(invalid)(hc11_state *cpustate) { - fatalerror("HC11: Invalid opcode 0x%02X at %04X", READ8(hc11.pc-1), hc11.pc-1); + fatalerror("HC11: Invalid opcode 0x%02X at %04X", READ8(cpustate, cpustate->pc-1), cpustate->pc-1); } diff --git a/src/emu/cpu/mc68hc11/hc11ops.h b/src/emu/cpu/mc68hc11/hc11ops.h index ea3751d0dfd..716e24d85cd 100644 --- a/src/emu/cpu/mc68hc11/hc11ops.h +++ b/src/emu/cpu/mc68hc11/hc11ops.h @@ -3,7 +3,7 @@ struct _hc11_opcode_list_struct { int page; int opcode; - void (*handler)(void); + void (*handler)(hc11_state *cpustate); }; static const hc11_opcode_list_struct hc11_opcode_list[] = diff --git a/src/emu/cpu/mc68hc11/mc68hc11.c b/src/emu/cpu/mc68hc11/mc68hc11.c index f752e803faf..612279ec938 100644 --- a/src/emu/cpu/mc68hc11/mc68hc11.c +++ b/src/emu/cpu/mc68hc11/mc68hc11.c @@ -26,7 +26,8 @@ enum #define CC_V 0x02 #define CC_C 0x01 -typedef struct +typedef struct _hc11_state hc11_state; +struct _hc11_state { union { struct { @@ -58,25 +59,23 @@ typedef struct int icount; int ram_position; int reg_position; -} HC11_REGS; - -static HC11_REGS hc11; -static UINT8 *internal_ram; -static int internal_ram_size; + UINT8 *internal_ram; + int internal_ram_size; +}; #define HC11OP(XX) hc11_##XX /*****************************************************************************/ /* Internal registers */ -static UINT8 hc11_regs_r(UINT32 address) +static UINT8 hc11_regs_r(hc11_state *cpustate, UINT32 address) { int reg = address & 0xff; switch(reg) { case 0x00: /* PORTA */ - return memory_read_byte(hc11.io, MC68HC11_IO_PORTA); + return memory_read_byte(cpustate->io, MC68HC11_IO_PORTA); case 0x01: /* DDRA */ return 0; case 0x09: /* DDRD */ @@ -87,46 +86,46 @@ static UINT8 hc11_regs_r(UINT32 address) return 0x80; case 0x31: /* ADR1 */ { - if (hc11.adctl & 0x10) + if (cpustate->adctl & 0x10) { - return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD0); + return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD0); } else { - return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); + return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x32: /* ADR2 */ { - if (hc11.adctl & 0x10) + if (cpustate->adctl & 0x10) { - return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD1); + return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD1); } else { - return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); + return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x33: /* ADR3 */ { - if (hc11.adctl & 0x10) + if (cpustate->adctl & 0x10) { - return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD2); + return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD2); } else { - return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); + return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x34: /* ADR4 */ { - if (hc11.adctl & 0x10) + if (cpustate->adctl & 0x10) { - return memory_read_byte(hc11.io, (hc11.adctl & 0x4) + MC68HC11_IO_AD3); + return memory_read_byte(cpustate->io, (cpustate->adctl & 0x4) + MC68HC11_IO_AD3); } else { - return memory_read_byte(hc11.io, (hc11.adctl & 0x7) + MC68HC11_IO_AD0); + return memory_read_byte(cpustate->io, (cpustate->adctl & 0x7) + MC68HC11_IO_AD0); } } case 0x38: /* OPT2 */ @@ -142,9 +141,9 @@ static UINT8 hc11_regs_r(UINT32 address) case 0x74: /* SCSR1 */ return 0x40; case 0x7c: /* PORTH */ - return memory_read_byte(hc11.io, MC68HC11_IO_PORTH); + return memory_read_byte(cpustate->io, MC68HC11_IO_PORTH); case 0x7e: /* PORTG */ - return memory_read_byte(hc11.io, MC68HC11_IO_PORTG); + return memory_read_byte(cpustate->io, MC68HC11_IO_PORTG); case 0x7f: /* DDRG */ return 0; @@ -153,7 +152,7 @@ static UINT8 hc11_regs_r(UINT32 address) case 0x89: /* SPSR2 */ return 0x80; case 0x8a: /* SPDR2 */ - return memory_read_byte(hc11.io, MC68HC11_IO_SPI2_DATA); + return memory_read_byte(cpustate->io, MC68HC11_IO_SPI2_DATA); case 0x8b: /* OPT4 */ return 0; @@ -163,20 +162,20 @@ static UINT8 hc11_regs_r(UINT32 address) return 0; // Dummy } -static void hc11_regs_w(UINT32 address, UINT8 value) +static void hc11_regs_w(hc11_state *cpustate, UINT32 address, UINT8 value) { int reg = address & 0xff; switch(reg) { case 0x00: /* PORTA */ - memory_write_byte(hc11.io, MC68HC11_IO_PORTA, value); + memory_write_byte(cpustate->io, MC68HC11_IO_PORTA, value); return; case 0x01: /* DDRA */ //mame_printf_debug("HC11: ddra = %02X\n", value); return; case 0x08: /* PORTD */ - memory_write_byte(hc11.io, MC68HC11_IO_PORTD, value); + memory_write_byte(cpustate->io, MC68HC11_IO_PORTD, value); return; case 0x09: /* DDRD */ //mame_printf_debug("HC11: ddrd = %02X\n", value); @@ -188,7 +187,7 @@ static void hc11_regs_w(UINT32 address, UINT8 value) case 0x28: /* SPCR1 */ return; case 0x30: /* ADCTL */ - hc11.adctl = value; + cpustate->adctl = value; return; case 0x38: /* OPT2 */ return; @@ -201,11 +200,11 @@ static void hc11_regs_w(UINT32 address, UINT8 value) int ram_page = (value >> 4) & 0xf; if (reg_page == ram_page) { - hc11.reg_position = reg_page << 12; - hc11.ram_position = (ram_page << 12) + 0x100; + cpustate->reg_position = reg_page << 12; + cpustate->ram_position = (ram_page << 12) + 0x100; } else { - hc11.reg_position = reg_page << 12; - hc11.ram_position = ram_page << 12; + cpustate->reg_position = reg_page << 12; + cpustate->ram_position = ram_page << 12; } return; } @@ -224,16 +223,16 @@ static void hc11_regs_w(UINT32 address, UINT8 value) case 0x77: /* SCDRL */ return; case 0x7c: /* PORTH */ - memory_write_byte(hc11.io, MC68HC11_IO_PORTH, value); + memory_write_byte(cpustate->io, MC68HC11_IO_PORTH, value); return; case 0x7d: /* DDRH */ - //mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, hc11.pc); + //mame_printf_debug("HC11: ddrh = %02X at %04X\n", value, cpustate->pc); return; case 0x7e: /* PORTG */ - memory_write_byte(hc11.io, MC68HC11_IO_PORTG, value); + memory_write_byte(cpustate->io, MC68HC11_IO_PORTG, value); return; case 0x7f: /* DDRG */ - //mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, hc11.pc); + //mame_printf_debug("HC11: ddrg = %02X at %04X\n", value, cpustate->pc); return; case 0x88: /* SPCR2 */ @@ -241,7 +240,7 @@ static void hc11_regs_w(UINT32 address, UINT8 value) case 0x89: /* SPSR2 */ return; case 0x8a: /* SPDR2 */ - memory_write_byte(hc11.io, MC68HC11_IO_SPI2_DATA, value); + memory_write_byte(cpustate->io, MC68HC11_IO_SPI2_DATA, value); return; case 0x8b: /* OPT4 */ @@ -253,70 +252,71 @@ static void hc11_regs_w(UINT32 address, UINT8 value) /*****************************************************************************/ -INLINE UINT8 FETCH(void) +INLINE UINT8 FETCH(hc11_state *cpustate) { - return memory_decrypted_read_byte(hc11.program, hc11.pc++); + return memory_decrypted_read_byte(cpustate->program, cpustate->pc++); } -INLINE UINT16 FETCH16(void) +INLINE UINT16 FETCH16(hc11_state *cpustate) { UINT16 w; - w = (memory_decrypted_read_byte(hc11.program, hc11.pc) << 8) | (memory_decrypted_read_byte(hc11.program, hc11.pc+1)); - hc11.pc += 2; + w = (memory_decrypted_read_byte(cpustate->program, cpustate->pc) << 8) | (memory_decrypted_read_byte(cpustate->program, cpustate->pc+1)); + cpustate->pc += 2; return w; } -INLINE UINT8 READ8(UINT32 address) +INLINE UINT8 READ8(hc11_state *cpustate, UINT32 address) { - if(address >= hc11.reg_position && address < hc11.reg_position+0x100) + if(address >= cpustate->reg_position && address < cpustate->reg_position+0x100) { - return hc11_regs_r(address); + return hc11_regs_r(cpustate, address); } - else if(address >= hc11.ram_position && address < hc11.ram_position+internal_ram_size) + else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size) { - return internal_ram[address-hc11.ram_position]; + return cpustate->internal_ram[address-cpustate->ram_position]; } - return memory_read_byte(hc11.program, address); + return memory_read_byte(cpustate->program, address); } -INLINE void WRITE8(UINT32 address, UINT8 value) +INLINE void WRITE8(hc11_state *cpustate, UINT32 address, UINT8 value) { - if(address >= hc11.reg_position && address < hc11.reg_position+0x100) + if(address >= cpustate->reg_position && address < cpustate->reg_position+0x100) { - hc11_regs_w(address, value); + hc11_regs_w(cpustate, address, value); return; } - else if(address >= hc11.ram_position && address < hc11.ram_position+internal_ram_size) + else if(address >= cpustate->ram_position && address < cpustate->ram_position+cpustate->internal_ram_size) { - internal_ram[address-hc11.ram_position] = value; + cpustate->internal_ram[address-cpustate->ram_position] = value; return; } - memory_write_byte(hc11.program, address, value); + memory_write_byte(cpustate->program, address, value); } -INLINE UINT16 READ16(UINT32 address) +INLINE UINT16 READ16(hc11_state *cpustate, UINT32 address) { - return (READ8(address) << 8) | (READ8(address+1)); + return (READ8(cpustate, address) << 8) | (READ8(cpustate, address+1)); } -INLINE void WRITE16(UINT32 address, UINT16 value) +INLINE void WRITE16(hc11_state *cpustate, UINT32 address, UINT16 value) { - WRITE8(address+0, (value >> 8) & 0xff); - WRITE8(address+1, (value >> 0) & 0xff); + WRITE8(cpustate, address+0, (value >> 8) & 0xff); + WRITE8(cpustate, address+1, (value >> 0) & 0xff); } /*****************************************************************************/ -static void (*hc11_optable[256])(void); -static void (*hc11_optable_page2[256])(void); -static void (*hc11_optable_page3[256])(void); -static void (*hc11_optable_page4[256])(void); +static void (*hc11_optable[256])(hc11_state *cpustate); +static void (*hc11_optable_page2[256])(hc11_state *cpustate); +static void (*hc11_optable_page3[256])(hc11_state *cpustate); +static void (*hc11_optable_page4[256])(hc11_state *cpustate); #include "hc11ops.c" #include "hc11ops.h" static CPU_INIT( hc11 ) { + hc11_state *cpustate = device->token; int i; /* clear the opcode tables */ @@ -346,20 +346,21 @@ static CPU_INIT( hc11 ) } } - internal_ram_size = 1280; /* FIXME: this is for MC68HC11M0 */ - internal_ram = auto_malloc(internal_ram_size); + cpustate->internal_ram_size = 1280; /* FIXME: this is for MC68HC11M0 */ + cpustate->internal_ram = auto_malloc(cpustate->internal_ram_size); - hc11.reg_position = 0; - hc11.ram_position = 0x100; - hc11.irq_callback = irqcallback; - hc11.device = device; - hc11.program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); - hc11.io = memory_find_address_space(device, ADDRESS_SPACE_IO); + cpustate->reg_position = 0; + cpustate->ram_position = 0x100; + cpustate->irq_callback = irqcallback; + cpustate->device = device; + cpustate->program = memory_find_address_space(device, ADDRESS_SPACE_PROGRAM); + cpustate->io = memory_find_address_space(device, ADDRESS_SPACE_IO); } static CPU_RESET( hc11 ) { - hc11.pc = READ16(0xfffe); + hc11_state *cpustate = device->token; + cpustate->pc = READ16(cpustate, 0xfffe); } static CPU_EXIT( hc11 ) @@ -367,61 +368,53 @@ static CPU_EXIT( hc11 ) } -static CPU_GET_CONTEXT( hc11 ) -{ - if (dst) { - *(HC11_REGS*)dst = hc11; - } -} - -static CPU_SET_CONTEXT( hc11 ) -{ - if (src) { - hc11 = *(HC11_REGS*)src; - } -} - static CPU_EXECUTE( hc11 ) { - hc11.icount = cycles; + hc11_state *cpustate = device->token; + + cpustate->icount = cycles; - while(hc11.icount > 0) + while(cpustate->icount > 0) { UINT8 op; - hc11.ppc = hc11.pc; - debugger_instruction_hook(device, hc11.pc); + cpustate->ppc = cpustate->pc; + debugger_instruction_hook(device, cpustate->pc); - op = FETCH(); - hc11_optable[op](); + op = FETCH(cpustate); + hc11_optable[op](cpustate); } - return cycles-hc11.icount; + return cycles-cpustate->icount; } /*****************************************************************************/ static CPU_SET_INFO( mc68hc11 ) { + hc11_state *cpustate = device->token; + switch (state) { /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_PC: hc11.pc = info->i; break; - case CPUINFO_INT_REGISTER + HC11_PC: hc11.pc = info->i; break; - case CPUINFO_INT_REGISTER + HC11_SP: hc11.sp = info->i; break; - case CPUINFO_INT_REGISTER + HC11_A: hc11.d.d8.a = info->i; break; - case CPUINFO_INT_REGISTER + HC11_B: hc11.d.d8.b = info->i; break; - case CPUINFO_INT_REGISTER + HC11_IX: hc11.ix = info->i; break; - case CPUINFO_INT_REGISTER + HC11_IY: hc11.iy = info->i; break; + case CPUINFO_INT_PC: cpustate->pc = info->i; break; + case CPUINFO_INT_REGISTER + HC11_PC: cpustate->pc = info->i; break; + case CPUINFO_INT_REGISTER + HC11_SP: cpustate->sp = info->i; break; + case CPUINFO_INT_REGISTER + HC11_A: cpustate->d.d8.a = info->i; break; + case CPUINFO_INT_REGISTER + HC11_B: cpustate->d.d8.b = info->i; break; + case CPUINFO_INT_REGISTER + HC11_IX: cpustate->ix = info->i; break; + case CPUINFO_INT_REGISTER + HC11_IY: cpustate->iy = info->i; break; } } CPU_GET_INFO( mc68hc11 ) { + hc11_state *cpustate = (device != NULL) ? device->token : NULL; + switch(state) { /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11); break; + case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(hc11_state); break; case CPUINFO_INT_INPUT_LINES: info->i = 1; break; case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; @@ -447,24 +440,24 @@ CPU_GET_INFO( mc68hc11 ) case CPUINFO_INT_PREVIOUSPC: /* not implemented */ break; case CPUINFO_INT_PC: /* intentional fallthrough */ - case CPUINFO_INT_REGISTER + HC11_PC: info->i = hc11.pc; break; - case CPUINFO_INT_REGISTER + HC11_SP: info->i = hc11.sp; break; - case CPUINFO_INT_REGISTER + HC11_A: info->i = hc11.d.d8.a; break; - case CPUINFO_INT_REGISTER + HC11_B: info->i = hc11.d.d8.b; break; - case CPUINFO_INT_REGISTER + HC11_IX: info->i = hc11.ix; break; - case CPUINFO_INT_REGISTER + HC11_IY: info->i = hc11.iy; break; + case CPUINFO_INT_REGISTER + HC11_PC: info->i = cpustate->pc; break; + case CPUINFO_INT_REGISTER + HC11_SP: info->i = cpustate->sp; break; + case CPUINFO_INT_REGISTER + HC11_A: info->i = cpustate->d.d8.a; break; + case CPUINFO_INT_REGISTER + HC11_B: info->i = cpustate->d.d8.b; break; + case CPUINFO_INT_REGISTER + HC11_IX: info->i = cpustate->ix; break; + case CPUINFO_INT_REGISTER + HC11_IY: info->i = cpustate->iy; break; /* --- the following bits of info are returned as pointers to data or functions --- */ case CPUINFO_PTR_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(mc68hc11); break; - case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(hc11); break; - case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(hc11); break; + case CPUINFO_PTR_GET_CONTEXT: info->getcontext = CPU_GET_CONTEXT_NAME(dummy); break; + case CPUINFO_PTR_SET_CONTEXT: info->setcontext = CPU_SET_CONTEXT_NAME(dummy); break; case CPUINFO_PTR_INIT: info->init = CPU_INIT_NAME(hc11); break; case CPUINFO_PTR_RESET: info->reset = CPU_RESET_NAME(hc11); break; case CPUINFO_PTR_EXIT: info->exit = CPU_EXIT_NAME(hc11); break; case CPUINFO_PTR_EXECUTE: info->execute = CPU_EXECUTE_NAME(hc11); break; case CPUINFO_PTR_BURN: info->burn = NULL; break; case CPUINFO_PTR_DISASSEMBLE: info->disassemble = hc11_disasm; break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &hc11.icount; break; + case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &cpustate->icount; break; /* --- the following bits of info are returned as NULL-terminated strings --- */ case CPUINFO_STR_NAME: strcpy(info->s, "MC68HC11"); break; @@ -475,21 +468,21 @@ CPU_GET_INFO( mc68hc11 ) case CPUINFO_STR_FLAGS: sprintf(info->s, "%c%c%c%c%c%c%c%c", - (hc11.ccr & CC_S) ? 'S' : '.', - (hc11.ccr & CC_X) ? 'X' : '.', - (hc11.ccr & CC_H) ? 'H' : '.', - (hc11.ccr & CC_I) ? 'I' : '.', - (hc11.ccr & CC_N) ? 'N' : '.', - (hc11.ccr & CC_Z) ? 'Z' : '.', - (hc11.ccr & CC_V) ? 'V' : '.', - (hc11.ccr & CC_C) ? 'C' : '.'); + (cpustate->ccr & CC_S) ? 'S' : '.', + (cpustate->ccr & CC_X) ? 'X' : '.', + (cpustate->ccr & CC_H) ? 'H' : '.', + (cpustate->ccr & CC_I) ? 'I' : '.', + (cpustate->ccr & CC_N) ? 'N' : '.', + (cpustate->ccr & CC_Z) ? 'Z' : '.', + (cpustate->ccr & CC_V) ? 'V' : '.', + (cpustate->ccr & CC_C) ? 'C' : '.'); break; - case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", hc11.pc); break; - case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", hc11.sp); break; - case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", hc11.d.d8.a); break; - case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", hc11.d.d8.b); break; - case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", hc11.ix); break; - case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", hc11.iy); break; + case CPUINFO_STR_REGISTER + HC11_PC: sprintf(info->s, "PC: %04X", cpustate->pc); break; + case CPUINFO_STR_REGISTER + HC11_SP: sprintf(info->s, "SP: %04X", cpustate->sp); break; + case CPUINFO_STR_REGISTER + HC11_A: sprintf(info->s, "A: %02X", cpustate->d.d8.a); break; + case CPUINFO_STR_REGISTER + HC11_B: sprintf(info->s, "B: %02X", cpustate->d.d8.b); break; + case CPUINFO_STR_REGISTER + HC11_IX: sprintf(info->s, "IX: %04X", cpustate->ix); break; + case CPUINFO_STR_REGISTER + HC11_IY: sprintf(info->s, "IY: %04X", cpustate->iy); break; } }