mirror of
https://github.com/holub/mame
synced 2025-04-22 08:22:15 +03:00
created a new device for the bus master ide controller, but the implementation is still in the ide controller. (nw)
This commit is contained in:
smf-
parent
cf58f7f28b
commit
b0a5f6fa03
@ -188,44 +188,6 @@ static TIMER_CALLBACK( reset_callback )
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/*************************************
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*
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* Convert offset/mem_mask to offset
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* and size
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*
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*************************************/
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INLINE int convert_to_offset_and_size32(offs_t *offset, UINT32 mem_mask)
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{
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int size = 4;
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/* determine which real offset */
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if (!ACCESSING_BITS_0_7)
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{
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(*offset)++, size = 3;
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if (!ACCESSING_BITS_8_15)
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{
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(*offset)++, size = 2;
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if (!ACCESSING_BITS_16_23)
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(*offset)++, size = 1;
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}
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}
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/* determine the real size */
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if (ACCESSING_BITS_24_31)
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return size;
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size--;
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if (ACCESSING_BITS_16_23)
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return size;
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size--;
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if (ACCESSING_BITS_8_15)
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return size;
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size--;
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return size;
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}
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/*************************************
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*
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* Advance to the next sector
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@ -1387,21 +1349,20 @@ WRITE16_MEMBER( ide_controller_device::write_cs1 )
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*
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*************************************/
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UINT32 ide_controller_device::ide_bus_master_read(offs_t offset, int size)
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READ32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_r )
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{
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LOG(("%s:ide_bus_master_read(%d, %d)\n", machine().describe_context(), offset, size));
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LOG(("%s:ide_bus_master32_r(%d, %08x)\n", machine().describe_context(), offset, mem_mask));
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/* command register */
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if (offset == 0)
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switch( offset )
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{
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case 0:
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/* command register/status register */
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return bus_master_command | (bus_master_status << 16);
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/* status register */
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if (offset == 2)
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return bus_master_status;
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/* descriptor table register */
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if (offset == 4)
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case 1:
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/* descriptor table register */
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return bus_master_descriptor;
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}
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return 0xffffffff;
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}
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@ -1414,82 +1375,67 @@ UINT32 ide_controller_device::ide_bus_master_read(offs_t offset, int size)
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*
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*************************************/
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void ide_controller_device::ide_bus_master_write(offs_t offset, int size, UINT32 data)
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WRITE32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_w )
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{
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LOG(("%s:ide_bus_master_write(%d, %d, %08X)\n", machine().describe_context(), offset, size, data));
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LOG(("%s:ide_bus_master32_w(%d, %08x, %08X)\n", machine().describe_context(), offset, mem_mask, data));
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/* command register */
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if (offset == 0)
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switch( offset )
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{
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UINT8 old = bus_master_command;
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UINT8 val = data & 0xff;
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/* save the read/write bit and the start/stop bit */
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bus_master_command = (old & 0xf6) | (val & 0x09);
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bus_master_status = (bus_master_status & ~IDE_BUSMASTER_STATUS_ACTIVE) | (val & 0x01);
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/* handle starting a transfer */
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if (!(old & 1) && (val & 1))
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case 0:
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if( ACCESSING_BITS_0_7 )
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{
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/* reset all the DMA data */
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dma_bytes_left = 0;
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dma_last_buffer = 0;
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dma_descriptor = bus_master_descriptor;
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/* command register */
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UINT8 old = bus_master_command;
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UINT8 val = data & 0xff;
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/* if we're going live, start the pending read/write */
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if (dma_active)
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/* save the read/write bit and the start/stop bit */
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bus_master_command = (old & 0xf6) | (val & 0x09);
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bus_master_status = (bus_master_status & ~IDE_BUSMASTER_STATUS_ACTIVE) | (val & 0x01);
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/* handle starting a transfer */
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if (!(old & 1) && (val & 1))
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{
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if (bus_master_command & 8)
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read_next_sector();
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else
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/* reset all the DMA data */
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dma_bytes_left = 0;
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dma_last_buffer = 0;
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dma_descriptor = bus_master_descriptor;
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/* if we're going live, start the pending read/write */
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if (dma_active)
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{
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read_buffer_from_dma();
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continue_write();
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if (bus_master_command & 8)
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read_next_sector();
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else
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{
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read_buffer_from_dma();
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continue_write();
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}
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}
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}
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}
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}
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/* status register */
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if (offset <= 2 && offset + size > 2)
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{
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UINT8 old = bus_master_status;
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UINT8 val = data >> (8 * (2 - offset));
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if( ACCESSING_BITS_16_23 )
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{
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/* status register */
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UINT8 old = bus_master_status;
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UINT8 val = (data >> 16) & 0xff;
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/* save the DMA capable bits */
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bus_master_status = (old & 0x9f) | (val & 0x60);
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/* save the DMA capable bits */
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bus_master_status = (old & 0x9f) | (val & 0x60);
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/* clear interrupt and error bits */
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if (val & IDE_BUSMASTER_STATUS_IRQ)
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bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ;
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if (val & IDE_BUSMASTER_STATUS_ERROR)
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bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR;
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}
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/* clear interrupt and error bits */
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if (val & IDE_BUSMASTER_STATUS_IRQ)
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bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ;
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if (val & IDE_BUSMASTER_STATUS_ERROR)
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bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR;
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}
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break;
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/* descriptor table register */
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if (offset == 4)
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case 1:
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/* descriptor table register */
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bus_master_descriptor = data & 0xfffffffc;
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}
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READ32_MEMBER( ide_controller_device::ide_bus_master32_r )
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{
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int size;
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offset *= 4;
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size = convert_to_offset_and_size32(&offset, mem_mask);
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return ide_bus_master_read(offset, size) << ((offset & 3) * 8);
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}
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WRITE32_MEMBER( ide_controller_device::ide_bus_master32_w )
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{
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int size;
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offset *= 4;
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size = convert_to_offset_and_size32(&offset, mem_mask);
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ide_bus_master_write(offset, size, data >> ((offset & 3) * 8));
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break;
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}
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}
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@ -1497,11 +1443,21 @@ SLOT_INTERFACE_START(ide_devices)
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SLOT_INTERFACE("hdd", IDE_HARDDISK)
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SLOT_INTERFACE_END
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const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
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ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
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ide_controller_device::ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, type, name, tag, owner, clock),
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status(0),
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bmcpu(NULL),
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bmspace(0),
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dma_space(NULL),
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dma_active(0),
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dma_address_xor(0),
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dma_last_buffer(0),
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dma_address(0),
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dma_descriptor(0),
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dma_bytes_left(0),
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bus_master_command(0),
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bus_master_status(0),
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bus_master_descriptor(0),
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adapter_control(0),
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error(0),
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command(0),
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@ -1512,16 +1468,6 @@ ide_controller_device::ide_controller_device(const machine_config &mconfig, cons
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block_count(0),
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sectors_until_int(0),
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verify_only(0),
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dma_active(0),
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dma_space(NULL),
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dma_address_xor(0),
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dma_last_buffer(0),
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dma_address(0),
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dma_descriptor(0),
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dma_bytes_left(0),
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bus_master_command(0),
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bus_master_status(0),
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bus_master_descriptor(0),
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config_unknown(0),
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config_register_num(0),
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master_password_enable(0),
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@ -1530,9 +1476,53 @@ ide_controller_device::ide_controller_device(const machine_config &mconfig, cons
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user_password(NULL),
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gnetreadlock(0),
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cur_drive(0),
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m_irq_handler(*this),
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m_irq_handler(*this)
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{
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}
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const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
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ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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device_t(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
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bmcpu(NULL),
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bmspace(0)
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bmspace(0),
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dma_space(NULL),
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dma_active(0),
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dma_address_xor(0),
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dma_last_buffer(0),
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dma_address(0),
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dma_descriptor(0),
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dma_bytes_left(0),
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bus_master_command(0),
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bus_master_status(0),
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bus_master_descriptor(0),
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adapter_control(0),
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error(0),
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command(0),
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interrupt_pending(0),
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precomp_offset(0),
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buffer_offset(0),
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sector_count(0),
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block_count(0),
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sectors_until_int(0),
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verify_only(0),
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config_unknown(0),
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config_register_num(0),
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master_password_enable(0),
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user_password_enable(0),
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master_password(NULL),
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user_password(NULL),
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gnetreadlock(0),
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cur_drive(0),
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m_irq_handler(*this)
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{
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}
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const device_type BUS_MASTER_IDE_CONTROLLER = &device_creator<bus_master_ide_controller_device>;
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bus_master_ide_controller_device::bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
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ide_controller_device(mconfig, BUS_MASTER_IDE_CONTROLLER, "Bus Master IDE Controller", tag, owner, clock)
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{
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}
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@ -49,9 +49,6 @@ extern const device_type IDE_SLOT;
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#define MCFG_IDE_CONTROLLER_IRQ_HANDLER(_devcb) \
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devcb = &ide_controller_device::set_irq_handler(*device, DEVCB2_##_devcb);
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#define MCFG_IDE_CONTROLLER_BUS_MASTER(bmcpu, bmspace) \
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ide_controller_device::set_bus_master(*device, bmcpu, bmspace);
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SLOT_INTERFACE_EXTERN(ide_devices);
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SLOT_INTERFACE_EXTERN(ide_devices);
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@ -80,10 +77,10 @@ class ide_controller_device : public device_t
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{
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public:
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ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
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// static configuration helpers
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template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<ide_controller_device &>(device).m_irq_handler.set_callback(object); }
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static void set_bus_master(device_t &device, const char *bmcpu, UINT32 bmspace) {ide_controller_device &ide = downcast<ide_controller_device &>(device); ide.bmcpu = bmcpu; ide.bmspace = bmspace; }
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UINT8 *ide_get_features(int drive);
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void ide_set_gnet_readlock(const UINT8 onoff);
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@ -102,11 +99,6 @@ public:
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DECLARE_WRITE16_MEMBER(write_cs0_pc);
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DECLARE_WRITE16_MEMBER(write_cs1_pc);
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DECLARE_READ32_MEMBER( ide_bus_master32_r );
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DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
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UINT32 ide_bus_master_read(offs_t offset, int size);
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void ide_bus_master_write(offs_t offset, int size, UINT32 data);
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void signal_interrupt();
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void clear_interrupt();
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void read_sector_done();
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@ -119,6 +111,23 @@ protected:
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virtual void device_start();
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virtual void device_reset();
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const char *bmcpu;
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UINT32 bmspace;
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address_space * dma_space;
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UINT8 dma_active;
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UINT8 dma_address_xor;
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UINT8 dma_last_buffer;
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offs_t dma_address;
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offs_t dma_descriptor;
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UINT32 dma_bytes_left;
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UINT8 bus_master_command;
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UINT8 bus_master_status;
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UINT32 bus_master_descriptor;
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void read_next_sector();
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void read_buffer_from_dma();
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void continue_write();
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private:
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void signal_delayed_interrupt(attotime time, int buffer_ready);
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void next_sector();
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@ -126,10 +135,7 @@ private:
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void continue_read();
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void write_buffer_to_dma();
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void read_first_sector();
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void read_next_sector();
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void read_buffer_from_dma();
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void handle_command(UINT8 _command);
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void continue_write();
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UINT8 adapter_control;
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UINT8 error;
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@ -145,18 +151,6 @@ private:
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UINT16 sectors_until_int;
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UINT8 verify_only;
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UINT8 dma_active;
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address_space *dma_space;
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UINT8 dma_address_xor;
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UINT8 dma_last_buffer;
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offs_t dma_address;
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offs_t dma_descriptor;
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UINT32 dma_bytes_left;
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UINT8 bus_master_command;
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UINT8 bus_master_status;
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UINT32 bus_master_descriptor;
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UINT8 config_unknown;
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UINT8 config_register[IDE_CONFIG_REGISTERS];
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UINT8 config_register_num;
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@ -175,10 +169,29 @@ private:
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ide_slot_device *slot[2];
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devcb2_write_line m_irq_handler;
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const char *bmcpu;
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UINT32 bmspace;
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};
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extern const device_type IDE_CONTROLLER;
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#define MCFG_BUS_MASTER_IDE_CONTROLLER_ADD(_tag, _slotintf, _master, _slave, _fixed) \
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MCFG_IDE_SLOT_ADD("drive_0", _slotintf, _master, _fixed) \
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MCFG_IDE_SLOT_ADD("drive_1", _slotintf, _slave, _fixed) \
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MCFG_DEVICE_ADD(_tag, BUS_MASTER_IDE_CONTROLLER, 0)
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#define MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(bmcpu, bmspace) \
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bus_master_ide_controller_device::set_bus_master_space(*device, bmcpu, bmspace);
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class bus_master_ide_controller_device : public ide_controller_device
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{
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public:
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bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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static void set_bus_master_space(device_t &device, const char *bmcpu, UINT32 bmspace) {bus_master_ide_controller_device &ide = downcast<bus_master_ide_controller_device &>(device); ide.bmcpu = bmcpu; ide.bmspace = bmspace; }
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DECLARE_READ32_MEMBER( ide_bus_master32_r );
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DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
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};
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extern const device_type BUS_MASTER_IDE_CONTROLLER;
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#endif /* __IDECTRL_H__ */
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@ -410,7 +410,7 @@ public:
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struct chihiro_devices {
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pic8259_device *pic8259_1;
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pic8259_device *pic8259_2;
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ide_controller_device *ide;
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bus_master_ide_controller_device *ide;
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} chihiro_devs;
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nv2a_renderer *nvidia_nv2a;
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@ -2945,11 +2945,11 @@ static ADDRESS_MAP_START(xbox_map_io, AS_IO, 32, chihiro_state )
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AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff)
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AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff)
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AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff)
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AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
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AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
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AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
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AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w)
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AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w)
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AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
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AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
|
||||
ADDRESS_MAP_END
|
||||
|
||||
static INPUT_PORTS_START( chihiro )
|
||||
@ -2967,7 +2967,7 @@ void chihiro_state::machine_start()
|
||||
m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(chihiro_state::irq_callback),this));
|
||||
chihiro_devs.pic8259_1 = machine().device<pic8259_device>( "pic8259_1" );
|
||||
chihiro_devs.pic8259_2 = machine().device<pic8259_device>( "pic8259_2" );
|
||||
chihiro_devs.ide = machine().device<ide_controller_device>( "ide" );
|
||||
chihiro_devs.ide = machine().device<bus_master_ide_controller_device>( "ide" );
|
||||
if (machine().debug_flags & DEBUG_FLAG_ENABLED)
|
||||
debug_console_register_command(machine(),"chihiro",CMDFLAG_NONE,0,1,4,chihiro_debug_commands);
|
||||
}
|
||||
@ -2997,9 +2997,9 @@ static MACHINE_CONFIG_START( chihiro_base, chihiro_state )
|
||||
MCFG_PIC8259_ADD( "pic8259_1", WRITELINE(chihiro_state, chihiro_pic8259_1_set_int_line), VCC, READ8(chihiro_state,get_slave_ack) )
|
||||
MCFG_PIC8259_ADD( "pic8259_2", DEVWRITELINE("pic8259_1", pic8259_device, ir2_w), GND, NULL )
|
||||
MCFG_PIT8254_ADD( "pit8254", chihiro_pit8254_config )
|
||||
MCFG_IDE_CONTROLLER_ADD( "ide", ide_baseboard, NULL, "bb", true)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD( "ide", ide_baseboard, NULL, "bb", true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
|
||||
MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
|
||||
|
||||
/* video hardware */
|
||||
MCFG_SCREEN_ADD("screen", RASTER)
|
||||
|
||||
@ -518,7 +518,7 @@ public:
|
||||
void update_widget_irq();
|
||||
void init_common(int ioasic, int serialnum, int yearoffs, int config);
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<ide_controller_device> m_ide;
|
||||
required_device<bus_master_ide_controller_device> m_ide;
|
||||
};
|
||||
|
||||
/*************************************
|
||||
@ -1785,10 +1785,10 @@ static ADDRESS_MAP_START( seattle_map, AS_PROGRAM, 32, seattle_state )
|
||||
ADDRESS_MAP_UNMAP_HIGH
|
||||
AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase") // wg3dh only has 4MB; sfrush, blitz99 8MB
|
||||
AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD_LEGACY("voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w)
|
||||
AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
|
||||
AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", ide_controller_device, write_cs1_pc, 0xffffffff)
|
||||
AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
|
||||
AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", bus_master_ide_controller_device, write_cs1_pc, 0xffffffff)
|
||||
AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP // IDE-related, but annoying
|
||||
AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
|
||||
AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
|
||||
AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(galileo_r, galileo_w)
|
||||
AM_RANGE(0x13000000, 0x13000003) AM_WRITE(asic_fifo_w)
|
||||
AM_RANGE(0x16000000, 0x1600003f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)
|
||||
@ -2535,9 +2535,9 @@ static MACHINE_CONFIG_START( seattle_common, seattle_state )
|
||||
|
||||
MCFG_NVRAM_ADD_1FILL("nvram")
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(seattle_state, ide_interrupt))
|
||||
MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
|
||||
|
||||
MCFG_3DFX_VOODOO_1_ADD("voodoo", STD_VOODOO_1_CLOCK, voodoo_intf)
|
||||
|
||||
|
||||
@ -1458,7 +1458,7 @@ static WRITE32_HANDLER( asic_fifo_w )
|
||||
|
||||
static READ32_DEVICE_HANDLER( ide_main_r )
|
||||
{
|
||||
ide_controller_device *ide = (ide_controller_device *) device;
|
||||
bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
|
||||
|
||||
UINT32 data = 0;
|
||||
if (ACCESSING_BITS_0_15)
|
||||
@ -1472,7 +1472,7 @@ static READ32_DEVICE_HANDLER( ide_main_r )
|
||||
|
||||
static WRITE32_DEVICE_HANDLER( ide_main_w )
|
||||
{
|
||||
ide_controller_device *ide = (ide_controller_device *) device;
|
||||
bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
|
||||
|
||||
if (ACCESSING_BITS_0_15)
|
||||
ide->write_cs0_pc(space, offset * 2, data, mem_mask);
|
||||
@ -1483,7 +1483,7 @@ static WRITE32_DEVICE_HANDLER( ide_main_w )
|
||||
|
||||
static READ32_DEVICE_HANDLER( ide_alt_r )
|
||||
{
|
||||
ide_controller_device *ide = (ide_controller_device *) device;
|
||||
bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
|
||||
|
||||
UINT32 data = 0;
|
||||
if (ACCESSING_BITS_0_15)
|
||||
@ -1497,7 +1497,7 @@ static READ32_DEVICE_HANDLER( ide_alt_r )
|
||||
|
||||
static WRITE32_DEVICE_HANDLER( ide_alt_w )
|
||||
{
|
||||
ide_controller_device *ide = (ide_controller_device *) device;
|
||||
bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
|
||||
|
||||
if (ACCESSING_BITS_0_15)
|
||||
ide->write_cs1_pc(space, 6/2 + offset * 2, data, mem_mask);
|
||||
@ -1508,14 +1508,14 @@ static WRITE32_DEVICE_HANDLER( ide_alt_w )
|
||||
|
||||
static READ32_DEVICE_HANDLER( ide_bus_master32_r )
|
||||
{
|
||||
ide_controller_device *ide = (ide_controller_device *) device;
|
||||
bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
|
||||
return ide->ide_bus_master32_r(space, offset, mem_mask);
|
||||
}
|
||||
|
||||
|
||||
static WRITE32_DEVICE_HANDLER( ide_bus_master32_w )
|
||||
{
|
||||
ide_controller_device *ide = (ide_controller_device *) device;
|
||||
bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
|
||||
ide->ide_bus_master32_w(space, offset, data, mem_mask);
|
||||
}
|
||||
|
||||
@ -2279,9 +2279,9 @@ static MACHINE_CONFIG_START( vegascore, vegas_state )
|
||||
|
||||
MCFG_M48T37_ADD("timekeeper")
|
||||
|
||||
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
|
||||
MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(vegas_state, ide_interrupt))
|
||||
MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM)
|
||||
MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
|
||||
|
||||
MCFG_SMC91C94_ADD("ethernet", ethernet_intf)
|
||||
|
||||
|
||||
Loading…
Reference in New Issue
Block a user