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created a new device for the bus master ide controller, but the implementation is still in the ide controller. (nw)

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This commit is contained in:
smf- 2013-06-09 15:44:43 +00:00
parent cf58f7f28b
commit b0a5f6fa03
5 changed files with 174 additions and 171 deletions
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240
src/emu/machine/idectrl.c
View File

@ -188,44 +188,6 @@ static TIMER_CALLBACK( reset_callback )
/*************************************
*
* Convert offset/mem_mask to offset
* and size
*
*************************************/
INLINE int convert_to_offset_and_size32(offs_t *offset, UINT32 mem_mask)
{
int size = 4;
/* determine which real offset */
if (!ACCESSING_BITS_0_7)
{
(*offset)++, size = 3;
if (!ACCESSING_BITS_8_15)
{
(*offset)++, size = 2;
if (!ACCESSING_BITS_16_23)
(*offset)++, size = 1;
}
}
/* determine the real size */
if (ACCESSING_BITS_24_31)
return size;
size--;
if (ACCESSING_BITS_16_23)
return size;
size--;
if (ACCESSING_BITS_8_15)
return size;
size--;
return size;
}
/************************************* /*************************************
* *
* Advance to the next sector * Advance to the next sector
@ -1387,21 +1349,20 @@ WRITE16_MEMBER( ide_controller_device::write_cs1 )
* *
*************************************/ *************************************/
UINT32 ide_controller_device::ide_bus_master_read(offs_t offset, int size) READ32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_r )
{ {
LOG(("%s:ide_bus_master_read(%d, %d)\n", machine().describe_context(), offset, size)); LOG(("%s:ide_bus_master32_r(%d, %08x)\n", machine().describe_context(), offset, mem_mask));
/* command register */ switch( offset )
if (offset == 0) {
case 0:
/* command register/status register */
return bus_master_command | (bus_master_status << 16); return bus_master_command | (bus_master_status << 16);
/* status register */ case 1:
if (offset == 2) /* descriptor table register */
return bus_master_status;
/* descriptor table register */
if (offset == 4)
return bus_master_descriptor; return bus_master_descriptor;
}
return 0xffffffff; return 0xffffffff;
} }
@ -1414,82 +1375,67 @@ UINT32 ide_controller_device::ide_bus_master_read(offs_t offset, int size)
* *
*************************************/ *************************************/
void ide_controller_device::ide_bus_master_write(offs_t offset, int size, UINT32 data) WRITE32_MEMBER( bus_master_ide_controller_device::ide_bus_master32_w )
{ {
LOG(("%s:ide_bus_master_write(%d, %d, %08X)\n", machine().describe_context(), offset, size, data)); LOG(("%s:ide_bus_master32_w(%d, %08x, %08X)\n", machine().describe_context(), offset, mem_mask, data));
/* command register */ switch( offset )
if (offset == 0)
{ {
UINT8 old = bus_master_command; case 0:
UINT8 val = data & 0xff; if( ACCESSING_BITS_0_7 )
/* save the read/write bit and the start/stop bit */
bus_master_command = (old & 0xf6) | (val & 0x09);
bus_master_status = (bus_master_status & ~IDE_BUSMASTER_STATUS_ACTIVE) | (val & 0x01);
/* handle starting a transfer */
if (!(old & 1) && (val & 1))
{ {
/* reset all the DMA data */ /* command register */
dma_bytes_left = 0; UINT8 old = bus_master_command;
dma_last_buffer = 0; UINT8 val = data & 0xff;
dma_descriptor = bus_master_descriptor;
/* if we're going live, start the pending read/write */ /* save the read/write bit and the start/stop bit */
if (dma_active) bus_master_command = (old & 0xf6) | (val & 0x09);
bus_master_status = (bus_master_status & ~IDE_BUSMASTER_STATUS_ACTIVE) | (val & 0x01);
/* handle starting a transfer */
if (!(old & 1) && (val & 1))
{ {
if (bus_master_command & 8) /* reset all the DMA data */
read_next_sector(); dma_bytes_left = 0;
else dma_last_buffer = 0;
dma_descriptor = bus_master_descriptor;
/* if we're going live, start the pending read/write */
if (dma_active)
{ {
read_buffer_from_dma(); if (bus_master_command & 8)
continue_write(); read_next_sector();
else
{
read_buffer_from_dma();
continue_write();
}
} }
} }
} }
}
/* status register */ if( ACCESSING_BITS_16_23 )
if (offset <= 2 && offset + size > 2) {
{ /* status register */
UINT8 old = bus_master_status; UINT8 old = bus_master_status;
UINT8 val = data >> (8 * (2 - offset)); UINT8 val = (data >> 16) & 0xff;
/* save the DMA capable bits */ /* save the DMA capable bits */
bus_master_status = (old & 0x9f) | (val & 0x60); bus_master_status = (old & 0x9f) | (val & 0x60);
/* clear interrupt and error bits */ /* clear interrupt and error bits */
if (val & IDE_BUSMASTER_STATUS_IRQ) if (val & IDE_BUSMASTER_STATUS_IRQ)
bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ; bus_master_status &= ~IDE_BUSMASTER_STATUS_IRQ;
if (val & IDE_BUSMASTER_STATUS_ERROR) if (val & IDE_BUSMASTER_STATUS_ERROR)
bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR; bus_master_status &= ~IDE_BUSMASTER_STATUS_ERROR;
} }
break;
/* descriptor table register */ case 1:
if (offset == 4) /* descriptor table register */
bus_master_descriptor = data & 0xfffffffc; bus_master_descriptor = data & 0xfffffffc;
} break;
}
READ32_MEMBER( ide_controller_device::ide_bus_master32_r )
{
int size;
offset *= 4;
size = convert_to_offset_and_size32(&offset, mem_mask);
return ide_bus_master_read(offset, size) << ((offset & 3) * 8);
}
WRITE32_MEMBER( ide_controller_device::ide_bus_master32_w )
{
int size;
offset *= 4;
size = convert_to_offset_and_size32(&offset, mem_mask);
ide_bus_master_write(offset, size, data >> ((offset & 3) * 8));
} }
@ -1497,11 +1443,21 @@ SLOT_INTERFACE_START(ide_devices)
SLOT_INTERFACE("hdd", IDE_HARDDISK) SLOT_INTERFACE("hdd", IDE_HARDDISK)
SLOT_INTERFACE_END SLOT_INTERFACE_END
const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>; ide_controller_device::ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock) :
device_t(mconfig, type, name, tag, owner, clock),
ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
device_t(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
status(0), status(0),
bmcpu(NULL),
bmspace(0),
dma_space(NULL),
dma_active(0),
dma_address_xor(0),
dma_last_buffer(0),
dma_address(0),
dma_descriptor(0),
dma_bytes_left(0),
bus_master_command(0),
bus_master_status(0),
bus_master_descriptor(0),
adapter_control(0), adapter_control(0),
error(0), error(0),
command(0), command(0),
@ -1512,16 +1468,6 @@ ide_controller_device::ide_controller_device(const machine_config &mconfig, cons
block_count(0), block_count(0),
sectors_until_int(0), sectors_until_int(0),
verify_only(0), verify_only(0),
dma_active(0),
dma_space(NULL),
dma_address_xor(0),
dma_last_buffer(0),
dma_address(0),
dma_descriptor(0),
dma_bytes_left(0),
bus_master_command(0),
bus_master_status(0),
bus_master_descriptor(0),
config_unknown(0), config_unknown(0),
config_register_num(0), config_register_num(0),
master_password_enable(0), master_password_enable(0),
@ -1530,9 +1476,53 @@ ide_controller_device::ide_controller_device(const machine_config &mconfig, cons
user_password(NULL), user_password(NULL),
gnetreadlock(0), gnetreadlock(0),
cur_drive(0), cur_drive(0),
m_irq_handler(*this), m_irq_handler(*this)
{
}
const device_type IDE_CONTROLLER = &device_creator<ide_controller_device>;
ide_controller_device::ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
device_t(mconfig, IDE_CONTROLLER, "IDE Controller", tag, owner, clock),
bmcpu(NULL), bmcpu(NULL),
bmspace(0) bmspace(0),
dma_space(NULL),
dma_active(0),
dma_address_xor(0),
dma_last_buffer(0),
dma_address(0),
dma_descriptor(0),
dma_bytes_left(0),
bus_master_command(0),
bus_master_status(0),
bus_master_descriptor(0),
adapter_control(0),
error(0),
command(0),
interrupt_pending(0),
precomp_offset(0),
buffer_offset(0),
sector_count(0),
block_count(0),
sectors_until_int(0),
verify_only(0),
config_unknown(0),
config_register_num(0),
master_password_enable(0),
user_password_enable(0),
master_password(NULL),
user_password(NULL),
gnetreadlock(0),
cur_drive(0),
m_irq_handler(*this)
{
}
const device_type BUS_MASTER_IDE_CONTROLLER = &device_creator<bus_master_ide_controller_device>;
bus_master_ide_controller_device::bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) :
ide_controller_device(mconfig, BUS_MASTER_IDE_CONTROLLER, "Bus Master IDE Controller", tag, owner, clock)
{ {
} }

65
src/emu/machine/idectrl.h
View File

@ -49,9 +49,6 @@ extern const device_type IDE_SLOT;
#define MCFG_IDE_CONTROLLER_IRQ_HANDLER(_devcb) \ #define MCFG_IDE_CONTROLLER_IRQ_HANDLER(_devcb) \
devcb = &ide_controller_device::set_irq_handler(*device, DEVCB2_##_devcb); devcb = &ide_controller_device::set_irq_handler(*device, DEVCB2_##_devcb);
#define MCFG_IDE_CONTROLLER_BUS_MASTER(bmcpu, bmspace) \
ide_controller_device::set_bus_master(*device, bmcpu, bmspace);
SLOT_INTERFACE_EXTERN(ide_devices); SLOT_INTERFACE_EXTERN(ide_devices);
SLOT_INTERFACE_EXTERN(ide_devices); SLOT_INTERFACE_EXTERN(ide_devices);
@ -80,10 +77,10 @@ class ide_controller_device : public device_t
{ {
public: public:
ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
ide_controller_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock);
// static configuration helpers // static configuration helpers
template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<ide_controller_device &>(device).m_irq_handler.set_callback(object); } template<class _Object> static devcb2_base &set_irq_handler(device_t &device, _Object object) { return downcast<ide_controller_device &>(device).m_irq_handler.set_callback(object); }
static void set_bus_master(device_t &device, const char *bmcpu, UINT32 bmspace) {ide_controller_device &ide = downcast<ide_controller_device &>(device); ide.bmcpu = bmcpu; ide.bmspace = bmspace; }
UINT8 *ide_get_features(int drive); UINT8 *ide_get_features(int drive);
void ide_set_gnet_readlock(const UINT8 onoff); void ide_set_gnet_readlock(const UINT8 onoff);
@ -102,11 +99,6 @@ public:
DECLARE_WRITE16_MEMBER(write_cs0_pc); DECLARE_WRITE16_MEMBER(write_cs0_pc);
DECLARE_WRITE16_MEMBER(write_cs1_pc); DECLARE_WRITE16_MEMBER(write_cs1_pc);
DECLARE_READ32_MEMBER( ide_bus_master32_r );
DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
UINT32 ide_bus_master_read(offs_t offset, int size);
void ide_bus_master_write(offs_t offset, int size, UINT32 data);
void signal_interrupt(); void signal_interrupt();
void clear_interrupt(); void clear_interrupt();
void read_sector_done(); void read_sector_done();
@ -119,6 +111,23 @@ protected:
virtual void device_start(); virtual void device_start();
virtual void device_reset(); virtual void device_reset();
const char *bmcpu;
UINT32 bmspace;
address_space * dma_space;
UINT8 dma_active;
UINT8 dma_address_xor;
UINT8 dma_last_buffer;
offs_t dma_address;
offs_t dma_descriptor;
UINT32 dma_bytes_left;
UINT8 bus_master_command;
UINT8 bus_master_status;
UINT32 bus_master_descriptor;
void read_next_sector();
void read_buffer_from_dma();
void continue_write();
private: private:
void signal_delayed_interrupt(attotime time, int buffer_ready); void signal_delayed_interrupt(attotime time, int buffer_ready);
void next_sector(); void next_sector();
@ -126,10 +135,7 @@ private:
void continue_read(); void continue_read();
void write_buffer_to_dma(); void write_buffer_to_dma();
void read_first_sector(); void read_first_sector();
void read_next_sector();
void read_buffer_from_dma();
void handle_command(UINT8 _command); void handle_command(UINT8 _command);
void continue_write();
UINT8 adapter_control; UINT8 adapter_control;
UINT8 error; UINT8 error;
@ -145,18 +151,6 @@ private:
UINT16 sectors_until_int; UINT16 sectors_until_int;
UINT8 verify_only; UINT8 verify_only;
UINT8 dma_active;
address_space *dma_space;
UINT8 dma_address_xor;
UINT8 dma_last_buffer;
offs_t dma_address;
offs_t dma_descriptor;
UINT32 dma_bytes_left;
UINT8 bus_master_command;
UINT8 bus_master_status;
UINT32 bus_master_descriptor;
UINT8 config_unknown; UINT8 config_unknown;
UINT8 config_register[IDE_CONFIG_REGISTERS]; UINT8 config_register[IDE_CONFIG_REGISTERS];
UINT8 config_register_num; UINT8 config_register_num;
@ -175,10 +169,29 @@ private:
ide_slot_device *slot[2]; ide_slot_device *slot[2];
devcb2_write_line m_irq_handler; devcb2_write_line m_irq_handler;
const char *bmcpu;
UINT32 bmspace;
}; };
extern const device_type IDE_CONTROLLER; extern const device_type IDE_CONTROLLER;
#define MCFG_BUS_MASTER_IDE_CONTROLLER_ADD(_tag, _slotintf, _master, _slave, _fixed) \
MCFG_IDE_SLOT_ADD("drive_0", _slotintf, _master, _fixed) \
MCFG_IDE_SLOT_ADD("drive_1", _slotintf, _slave, _fixed) \
MCFG_DEVICE_ADD(_tag, BUS_MASTER_IDE_CONTROLLER, 0)
#define MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE(bmcpu, bmspace) \
bus_master_ide_controller_device::set_bus_master_space(*device, bmcpu, bmspace);
class bus_master_ide_controller_device : public ide_controller_device
{
public:
bus_master_ide_controller_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
static void set_bus_master_space(device_t &device, const char *bmcpu, UINT32 bmspace) {bus_master_ide_controller_device &ide = downcast<bus_master_ide_controller_device &>(device); ide.bmcpu = bmcpu; ide.bmspace = bmspace; }
DECLARE_READ32_MEMBER( ide_bus_master32_r );
DECLARE_WRITE32_MEMBER( ide_bus_master32_w );
};
extern const device_type BUS_MASTER_IDE_CONTROLLER;
#endif /* __IDECTRL_H__ */ #endif /* __IDECTRL_H__ */

12
src/mame/drivers/chihiro.c
View File

@ -410,7 +410,7 @@ public:
struct chihiro_devices { struct chihiro_devices {
pic8259_device *pic8259_1; pic8259_device *pic8259_1;
pic8259_device *pic8259_2; pic8259_device *pic8259_2;
ide_controller_device *ide; bus_master_ide_controller_device *ide;
} chihiro_devs; } chihiro_devs;
nv2a_renderer *nvidia_nv2a; nv2a_renderer *nvidia_nv2a;
@ -2945,11 +2945,11 @@ static ADDRESS_MAP_START(xbox_map_io, AS_IO, 32, chihiro_state )
AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff) AM_RANGE(0x0020, 0x0023) AM_DEVREADWRITE8("pic8259_1", pic8259_device, read, write, 0xffffffff)
AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff) AM_RANGE(0x0040, 0x0043) AM_DEVREADWRITE8("pit8254", pit8254_device, read, write, 0xffffffff)
AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff) AM_RANGE(0x00a0, 0x00a3) AM_DEVREADWRITE8("pic8259_2", pic8259_device, read, write, 0xffffffff)
AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x01f0, 0x01f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write) AM_RANGE(0x0cf8, 0x0cff) AM_DEVREADWRITE("pcibus", pci_bus_legacy_device, read, write)
AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w) AM_RANGE(0x8000, 0x80ff) AM_READWRITE(dummy_r, dummy_w)
AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w) AM_RANGE(0xc000, 0xc0ff) AM_READWRITE(smbus_r, smbus_w)
AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", ide_controller_device, ide_bus_master32_r, ide_bus_master32_w) AM_RANGE(0xff60, 0xff67) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
ADDRESS_MAP_END ADDRESS_MAP_END
static INPUT_PORTS_START( chihiro ) static INPUT_PORTS_START( chihiro )
@ -2967,7 +2967,7 @@ void chihiro_state::machine_start()
m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(chihiro_state::irq_callback),this)); m_maincpu->set_irq_acknowledge_callback(device_irq_acknowledge_delegate(FUNC(chihiro_state::irq_callback),this));
chihiro_devs.pic8259_1 = machine().device<pic8259_device>( "pic8259_1" ); chihiro_devs.pic8259_1 = machine().device<pic8259_device>( "pic8259_1" );
chihiro_devs.pic8259_2 = machine().device<pic8259_device>( "pic8259_2" ); chihiro_devs.pic8259_2 = machine().device<pic8259_device>( "pic8259_2" );
chihiro_devs.ide = machine().device<ide_controller_device>( "ide" ); chihiro_devs.ide = machine().device<bus_master_ide_controller_device>( "ide" );
if (machine().debug_flags & DEBUG_FLAG_ENABLED) if (machine().debug_flags & DEBUG_FLAG_ENABLED)
debug_console_register_command(machine(),"chihiro",CMDFLAG_NONE,0,1,4,chihiro_debug_commands); debug_console_register_command(machine(),"chihiro",CMDFLAG_NONE,0,1,4,chihiro_debug_commands);
} }
@ -2997,9 +2997,9 @@ static MACHINE_CONFIG_START( chihiro_base, chihiro_state )
MCFG_PIC8259_ADD( "pic8259_1", WRITELINE(chihiro_state, chihiro_pic8259_1_set_int_line), VCC, READ8(chihiro_state,get_slave_ack) ) MCFG_PIC8259_ADD( "pic8259_1", WRITELINE(chihiro_state, chihiro_pic8259_1_set_int_line), VCC, READ8(chihiro_state,get_slave_ack) )
MCFG_PIC8259_ADD( "pic8259_2", DEVWRITELINE("pic8259_1", pic8259_device, ir2_w), GND, NULL ) MCFG_PIC8259_ADD( "pic8259_2", DEVWRITELINE("pic8259_1", pic8259_device, ir2_w), GND, NULL )
MCFG_PIT8254_ADD( "pit8254", chihiro_pit8254_config ) MCFG_PIT8254_ADD( "pit8254", chihiro_pit8254_config )
MCFG_IDE_CONTROLLER_ADD( "ide", ide_baseboard, NULL, "bb", true) MCFG_BUS_MASTER_IDE_CONTROLLER_ADD( "ide", ide_baseboard, NULL, "bb", true)
MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w)) MCFG_IDE_CONTROLLER_IRQ_HANDLER(DEVWRITELINE("pic8259_2", pic8259_device, ir6_w))
MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM) MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
/* video hardware */ /* video hardware */
MCFG_SCREEN_ADD("screen", RASTER) MCFG_SCREEN_ADD("screen", RASTER)

12
src/mame/drivers/seattle.c
View File

@ -518,7 +518,7 @@ public:
void update_widget_irq(); void update_widget_irq();
void init_common(int ioasic, int serialnum, int yearoffs, int config); void init_common(int ioasic, int serialnum, int yearoffs, int config);
required_device<cpu_device> m_maincpu; required_device<cpu_device> m_maincpu;
required_device<ide_controller_device> m_ide; required_device<bus_master_ide_controller_device> m_ide;
}; };
/************************************* /*************************************
@ -1785,10 +1785,10 @@ static ADDRESS_MAP_START( seattle_map, AS_PROGRAM, 32, seattle_state )
ADDRESS_MAP_UNMAP_HIGH ADDRESS_MAP_UNMAP_HIGH
AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase") // wg3dh only has 4MB; sfrush, blitz99 8MB AM_RANGE(0x00000000, 0x007fffff) AM_RAM AM_SHARE("rambase") // wg3dh only has 4MB; sfrush, blitz99 8MB
AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD_LEGACY("voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w) AM_RANGE(0x08000000, 0x08ffffff) AM_DEVREAD_LEGACY("voodoo", voodoo_r) AM_WRITE(seattle_voodoo_w)
AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff) AM_RANGE(0x0a0001f0, 0x0a0001f7) AM_DEVREADWRITE16("ide", bus_master_ide_controller_device, read_cs0_pc, write_cs0_pc, 0xffffffff)
AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", ide_controller_device, write_cs1_pc, 0xffffffff) AM_RANGE(0x0a0003f0, 0x0a0003f7) AM_READ16(seattle_ide_r, 0xffffffff) AM_DEVWRITE16("ide", bus_master_ide_controller_device, write_cs1_pc, 0xffffffff)
AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP // IDE-related, but annoying AM_RANGE(0x0a00040c, 0x0a00040f) AM_NOP // IDE-related, but annoying
AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", ide_controller_device, ide_bus_master32_r, ide_bus_master32_w) AM_RANGE(0x0a000f00, 0x0a000f07) AM_DEVREADWRITE("ide", bus_master_ide_controller_device, ide_bus_master32_r, ide_bus_master32_w)
AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(galileo_r, galileo_w) AM_RANGE(0x0c000000, 0x0c000fff) AM_READWRITE(galileo_r, galileo_w)
AM_RANGE(0x13000000, 0x13000003) AM_WRITE(asic_fifo_w) AM_RANGE(0x13000000, 0x13000003) AM_WRITE(asic_fifo_w)
AM_RANGE(0x16000000, 0x1600003f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w) AM_RANGE(0x16000000, 0x1600003f) AM_READWRITE_LEGACY(midway_ioasic_r, midway_ioasic_w)
@ -2535,9 +2535,9 @@ static MACHINE_CONFIG_START( seattle_common, seattle_state )
MCFG_NVRAM_ADD_1FILL("nvram") MCFG_NVRAM_ADD_1FILL("nvram")
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true) MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(seattle_state, ide_interrupt)) MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(seattle_state, ide_interrupt))
MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM) MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
MCFG_3DFX_VOODOO_1_ADD("voodoo", STD_VOODOO_1_CLOCK, voodoo_intf) MCFG_3DFX_VOODOO_1_ADD("voodoo", STD_VOODOO_1_CLOCK, voodoo_intf)

16
src/mame/drivers/vegas.c
View File

@ -1458,7 +1458,7 @@ static WRITE32_HANDLER( asic_fifo_w )
static READ32_DEVICE_HANDLER( ide_main_r ) static READ32_DEVICE_HANDLER( ide_main_r )
{ {
ide_controller_device *ide = (ide_controller_device *) device; bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
UINT32 data = 0; UINT32 data = 0;
if (ACCESSING_BITS_0_15) if (ACCESSING_BITS_0_15)
@ -1472,7 +1472,7 @@ static READ32_DEVICE_HANDLER( ide_main_r )
static WRITE32_DEVICE_HANDLER( ide_main_w ) static WRITE32_DEVICE_HANDLER( ide_main_w )
{ {
ide_controller_device *ide = (ide_controller_device *) device; bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
if (ACCESSING_BITS_0_15) if (ACCESSING_BITS_0_15)
ide->write_cs0_pc(space, offset * 2, data, mem_mask); ide->write_cs0_pc(space, offset * 2, data, mem_mask);
@ -1483,7 +1483,7 @@ static WRITE32_DEVICE_HANDLER( ide_main_w )
static READ32_DEVICE_HANDLER( ide_alt_r ) static READ32_DEVICE_HANDLER( ide_alt_r )
{ {
ide_controller_device *ide = (ide_controller_device *) device; bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
UINT32 data = 0; UINT32 data = 0;
if (ACCESSING_BITS_0_15) if (ACCESSING_BITS_0_15)
@ -1497,7 +1497,7 @@ static READ32_DEVICE_HANDLER( ide_alt_r )
static WRITE32_DEVICE_HANDLER( ide_alt_w ) static WRITE32_DEVICE_HANDLER( ide_alt_w )
{ {
ide_controller_device *ide = (ide_controller_device *) device; bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
if (ACCESSING_BITS_0_15) if (ACCESSING_BITS_0_15)
ide->write_cs1_pc(space, 6/2 + offset * 2, data, mem_mask); ide->write_cs1_pc(space, 6/2 + offset * 2, data, mem_mask);
@ -1508,14 +1508,14 @@ static WRITE32_DEVICE_HANDLER( ide_alt_w )
static READ32_DEVICE_HANDLER( ide_bus_master32_r ) static READ32_DEVICE_HANDLER( ide_bus_master32_r )
{ {
ide_controller_device *ide = (ide_controller_device *) device; bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
return ide->ide_bus_master32_r(space, offset, mem_mask); return ide->ide_bus_master32_r(space, offset, mem_mask);
} }
static WRITE32_DEVICE_HANDLER( ide_bus_master32_w ) static WRITE32_DEVICE_HANDLER( ide_bus_master32_w )
{ {
ide_controller_device *ide = (ide_controller_device *) device; bus_master_ide_controller_device *ide = (bus_master_ide_controller_device *) device;
ide->ide_bus_master32_w(space, offset, data, mem_mask); ide->ide_bus_master32_w(space, offset, data, mem_mask);
} }
@ -2279,9 +2279,9 @@ static MACHINE_CONFIG_START( vegascore, vegas_state )
MCFG_M48T37_ADD("timekeeper") MCFG_M48T37_ADD("timekeeper")
MCFG_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true) MCFG_BUS_MASTER_IDE_CONTROLLER_ADD("ide", ide_devices, "hdd", NULL, true)
MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(vegas_state, ide_interrupt)) MCFG_IDE_CONTROLLER_IRQ_HANDLER(WRITELINE(vegas_state, ide_interrupt))
MCFG_IDE_CONTROLLER_BUS_MASTER("maincpu", AS_PROGRAM) MCFG_BUS_MASTER_IDE_CONTROLLER_SPACE("maincpu", AS_PROGRAM)
MCFG_SMC91C94_ADD("ethernet", ethernet_intf) MCFG_SMC91C94_ADD("ethernet", ethernet_intf)