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remove safe_pc() (nw)

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This commit is contained in:
smf- 2017-12-14 14:41:18 +00:00
parent 8b9246599a
commit b0b96416eb
8 changed files with 119 additions and 147 deletions
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6
src/devices/machine/68307.cpp
View File

@ -283,8 +283,7 @@ void m68307_cpu_device::device_start()
READ16_MEMBER( m68307_cpu_device::m68307_internal_base_r )
{
int pc = space.device().safe_pc();
logerror("%08x m68307_internal_base_r %08x, (%04x)\n", pc, offset*2,mem_mask);
logerror("%08x m68307_internal_base_r %08x, (%04x)\n", m_ppc, offset*2,mem_mask);
switch (offset<<1)
{
@ -300,8 +299,7 @@ READ16_MEMBER( m68307_cpu_device::m68307_internal_base_r )
WRITE16_MEMBER( m68307_cpu_device::m68307_internal_base_w )
{
int pc = space.device().safe_pc();
logerror("%08x m68307_internal_base_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_base_w %08x, %04x (%04x)\n", m_ppc, offset*2,data,mem_mask);
int base;
//int mask = 0;

29
src/devices/machine/68307bus.cpp
View File

@ -19,25 +19,22 @@ READ8_MEMBER( m68307_cpu_device::m68307_internal_mbus_r )
m68307_mbus &mbus = *m_m68307MBUS;
uint8_t retval;
int pc = space.device().safe_pc();
switch (offset)
{
case m68307BUS_MADR:
logerror("%08x m68307_internal_mbus_r %08x (MADR - M-Bus Address Register)\n", pc, offset);
logerror("%08x m68307_internal_mbus_r %08x (MADR - M-Bus Address Register)\n", m_ppc, offset);
return space.machine().rand();
case m68307BUS_MFDR:
logerror("%08x m68307_internal_mbus_r %08x (MFDR - M-Bus Frequency Divider Register)\n", pc, offset);
logerror("%08x m68307_internal_mbus_r %08x (MFDR - M-Bus Frequency Divider Register)\n", m_ppc, offset);
return space.machine().rand();
case m68307BUS_MBCR:
logerror("%08x m68307_internal_mbus_r %08x (MFCR - M-Bus Control Register)\n", pc, offset);
logerror("%08x m68307_internal_mbus_r %08x (MFCR - M-Bus Control Register)\n", m_ppc, offset);
return mbus.m_MFCR;//space.machine().rand();
case m68307BUS_MBSR:
logerror("%08x m68307_internal_mbus_r %08x (MBSR - M-Bus Status Register)\n", pc, offset);
logerror("%08x m68307_internal_mbus_r %08x (MBSR - M-Bus Status Register)\n", m_ppc, offset);
retval = 0;
if (mbus.m_busy) retval |= 0x20;
if (mbus.m_intpend) retval |= 0x02;
@ -45,12 +42,12 @@ READ8_MEMBER( m68307_cpu_device::m68307_internal_mbus_r )
return retval;
case m68307BUS_MBDR:
logerror("%08x m68307_internal_mbus_r %08x (MBDR - M-Bus Data I/O Register)\n", pc, offset);
logerror("%08x m68307_internal_mbus_r %08x (MBDR - M-Bus Data I/O Register)\n", m_ppc, offset);
mbus.m_intpend = true;
return 0xff;//space.machine().rand();
default:
logerror("%08x m68307_internal_mbus_r %08x (UNKNOWN / ILLEGAL)\n", pc, offset);
logerror("%08x m68307_internal_mbus_r %08x (UNKNOWN / ILLEGAL)\n", m_ppc, offset);
return 0x00;
}
@ -62,20 +59,18 @@ WRITE8_MEMBER( m68307_cpu_device::m68307_internal_mbus_w )
assert(m_m68307MBUS);
m68307_mbus &mbus = *m_m68307MBUS;
int pc = space.device().safe_pc();
switch (offset)
{
case m68307BUS_MADR:
logerror("%08x m68307_internal_mbus_w %08x, %02x (MADR - M-Bus Address Register)\n", pc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (MADR - M-Bus Address Register)\n", m_ppc, offset,data);
break;
case m68307BUS_MFDR:
logerror("%08x m68307_internal_mbus_w %08x, %02x (MFDR - M-Bus Frequency Divider Register)\n", pc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (MFDR - M-Bus Frequency Divider Register)\n", m_ppc, offset,data);
break;
case m68307BUS_MBCR:
logerror("%08x m68307_internal_mbus_w %08x, %02x (MFCR - M-Bus Control Register)\n", pc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (MFCR - M-Bus Control Register)\n", m_ppc, offset,data);
mbus.m_MFCR = data;
if (data & 0x80)
@ -88,18 +83,18 @@ WRITE8_MEMBER( m68307_cpu_device::m68307_internal_mbus_w )
break;
case m68307BUS_MBSR:
logerror("%08x m68307_internal_mbus_w %08x, %02x (MBSR - M-Bus Status Register)\n", pc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (MBSR - M-Bus Status Register)\n", m_ppc, offset,data);
break;
case m68307BUS_MBDR:
logerror("%08x m68307_internal_mbus_w %08x, %02x (MBDR - M-Bus Data I/O Register)\n", pc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (MBDR - M-Bus Data I/O Register)\n", m_ppc, offset,data);
mbus.m_intpend = true;
break;
default:
logerror("%08x m68307_internal_mbus_w %08x, %02x (UNKNOWN / ILLEGAL)\n", pc, offset,data);
logerror("%08x m68307_internal_mbus_w %08x, %02x (UNKNOWN / ILLEGAL)\n", m_ppc, offset,data);
break;
}
}

38
src/devices/machine/68307sim.cpp
View File

@ -35,8 +35,6 @@ READ16_MEMBER( m68307_cpu_device::m68307_internal_sim_r )
assert(m_m68307SIM);
m68307_sim &sim = *m_m68307SIM;
int pc = space.device().safe_pc();
switch (offset<<1)
{
case m68307SIM_PADAT: return sim.read_padat(this, space, mem_mask);
@ -54,7 +52,7 @@ READ16_MEMBER( m68307_cpu_device::m68307_internal_sim_r )
case m68307SIM_OR3: return sim.m_or[3];
default:
logerror("%08x m68307_internal_sim_r %08x, (%04x)\n", pc, offset*2, mem_mask);
logerror("%08x m68307_internal_sim_r %08x, (%04x)\n", m_ppc, offset*2, mem_mask);
return 0xff;
}
@ -67,17 +65,15 @@ WRITE16_MEMBER( m68307_cpu_device::m68307_internal_sim_w )
assert(m_m68307SIM);
m68307_sim &sim = *m_m68307SIM;
int pc = space.device().safe_pc();
switch (offset<<1)
{
case m68307SIM_PACNT:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Control Register - PACNT)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Control Register - PACNT)\n", m_ppc, offset*2,data,mem_mask);
sim.write_pacnt(data,mem_mask);
break;
case m68307SIM_PADDR:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Direction Register - PADDR)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port A (8-bit) Direction Register - PADDR)\n", m_ppc, offset*2,data,mem_mask);
sim.write_paddr(data,mem_mask);
break;
@ -86,12 +82,12 @@ WRITE16_MEMBER( m68307_cpu_device::m68307_internal_sim_w )
break;
case m68307SIM_PBCNT:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Control Register - PBCNT)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Control Register - PBCNT)\n", m_ppc, offset*2,data,mem_mask);
sim.write_pbcnt(data,mem_mask);
break;
case m68307SIM_PBDDR:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Direction Register - PBDDR)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Port B (16-bit) Direction Register - PBDDR)\n", m_ppc, offset*2,data,mem_mask);
sim.write_pbddr(data,mem_mask);
break;
@ -101,22 +97,22 @@ WRITE16_MEMBER( m68307_cpu_device::m68307_internal_sim_w )
case m68307SIM_LICR1:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 1 - LICR1)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 1 - LICR1)\n", m_ppc, offset*2,data,mem_mask);
sim.write_licr1(this,data,mem_mask);
break;
case m68307SIM_LICR2:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 2 - LICR2)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Latched Interrupt Control Register 2 - LICR2)\n", m_ppc, offset*2,data,mem_mask);
sim.write_licr2(this,data,mem_mask);
break;
case m68307SIM_PICR:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Control Register - PICR)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Control Register - PICR)\n", m_ppc, offset*2,data,mem_mask);
sim.write_picr(this,data,mem_mask);
break;
case m68307SIM_PIVR:
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Vector Register - PIVR)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x) (Peripheral Interrupt Vector Register - PIVR)\n", m_ppc, offset*2,data,mem_mask);
sim.write_pivr(this,data,mem_mask);
break;
@ -148,7 +144,7 @@ WRITE16_MEMBER( m68307_cpu_device::m68307_internal_sim_w )
default :
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_sim_w %08x, %04x (%04x)\n", m_ppc, offset*2,data,mem_mask);
break;
}
}
@ -167,8 +163,6 @@ void m68307_cpu_device::m68307_sim::write_paddr(uint16_t data, uint16_t mem_mask
uint16_t m68307_cpu_device::m68307_sim::read_padat(m68307_cpu_device* m68k, address_space &space, uint16_t mem_mask)
{
int pc = space.device().safe_pc();
if (!m68k->m_porta_r.isnull())
{
// for general purpose bits, if configured as 'output' then anything output gets latched
@ -185,7 +179,7 @@ uint16_t m68307_cpu_device::m68307_sim::read_padat(m68307_cpu_device* m68k, addr
}
else
{
m68k->logerror("%08x m68307_internal_sim_r (%04x) (Port A (8-bit) Data Register - PADAT)\n", pc, mem_mask);
m68k->logerror("%08x m68307_internal_sim_r (%04x) (Port A (8-bit) Data Register - PADAT)\n", m68k->pcbase(), mem_mask);
}
return 0xffff;
}
@ -193,7 +187,6 @@ uint16_t m68307_cpu_device::m68307_sim::read_padat(m68307_cpu_device* m68k, addr
void m68307_cpu_device::m68307_sim::write_padat(m68307_cpu_device* m68k, address_space &space, uint16_t data, uint16_t mem_mask)
{
int pc = space.device().safe_pc();
COMBINE_DATA(&m_padat);
if (!m68k->m_porta_w.isnull())
@ -202,7 +195,7 @@ void m68307_cpu_device::m68307_sim::write_padat(m68307_cpu_device* m68k, address
}
else
{
m68k->logerror("%08x m68307_internal_sim_w %04x (%04x) (Port A (8-bit) Data Register - PADAT)\n", pc, data,mem_mask);
m68k->logerror("%08x m68307_internal_sim_w %04x (%04x) (Port A (8-bit) Data Register - PADAT)\n", m68k->pcbase(), data,mem_mask);
}
}
@ -218,8 +211,6 @@ void m68307_cpu_device::m68307_sim::write_pbddr(uint16_t data, uint16_t mem_mask
uint16_t m68307_cpu_device::m68307_sim::read_pbdat(m68307_cpu_device* m68k, address_space &space, uint16_t mem_mask)
{
int pc = space.device().safe_pc();
if (!m68k->m_portb_r.isnull())
{
// for general purpose bits, if configured as 'output' then anything output gets latched
@ -236,7 +227,7 @@ uint16_t m68307_cpu_device::m68307_sim::read_pbdat(m68307_cpu_device* m68k, addr
}
else
{
m68k->logerror("%08x m68307_internal_sim_r (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, mem_mask);
m68k->logerror("%08x m68307_internal_sim_r (%04x) (Port B (16-bit) Data Register - PBDAT)\n", m68k->pcbase(), mem_mask);
}
return 0xffff;
}
@ -244,7 +235,6 @@ uint16_t m68307_cpu_device::m68307_sim::read_pbdat(m68307_cpu_device* m68k, addr
void m68307_cpu_device::m68307_sim::write_pbdat(m68307_cpu_device* m68k, address_space &space, uint16_t data, uint16_t mem_mask)
{
int pc = space.device().safe_pc();
COMBINE_DATA(&m_pbdat);
if (!m68k->m_portb_w.isnull())
@ -253,7 +243,7 @@ void m68307_cpu_device::m68307_sim::write_pbdat(m68307_cpu_device* m68k, address
}
else
{
m68k->logerror("%08x m68307_internal_sim_w %04x (%04x) (Port B (16-bit) Data Register - PBDAT)\n", pc, data,mem_mask);
m68k->logerror("%08x m68307_internal_sim_w %04x (%04x) (Port B (16-bit) Data Register - PBDAT)\n", m68k->pcbase(), data,mem_mask);
}
}

26
src/devices/machine/68307tmu.cpp
View File

@ -20,17 +20,16 @@ READ16_MEMBER( m68307_cpu_device::m68307_internal_timer_r )
assert(m_m68307TIMER);
m68307_timer &timer = *m_m68307TIMER;
int pc = space.device().safe_pc();
int which = offset & 0x8;
switch (offset&0x7)
{
case m68307TIMER_TCN: /* 0x3 (0x126 / 0x136) */
//if (pc!=0x2182e) logerror("%08x m68307_internal_timer_r %08x (%04x) (TCN - Timer Counter for timer %d)\n", pc, offset*2,mem_mask, which);
//if (m_ppc!=0x2182e) logerror("%08x m68307_internal_timer_r %08x (%04x) (TCN - Timer Counter for timer %d)\n", m_ppc, offset*2,mem_mask, which);
return timer.read_tcn(mem_mask, which);
default:
logerror("%08x m68307_internal_timer_r %08x, (%04x)\n", pc, offset*2,mem_mask);
logerror("%08x m68307_internal_timer_r %08x, (%04x)\n", m_ppc, offset*2,mem_mask);
break;
}
@ -42,59 +41,58 @@ WRITE16_MEMBER( m68307_cpu_device::m68307_internal_timer_w )
assert(m_m68307TIMER);
m68307_timer &timer = *m_m68307TIMER;
int pc = space.device().safe_pc();
int which = offset & 0x8;
switch (offset&0x7)
{
case m68307TIMER_TMR: /* 0x0 (0x120 / 0x130) */
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TMR - Timer Mode Register for timer %d)\n", pc, offset*2,data,mem_mask, which);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TMR - Timer Mode Register for timer %d)\n", m_ppc, offset*2,data,mem_mask, which);
timer.write_tmr(data, mem_mask, which);
break;
case m68307TIMER_TRR: /* 0x1 (0x122 / 0x132) */
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TRR - Timer Reference Register for timer %d)\n", pc, offset*2,data,mem_mask, which);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TRR - Timer Reference Register for timer %d)\n", m_ppc, offset*2,data,mem_mask, which);
timer.write_trr(data, mem_mask, which);
break;
case m68307TIMER_TCR: /* 0x2 (0x124 / 0x134) */
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCR - Timer Capture Register for timer %d) (illegal, read-only)\n", pc, offset*2,data,mem_mask, which);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCR - Timer Capture Register for timer %d) (illegal, read-only)\n", m_ppc, offset*2,data,mem_mask, which);
break;
case m68307TIMER_TCN: /* 0x3 (0x126 / 0x136) */
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCN - Timer Counter for timer %d)\n", pc, offset*2,data,mem_mask, which);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TCN - Timer Counter for timer %d)\n", m_ppc, offset*2,data,mem_mask, which);
break;
case m68307TIMER_TER: /* 0x4 (0x128 / 0x138) */
/* 8-bit only!! */
//logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TER - Timer Event Register for timer %d)\n", pc, offset*2,data,mem_mask, which);
//logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (TER - Timer Event Register for timer %d)\n", m_ppc, offset*2,data,mem_mask, which);
timer.write_ter(data, mem_mask, which);
break;
case m68307TIMER_WRR: /* 0x5 (0x12a / 0x13a) */
if (which==0)
{
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Reference Register)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Reference Register)\n", m_ppc, offset*2,data,mem_mask);
}
else
{
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", m_ppc, offset*2,data,mem_mask);
}
break;
case m68307TIMER_WCR: /* 0x6 (0x12c / 0x13c) */
if (which==0)
{
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Counter Register)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (WRR - Watchdog Counter Register)\n", m_ppc, offset*2,data,mem_mask);
}
else
{
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", m_ppc, offset*2,data,mem_mask);
}
break;
case m68307TIMER_XXX: /* 0x7 (0x12e / 0x13e) */
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", pc, offset*2,data,mem_mask);
logerror("%08x m68307_internal_timer_w %08x, %04x (%04x) (illegal)\n", m_ppc, offset*2,data,mem_mask);
break;
}
}

12
src/devices/machine/68340dma.cpp
View File

@ -8,16 +8,20 @@
READ32_MEMBER( m68340_cpu_device::m68340_internal_dma_r )
{
int pc = space.device().safe_pc();
logerror("%08x m68340_internal_dma_r %08x, (%08x)\n", pc, offset*4,mem_mask);
assert(m_m68340DMA);
//m68340_dma &dma = *m_m68340DMA;
logerror("%08x m68340_internal_dma_r %08x, (%08x)\n", m_ppc, offset*4,mem_mask);
return 0x00000000;
}
WRITE32_MEMBER( m68340_cpu_device::m68340_internal_dma_w )
{
int pc = space.device().safe_pc();
logerror("%08x m68340_internal_dma_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
assert(m_m68340DMA);
//m68340_dma &dma = *m_m68340DMA;
logerror("%08x m68340_internal_dma_w %08x, %08x (%08x)\n", m_ppc, offset*4,data,mem_mask);
}
void m68340_dma::reset()

18
src/devices/machine/68340ser.cpp
View File

@ -43,7 +43,7 @@ READ8_MEMBER( mc68340_serial_module_device::read )
LOG("%s\n", FUNCNAME);
int val = 0;
LOGR("%08x %s %08x, (%08x)\n", space.device().safe_pc(), FUNCNAME, offset, mem_mask);
LOGR("%08x %s %08x, (%08x)\n", m_cpu->pcbase(), FUNCNAME, offset, mem_mask);
/*Setting the STP bit stops all clocks within the serial module (including the crystal
or external clock and SCLK), except for the clock from the IMB. The clock from the IMB
@ -60,19 +60,19 @@ READ8_MEMBER( mc68340_serial_module_device::read )
{
case REG_MCRH:
val = m_mcrh;
LOGSERIAL("- %08x %s %04x, %04x (%04x) (MCRH - Module Configuration Register High byte)\n", space.device().safe_pc(), FUNCNAME, offset, val, mem_mask);
LOGSERIAL("- %08x %s %04x, %04x (%04x) (MCRH - Module Configuration Register High byte)\n", m_cpu->pcbase(), FUNCNAME, offset, val, mem_mask);
break;
case REG_MCRL:
val = m_mcrl;
LOGSERIAL("- %08x %s %04x, %04x (%04x) (MCRL - Module Configuration Register Low byte)\n", space.device().safe_pc(), FUNCNAME, offset, val, mem_mask);
LOGSERIAL("- %08x %s %04x, %04x (%04x) (MCRL - Module Configuration Register Low byte)\n", m_cpu->pcbase(), FUNCNAME, offset, val, mem_mask);
break;
case REG_ILR:
val = m_ilr;
LOGSERIAL("- %08x %s %04x, %04x (%04x) (ILR - Interrupt Level Register)\n", space.device().safe_pc(), FUNCNAME, offset, val, mem_mask);
LOGSERIAL("- %08x %s %04x, %04x (%04x) (ILR - Interrupt Level Register)\n", m_cpu->pcbase(), FUNCNAME, offset, val, mem_mask);
break;
case REG_IVR:
val = m_ivr;
LOGSERIAL("- %08x %s %04x, %04x (%04x) (IVR - Interrupt Vector Register)\n", space.device().safe_pc(), FUNCNAME, offset, val, mem_mask);
LOGSERIAL("- %08x %s %04x, %04x (%04x) (IVR - Interrupt Vector Register)\n", m_cpu->pcbase(), FUNCNAME, offset, val, mem_mask);
break;
}
@ -118,25 +118,25 @@ WRITE8_MEMBER( mc68340_serial_module_device::write )
{
case REG_MCRH:
m_mcrh = data;
LOGSERIAL("PC: %08x %s %04x, %04x (%04x) (MCRH - Module Configuration Register High byte)\n", space.device().safe_pc(), FUNCNAME, offset, data, mem_mask);
LOGSERIAL("PC: %08x %s %04x, %04x (%04x) (MCRH - Module Configuration Register High byte)\n", m_cpu->pcbase(), FUNCNAME, offset, data, mem_mask);
LOGSERIAL("- Clocks are %s\n", data & REG_MCRH_STP ? "stopped" : "running");
LOGSERIAL("- Freeze signal %s - not implemented\n", data & REG_MCRH_FRZ1 ? "stops at character boundary" : "is ignored");
LOGSERIAL("- CTS capture clock: %s - not implemented\n", data & REG_MCRH_ICCS ? "SCLK" : "Crystal");
break;
case REG_MCRL:
m_mcrl = data;
LOGSERIAL("PC: %08x %s %04x, %04x (%04x) (MCRL - Module Configuration Register Low byte)\n", space.device().safe_pc(), FUNCNAME, offset, data, mem_mask);
LOGSERIAL("PC: %08x %s %04x, %04x (%04x) (MCRL - Module Configuration Register Low byte)\n", m_cpu->pcbase(), FUNCNAME, offset, data, mem_mask);
LOGSERIAL("- Supervisor registers %s - not implemented\n", data & REG_MCRL_SUPV ? "requries supervisor privileges" : "can be accessed by user privileged software");
LOGSERIAL("- Interrupt Arbitration level: %02x - not implemented\n", data & REG_MCRL_ARBLV);
break;
case REG_ILR:
m_ilr = data;
LOGSERIAL("PC: %08x %s %04x, %04x (%04x) (ILR - Interrupt Level Register)\n", space.device().safe_pc(), FUNCNAME, offset, data, mem_mask);
LOGSERIAL("PC: %08x %s %04x, %04x (%04x) (ILR - Interrupt Level Register)\n", m_cpu->pcbase(), FUNCNAME, offset, data, mem_mask);
LOGSERIAL("- Interrupt Level: %02x\n", data & REG_ILR_MASK);
break;
case REG_IVR:
m_ivr = data;
LOGSERIAL("PC: %08x %s %04x, %04x (%04x) (IVR - Interrupt Vector Register)\n", space.device().safe_pc(), FUNCNAME, offset, data, mem_mask);
LOGSERIAL("PC: %08x %s %04x, %04x (%04x) (IVR - Interrupt Vector Register)\n", m_cpu->pcbase(), FUNCNAME, offset, data, mem_mask);
LOGSERIAL("- Interrupt Vector: %02x\n", data);
break;
default:

88
src/devices/machine/68340sim.cpp
View File

@ -48,48 +48,47 @@ READ16_MEMBER( m68340_cpu_device::m68340_internal_sim_r )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int val = 0;
int pc = space.device().safe_pc();
switch (offset * 2)
{
case m68340_sim::REG_MCR:
LOGSIM("- %08x %s %04x, (%04x) (MCR - Module Configuration Register) - not implemented\n", pc, FUNCNAME, offset * 2, mem_mask);
LOGSIM("- %08x %s %04x, (%04x) (MCR - Module Configuration Register) - not implemented\n", m_ppc, FUNCNAME, offset * 2, mem_mask);
val = sim.m_mcr;
break;
case m68340_sim::REG_SYNCR:
LOGSIM("- %08x %s %04x, (%04x) (SYNCR - Clock Synthesizer Register) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
LOGSIM("- %08x %s %04x, (%04x) (SYNCR - Clock Synthesizer Register) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_syncr;
break;
case m68340_sim::REG_AVR_RSR:
LOGSIM("- %08x %s %04x, (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
LOGSIM("- %08x %s %04x, (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_avr_rsr;
break;
case m68340_sim::REG_SWIV_SYPCR:
LOGSIM("- %08x %s %04x, (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
LOGSIM("- %08x %s %04x, (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_swiv_sypcr;
break;
case m68340_sim::REG_PICR:
LOGPIT("- %08x %s %04x, (%04x) (PICR - Periodic Interrupt Control Register) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
LOGPIT("- %08x %s %04x, (%04x) (PICR - Periodic Interrupt Control Register) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_picr;
break;
case m68340_sim::REG_PITR:
LOGPIT("- %08x %s %04x, (%04x) (PITR - Periodic Interrupt Timer Register) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
LOGPIT("- %08x %s %04x, (%04x) (PITR - Periodic Interrupt Timer Register) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_pitr;
break;
case m68340_sim::REG_SWSR:
LOGSIM("- %08x %s %04x, (%04x) (SWSR - Software Service) - not implemented\n", pc, FUNCNAME, offset*2,mem_mask);
LOGSIM("- %08x %s %04x, (%04x) (SWSR - Software Service) - not implemented\n", m_ppc, FUNCNAME, offset*2,mem_mask);
val = sim.m_swsr;
break;
default:
logerror("- %08x %s %04x, (%04x) (unsupported register)\n", pc, FUNCNAME, offset * 2, mem_mask);
LOGSIM("- %08x %s %04x, (%04x) (unsupported register)\n", pc, FUNCNAME, offset * 2, mem_mask);
logerror("- %08x %s %04x, (%04x) (unsupported register)\n", m_ppc, FUNCNAME, offset * 2, mem_mask);
LOGSIM("- %08x %s %04x, (%04x) (unsupported register)\n", m_ppc, FUNCNAME, offset * 2, mem_mask);
}
LOGR(" * Reg %02x -> %02x - %s\n", offset * 2, val,
@ -109,13 +108,11 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int pc = space.device().safe_pc();
switch (offset<<1)
{
case m68340_sim::REG_MCR:
COMBINE_DATA(&sim.m_mcr);
LOGSIM("PC: %08x %s %04x, %04x (%04x) (MCR - Module Configuration Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGSIM("PC: %08x %s %04x, %04x (%04x) (MCR - Module Configuration Register)\n", m_ppc, FUNCNAME, offset * 2, data, mem_mask);
LOGPIT("- FRZ1: Watchdog and PIT timer are %s\n", (data & m68340_sim::REG_MCR_FRZ1) == 0 ? "enabled" : "disabled");
LOGSIM("- FRZ0: The BUS monitor is %s\n", (data & m68340_sim::REG_MCR_FRZ0) == 0 ? "enabled" : "disabled");
LOGSIM("- FIRQ: Full Interrupt Request Mode %s\n", data & m68340_sim::REG_MCR_FIRQ ? "used on port B" : "supressed, adding 4 chip select lines on Port B");
@ -125,7 +122,7 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
break;
case m68340_sim::REG_SYNCR:
LOGSIM("PC: %08x %s %04x, %04x (%04x) (SYNCR - Clock Synthesizer Register) - not implemented\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGSIM("PC: %08x %s %04x, %04x (%04x) (SYNCR - Clock Synthesizer Register) - not implemented\n", m_ppc, FUNCNAME, offset * 2, data, mem_mask);
COMBINE_DATA(&sim.m_syncr);
LOGSIM("- W : VCO x %d\n", data & m68340_sim::REG_SYNCR_W ? 4 : 1);
LOGSIM("- X : System clock / %d\n", data & m68340_sim::REG_SYNCR_X ? 1 : 2);
@ -147,14 +144,14 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
break;
case m68340_sim::REG_AVR_RSR:
LOGSIM("PC: %08x %s %04x, %04x (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGSIM("PC: %08x %s %04x, %04x (%04x) (AVR, RSR - Auto Vector Register, Reset Status Register)\n", m_ppc, FUNCNAME, offset * 2, data, mem_mask);
COMBINE_DATA(&sim.m_avr_rsr);
LOGSIM("- AVR: AV7-AV1 autovector bits: %02x\n", ((data & m68340_sim::REG_AVR_VEC) >> 8) & 0xff);
LOGSIM("- RSR: Last reset type: %02x - not implemented\n", (data & m68340_sim::REG_RSR_RESBITS) & 0xff);
break;
case m68340_sim::REG_SWIV_SYPCR:
LOGSIM("PC: %08x %s %04x, %04x (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register) - not implemented\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGSIM("PC: %08x %s %04x, %04x (%04x) (SWIV_SYPCR - Software Interrupt Vector, System Protection Control Register) - not implemented\n", m_ppc, FUNCNAME, offset * 2, data, mem_mask);
COMBINE_DATA(&sim.m_swiv_sypcr);
LOGSIM("- SWIV: Software watchdog Interrupt Vector: %02x\n", ((data & m68340_sim::REG_SWIV_VEC) >> 8) & 0xff);
LOGSIM("- SWE : Software watchdog %s\n", (data & m68340_sim::REG_SYPCR_SWE) ? "enabled" : "disabled");
@ -164,14 +161,14 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
break;
case m68340_sim::REG_PICR:
LOGPIT("PC: %08x %s %04x, %04x (%04x) (PICR - Periodic Interrupt Control Register)\n", pc, FUNCNAME, offset*2,data,mem_mask);
LOGPIT("PC: %08x %s %04x, %04x (%04x) (PICR - Periodic Interrupt Control Register)\n", m_ppc, FUNCNAME, offset*2,data,mem_mask);
COMBINE_DATA(&sim.m_picr);
LOGPIT("- PIRQL: Periodic Interrupt Level %d%s\n", (data & m68340_sim::REG_PICR_PIRQL) >> 8, (data & m68340_sim::REG_PICR_PIRQL) == 0 ? " (disabled)" : "");
LOGPIT("- PIV : Periodic Interrupt Vector %02x\n", (data & m68340_sim::REG_PICR_PIVEC));
break;
case m68340_sim::REG_PITR:
LOGPIT("PC: %08x %s %04x, %04x (%04x) (PITR - Periodic Interrupt Timer Register)\n", pc, FUNCNAME, offset*2,data,mem_mask);
LOGPIT("PC: %08x %s %04x, %04x (%04x) (PITR - Periodic Interrupt Timer Register)\n", m_ppc, FUNCNAME, offset*2,data,mem_mask);
COMBINE_DATA(&sim.m_pitr);
LOGSIM("- SWP : Software watchdog prescale factor is %d\n", (data & m68340_sim::REG_PITR_SWP) ? 512 : 1);
LOGPIT("- PTP : Periodic timer prescale factor is %d\n", (data & m68340_sim::REG_PITR_PTP) ? 512 : 1);
@ -187,11 +184,11 @@ WRITE16_MEMBER( m68340_cpu_device::m68340_internal_sim_w )
case m68340_sim::REG_SWSR:
// basically watchdog, you must write an alternating pattern of 0x55 / 0xaa to keep the watchdog from resetting the system
//LOGSIM("- %08x %s %04x, %04x (%04x) (SWSR - Software Service)\n", pc, FUNCNAME, offset*2,data,mem_mask);
//LOGSIM("- %08x %s %04x, %04x (%04x) (SWSR - Software Service)\n", m_ppc, FUNCNAME, offset*2,data,mem_mask);
break;
default:
LOGSIM("- %08x %s %04x, %04x (%04x) - not implemented\n", pc, FUNCNAME, offset*2,data,mem_mask);
LOGSIM("- %08x %s %04x, %04x (%04x) - not implemented\n", m_ppc, FUNCNAME, offset*2,data,mem_mask);
}
}
@ -203,13 +200,12 @@ READ8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_r )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int pc = space.device().safe_pc();
int val = space.machine().rand();
switch (offset)
{
case m68340_sim::REG_PORTA:
LOGR("- %08x %s %04x (PORTA - Port A Data)\n", pc, FUNCNAME, offset);
LOGR("- %08x %s %04x (PORTA - Port A Data)\n", m_ppc, FUNCNAME, offset);
sim.m_porta &= sim.m_ddra;
// TODO: call callback
@ -227,25 +223,25 @@ READ8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_r )
break;
case m68340_sim::REG_DDRA:
LOGR("- %08x %s %04x (DDRA - Port A Data Direction)\n", pc, FUNCNAME, offset);
LOGR("- %08x %s %04x (DDRA - Port A Data Direction)\n", m_ppc, FUNCNAME, offset);
val = sim.m_ddra;
break;
case m68340_sim::REG_PPARA1:
LOGR("- %08x %s %04x (PPRA1 - Port A Pin Assignment 1)\n", pc, FUNCNAME, offset);
LOGR("- %08x %s %04x (PPRA1 - Port A Pin Assignment 1)\n", m_ppc, FUNCNAME, offset);
val = sim.m_ppara1;
break;
case m68340_sim::REG_PPARA2:
LOGR("- %08x %s %04x (PPRA2 - Port A Pin Assignment 2) - not implemented\n", pc, FUNCNAME, offset);
LOGR("- %08x %s %04x (PPRA2 - Port A Pin Assignment 2) - not implemented\n", m_ppc, FUNCNAME, offset);
val = sim.m_ppara2;
break;
case m68340_sim::REG_PORTB1:
LOGR("- %08x %s %04x (PORTB1 - Port B Data 1)\n", pc, FUNCNAME, offset);
LOGR("- %08x %s %04x (PORTB1 - Port B Data 1)\n", m_ppc, FUNCNAME, offset);
// Fallthrough to mirror register
case m68340_sim::REG_PORTB:
LOGR("- %08x %s %04x (PORTB - Port B Data 0)\n", pc, FUNCNAME, offset);
LOGR("- %08x %s %04x (PORTB - Port B Data 0)\n", m_ppc, FUNCNAME, offset);
sim.m_portb &= sim.m_ddrb;
// TODO: call callback
@ -263,18 +259,18 @@ READ8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_r )
break;
case m68340_sim::REG_DDRB:
LOGR("- %08x %s %04x (DDR - Port B Data Direction)\n", pc, FUNCNAME, offset);
LOGR("- %08x %s %04x (DDR - Port B Data Direction)\n", m_ppc, FUNCNAME, offset);
val = sim.m_ddrb;
break;
case m68340_sim::REG_PPARB:
LOGR("- %08x %s %04x (PPARB - Port B Pin Assignment)\n", pc, FUNCNAME, offset);
LOGR("- %08x %s %04x (PPARB - Port B Pin Assignment)\n", m_ppc, FUNCNAME, offset);
val = sim.m_pparb;
break;
default:
LOGR("- %08x %s %04x (ILLEGAL?)\n", pc, FUNCNAME, offset);
logerror("%08x m68340_internal_sim_r %04x (ILLEGAL?)\n", pc, FUNCNAME, offset);
LOGR("- %08x %s %04x (ILLEGAL?)\n", m_ppc, FUNCNAME, offset);
logerror("%08x m68340_internal_sim_r %04x (ILLEGAL?)\n", m_ppc, FUNCNAME, offset);
break;
}
LOGR(" * Reg %02x -> %02x - %s\n", offset, val, std::array<char const *, 16>
@ -290,14 +286,12 @@ WRITE8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_w )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int pc = space.device().safe_pc();
LOGSETUP(" * Reg %02x <- %02x - %s\n", offset, data, std::array<char const *, 8>
{{"PORTA", "DDRA", "PPRA1", "PPRA2", "PORTB", "PORTB1", "DDRB", "PPARB"}}[(offset - 0x10) / 2]);
switch (offset)
{
case m68340_sim::REG_PORTA:
LOGDATA("- %08x %04x, %02x (PORTA - Port A Data)\n", pc, offset,data);
LOGDATA("- %08x %04x, %02x (PORTA - Port A Data)\n", m_ppc, offset,data);
sim.m_porta = (data & sim.m_ddra & sim.m_ppara1);
// callback
@ -305,25 +299,25 @@ WRITE8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_w )
break;
case m68340_sim::REG_DDRA:
LOGPORTS("- %08x %04x, %02x (DDRA - Port A Data Direction)\n", pc, offset,data);
LOGPORTS("- %08x %04x, %02x (DDRA - Port A Data Direction)\n", m_ppc, offset,data);
sim.m_ddra = data;
break;
case m68340_sim::REG_PPARA1:
LOGPORTS("- %08x %04x, %02x (PPARA1 - Port A Pin Assignment 1)\n", pc, offset,data);
LOGPORTS("- %08x %04x, %02x (PPARA1 - Port A Pin Assignment 1)\n", m_ppc, offset,data);
sim.m_ppara1 = data;
break;
case m68340_sim::REG_PPARA2:
LOGPORTS("- %08x %04x, %02x (PPARA2 - Port A Pin Assignment 2)\n", pc, offset,data);
LOGPORTS("- %08x %04x, %02x (PPARA2 - Port A Pin Assignment 2)\n", m_ppc, offset,data);
sim.m_ppara2 = data;
break;
case m68340_sim::REG_PORTB1:
LOGDATA("- %08x %04x, %02x (PORTB1 - Port B Data - mirror)\n", pc, offset,data);
LOGDATA("- %08x %04x, %02x (PORTB1 - Port B Data - mirror)\n", m_ppc, offset,data);
// Falling through to mirrored register portb
case m68340_sim::REG_PORTB:
LOGDATA("- %08x %04x, %02x (PORTB - Port B Data)\n", pc, offset,data);
LOGDATA("- %08x %04x, %02x (PORTB - Port B Data)\n", m_ppc, offset,data);
sim.m_portb = (data & sim.m_ddrb & sim.m_pparb);
// callback
@ -331,18 +325,18 @@ WRITE8_MEMBER( m68340_cpu_device::m68340_internal_sim_ports_w )
break;
case m68340_sim::REG_DDRB:
LOGPORTS("- %08x %04x, %02x (DDR - Port B Data Direction)\n", pc, offset,data);
LOGPORTS("- %08x %04x, %02x (DDR - Port B Data Direction)\n", m_ppc, offset,data);
sim.m_ddrb = data;
break;
case m68340_sim::REG_PPARB:
LOGPORTS("- %08x %04x, %02x (PPARB - Port B Pin Assignment)\n", pc, offset,data);
LOGPORTS("- %08x %04x, %02x (PPARB - Port B Pin Assignment)\n", m_ppc, offset,data);
sim.m_pparb = data;
break;
default:
LOGPORTS("- %08x %s %04x, %02x (ILLEGAL?) - not implemented\n", pc, FUNCNAME, offset,data);
logerror("%08x m68340_internal_sim_ports_w %04x, %02x (ILLEGAL?)\n", pc, offset,data);
LOGPORTS("- %08x %s %04x, %02x (ILLEGAL?) - not implemented\n", m_ppc, FUNCNAME, offset,data);
logerror("%08x m68340_internal_sim_ports_w %04x, %02x (ILLEGAL?)\n", m_ppc, offset,data);
break;
}
}
@ -355,8 +349,6 @@ READ32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_r )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int pc = space.device().safe_pc();
switch (offset<<2)
{
case m68340_sim::REG_AM_CS0: return sim.m_am[0];
@ -369,7 +361,7 @@ READ32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_r )
case m68340_sim::REG_BA_CS3: return sim.m_ba[3];
default:
logerror("%08x m68340_internal_sim_r %08x, (%08x)\n", pc, offset*4,mem_mask);
logerror("%08x m68340_internal_sim_r %08x, (%08x)\n", m_ppc, offset*4,mem_mask);
}
return 0x00000000;
@ -394,8 +386,6 @@ WRITE32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_w )
assert(m_m68340SIM);
m68340_sim &sim = *m_m68340SIM;
int pc = space.device().safe_pc();
switch (offset << 2)
{
case m68340_sim::REG_AM_CS0:
@ -431,7 +421,7 @@ WRITE32_MEMBER( m68340_cpu_device::m68340_internal_sim_cs_w )
break;
default:
logerror("%08x m68340_internal_sim_cs_w %08x, %08x (%08x)\n", pc, offset*4,data,mem_mask);
logerror("%08x m68340_internal_sim_cs_w %08x, %08x (%08x)\n", m_ppc, offset*4,data,mem_mask);
break;
}
}

49
src/devices/machine/68340tmu.cpp
View File

@ -43,8 +43,7 @@ READ16_MEMBER( mc68340_timer_module_device::read )
int val = 0;
int pc = space.device().safe_pc();
LOGR("%08x m68340_internal_timer_r %08x, (%08x)\n", pc, offset * 2, mem_mask);
LOGR("%08x m68340_internal_timer_r %08x, (%08x)\n", m_cpu->pcbase(), offset * 2, mem_mask);
/*Setting the STP bit stops all clocks within the timer module except for the clock
from the IMB. The clock from the IMB remains active to allow the CPU32 access to the MCR.
@ -59,39 +58,39 @@ READ16_MEMBER( mc68340_timer_module_device::read )
{
case REG_MCR:
val = m_mcr;
LOGTIMER("- %08x %s %04x, %04x (%04x) (MCR - Module Configuration Register)\n", pc, FUNCNAME, offset * 2, val, mem_mask);
LOGTIMER("- %08x %s %04x, %04x (%04x) (MCR - Module Configuration Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, val, mem_mask);
break;
case REG_IR:
val = m_ir;
LOGTIMER("- %08x %s %04x, %04x (%04x) (IR - Interrupt Register)\n", pc, FUNCNAME, offset * 2, val, mem_mask);
LOGTIMER("- %08x %s %04x, %04x (%04x) (IR - Interrupt Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, val, mem_mask);
break;
case REG_CR:
val = m_cr;
LOGTIMER("- %08x %s %04x, %04x (%04x) (CR - Control Register)\n", pc, FUNCNAME, offset * 2, val, mem_mask);
LOGTIMER("- %08x %s %04x, %04x (%04x) (CR - Control Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, val, mem_mask);
break;
case REG_SR:
val = m_sr;
LOGTIMER("- %08x %s %04x, %04x (%04x) (SR - Status/Prescaler Register)\n", pc, FUNCNAME, offset * 2, val, mem_mask);
LOGTIMER("- %08x %s %04x, %04x (%04x) (SR - Status/Prescaler Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, val, mem_mask);
break;
case REG_CNTR:
val = m_cntr_reg;
LOGTIMER("- %08x %s %04x, %04x (%04x) (CNTR - Counter Register)\n", pc, FUNCNAME, offset * 2, val, mem_mask);
LOGTIMER("- %08x %s %04x, %04x (%04x) (CNTR - Counter Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, val, mem_mask);
break;
case REG_PREL1:
val = m_prel1;
LOGTIMER("- %08x %s %04x, %04x (%04x) (PREL1 - Preload 1 Register)\n", pc, FUNCNAME, offset * 2, val, mem_mask);
LOGTIMER("- %08x %s %04x, %04x (%04x) (PREL1 - Preload 1 Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, val, mem_mask);
break;
case REG_PREL2:
val = m_prel2;
LOGTIMER("- %08x %s %04x, %04x (%04x) (PREL2 - Preload 2 Register)\n", pc, FUNCNAME, offset * 2, val, mem_mask);
LOGTIMER("- %08x %s %04x, %04x (%04x) (PREL2 - Preload 2 Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, val, mem_mask);
break;
case REG_COM:
val = m_com;
LOGTIMER("- %08x %s %04x, %04x (%04x) (COM - Compare Register)\n", pc, FUNCNAME, offset * 2, val, mem_mask);
LOGTIMER("- %08x %s %04x, %04x (%04x) (COM - Compare Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, val, mem_mask);
break;
default:
LOGTIMER("- %08x FUNCNAME %08x, %08x (%08x) - not implemented\n", pc, offset * 2, val, mem_mask);
logerror("%08x m68340_internal_timer_r %08x, %08x (%08x)\n", pc, offset * 2, val, mem_mask);
LOGTIMER("- %08x FUNCNAME %08x, %08x (%08x) - not implemented\n", m_cpu->pcbase(), offset * 2, val, mem_mask);
logerror("%08x m68340_internal_timer_r %08x, %08x (%08x)\n", m_cpu->pcbase(), offset * 2, val, mem_mask);
break;
}
LOGR(" * Timer%d Reg %02x [%02x] -> %02x - %s\n", m_cpu->get_timer_index(this) + 1, offset * 2, offset, val, (offset * 2) > 0x12 ? "reserved" : std::array<char const *, 9> {{"MCR", "reserved", "IR", "CR", "SR", "CNTR", "PREL1", "PREL2", "COM"}}[offset % 0x20]);
@ -100,8 +99,6 @@ READ16_MEMBER( mc68340_timer_module_device::read )
WRITE16_MEMBER( mc68340_timer_module_device::write )
{
int pc = space.device().safe_pc();
LOGSETUP("\n%s\n", FUNCNAME);
LOGSETUP(" * Timer%d Reg %02x [%02x] <- %02x - %s\n", m_cpu->get_timer_index(this) + 1, (offset * 2), offset, data,
(offset * 2) > 0x12 ? "reserved" : std::array<char const *, 9>
@ -120,7 +117,7 @@ WRITE16_MEMBER( mc68340_timer_module_device::write )
{
case REG_MCR:
COMBINE_DATA(&m_mcr);
LOGTIMER("PC: %08x %s %04x, %04x (%04x) (MCR - Module Configuration Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("PC: %08x %s %04x, %04x (%04x) (MCR - Module Configuration Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("- Clocks are %s\n", data & REG_MCR_STP ? "stopped" : "running");
LOGTIMER("- Freeze signal %s - not implemented\n", data & REG_MCR_FRZ1 ? "stops execution" : "is ignored");
LOGTIMER("- Supervisor registers %s - not implemented\n", data & REG_MCR_SUPV ? "requries supervisor privileges" : "can be accessed by user privileged software");
@ -128,13 +125,13 @@ WRITE16_MEMBER( mc68340_timer_module_device::write )
break;
case REG_IR:
COMBINE_DATA(&m_ir);
LOGTIMER("PC: %08x %s %04x, %04x (%04x) (IR - Interrupt Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("PC: %08x %s %04x, %04x (%04x) (IR - Interrupt Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("- Interrupt level : %02x\n", (data & REG_IR_INTLEV) >> 8);
LOGTIMER("- Interrupt vector: %02x\n", (data & REG_IR_INTVEC));
break;
case REG_CR:
COMBINE_DATA(&m_cr);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (CR - Module Control Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (CR - Module Control Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("- Software reset: %s\n", (data & REG_CR_SWR) ? "inactive" : "active" );
LOGTIMER("- Enabled interrupts: %02x TO:%d TG:%d TC:%d\n",
data & REG_CR_INTMSK,
@ -200,7 +197,7 @@ WRITE16_MEMBER( mc68340_timer_module_device::write )
}
break;
case REG_SR:
LOGTIMER("PC %08x %s %04x, %04x (%04x) (SR - Status/Prescaler Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (SR - Status/Prescaler Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, data, mem_mask);
/* IRQ - Interrupt Request bit
1 = An interrupt condition has occurred. This bit is the logical OR of the enabled TO, TG, and TC interrupt bits.
@ -212,7 +209,7 @@ WRITE16_MEMBER( mc68340_timer_module_device::write )
// TODO: clear IRQ line
}
COMBINE_DATA(&m_sr);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (SR - Status/Prescaler Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (SR - Status/Prescaler Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("- IRQ: %s\n", (data & REG_SR_IRQ) ? "Yes" : "None");
LOGTIMER("- TO TimeOut int : %s\n", (data & REG_SR_TO) ? "Asserted" : "Cleared");
LOGTIMER("- TG Timer Gate int : %s\n", (data & REG_SR_TG) ? "Asserted" : "Cleared");
@ -225,30 +222,30 @@ WRITE16_MEMBER( mc68340_timer_module_device::write )
break;
case REG_CNTR:
COMBINE_DATA(&m_cntr_reg);
LOGTIMER("- %08x %s %04x, %04x (%04x) (CNTR - Counter Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("- %08x %s %04x, %04x (%04x) (CNTR - Counter Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, data, mem_mask);
break;
case REG_PREL1:
COMBINE_DATA(&m_prel1);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (PREL1 - Preload 1 Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (PREL1 - Preload 1 Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("- PR1-15 to PR1-0: %04x\n", (data & 0xffff));
break;
case REG_PREL2:
COMBINE_DATA(&m_prel2);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (PREL2 - Preload 2 Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (PREL2 - Preload 2 Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("- PR2-15 to PR2-0: %04x\n", (data & 0xffff));
break;
case REG_COM:
COMBINE_DATA(&m_com);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (COM - Compare Register)\n", pc, FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("PC %08x %s %04x, %04x (%04x) (COM - Compare Register)\n", m_cpu->pcbase(), FUNCNAME, offset * 2, data, mem_mask);
LOGTIMER("- COM15-COM0: %04x\n", (data & 0xfff));
break;
default:
LOGTIMER("- %08x FUNCNAME %08x, %08x (%08x) - not implemented\n", pc, offset * 2, data, mem_mask);
logerror("%08x m68340_internal_sim_w %08x, %08x (%08x)\n", pc, offset * 2, data, mem_mask);
LOGTIMER("- %08x FUNCNAME %08x, %08x (%08x) - not implemented\n", m_cpu->pcbase(), offset * 2, data, mem_mask);
logerror("%08x m68340_internal_sim_w %08x, %08x (%08x)\n", m_cpu->pcbase(), offset * 2, data, mem_mask);
break;
}
LOG("%08x m68340_internal_timer_w %08x, %08x (%08x)\n", pc, offset * 2, data, mem_mask);
LOG("%08x m68340_internal_timer_w %08x, %08x (%08x)\n", m_cpu->pcbase(), offset * 2, data, mem_mask);
}
WRITE_LINE_MEMBER( mc68340_timer_module_device::tin_w)