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https://github.com/holub/mame
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-sun4c_mmu: Checkins, likely will cause other regressions, but checking in as a checkpoint, nw
This commit is contained in:
MooglyGuy
parent
9e34a7f5cb
commit
b0dd896e3e
@ -36,7 +36,7 @@ DEFINE_DEVICE_TYPE(SUN4C_MMU, sun4c_mmu_device, "sun4c_mmu", "Sun 4c MMU")
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#define LOG_PARITY (1U << 15)
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#define LOG_ALL_ASI (1U << 16) // WARNING: Heavy!
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#define VERBOSE (LOG_CACHE_TAGS)
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#define VERBOSE (0)
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#include "logmacro.h"
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sun4_mmu_base_device::sun4_mmu_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock)
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@ -130,6 +130,13 @@ void sun4_mmu_base_device::device_start()
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using namespace std::placeholders;
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machine().debugger().console().register_command("l2p", CMDFLAG_NONE, 0, 1, 1, std::bind(&sun4_mmu_base_device::l2p_command, this, _1, _2));
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}
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m_cache_tag_mask = m_cache_mask >> 3;
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printf("m_page_mask %08x\n", m_page_mask);
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printf("m_seg_entry_shift %08x\n", m_seg_entry_shift);
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printf("m_seg_entry_mask %08x\n", m_seg_entry_mask);
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printf("m_page_entry_mask %08x\n", m_page_entry_mask);
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printf("m_cache_mask %08x\n", m_cache_mask);
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}
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void sun4_mmu_base_device::device_reset()
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@ -170,7 +177,7 @@ void sun4_mmu_base_device::device_reset()
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m_system_enable = 0;
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m_fetch_bootrom = true;
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memset(m_buserr, 0, sizeof(uint32_t) * 8);
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memset(m_buserr, 0, sizeof(uint32_t) * 16);
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for (int i = 0; i < 16; i++)
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{
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memset(&m_segmap[i][0], 0, 4096);
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@ -219,7 +226,6 @@ uint32_t sun4_mmu_base_device::read_asi(uint8_t asi, uint32_t offset, uint32_t m
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case 12:
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case 13:
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case 14:
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cache_flush_r();
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return 0;
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default:
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return ~0;
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@ -253,9 +259,13 @@ void sun4_mmu_base_device::write_asi(uint8_t asi, uint32_t offset, uint32_t data
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insn_data_w<SUPER_DATA>(offset, data, mem_mask);
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return;
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case 12:
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segment_flush_w(offset);
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break;
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case 13:
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page_flush_w(offset);
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break;
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case 14:
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cache_flush_w();
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context_flush_w(offset);
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return;
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default:
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return;
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@ -293,15 +303,33 @@ void sun4_mmu_base_device::parity_w(uint32_t offset, uint32_t data, uint32_t mem
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}
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}
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uint32_t sun4_mmu_base_device::cache_flush_r()
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void sun4_mmu_base_device::segment_flush_w(const uint32_t vaddr)
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{
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// Do nothing for now
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return 0;
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logerror("%s: segment_flush_w %08x\n", machine().describe_context(), vaddr);
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}
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void sun4_mmu_base_device::cache_flush_w()
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void sun4_mmu_base_device::context_flush_w(const uint32_t vaddr)
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{
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// Do nothing for now
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logerror("%s: context_flush_w %08x\n", machine().describe_context(), vaddr);
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const uint32_t cache_addr = (vaddr >> 3) & m_cache_mask;
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if ((m_cachetags[cache_addr] & (1 << 19)) != 0)
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{
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if (((m_cachetags[cache_addr] >> 20) & m_ctx_mask) == m_context_masked)
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{
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const uint32_t paddr = ((cache_addr << 12) & 0x0fffc000) | ((vaddr << 2) & 0x3ff8);
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const uint32_t caddr = (vaddr & ~7) & m_cache_mask;
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if (paddr < m_populated_ram_words)
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{
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memcpy(m_ram_ptr, &m_cachedata[caddr], sizeof(uint32_t) * 8);
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}
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m_cachetags[cache_addr] &= ~(1 << 19);
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}
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}
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}
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void sun4_mmu_base_device::page_flush_w(const uint32_t vaddr)
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{
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logerror("%s: page_flush_w %08x\n", machine().describe_context(), vaddr);
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}
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uint32_t sun4_mmu_base_device::system_r(const uint32_t offset, const uint32_t mem_mask)
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@ -333,11 +361,11 @@ uint32_t sun4_mmu_base_device::system_r(const uint32_t offset, const uint32_t me
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}
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case 8: // (d-)cache tags
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LOGMASKED(LOG_CACHE_TAGS, "sun4_mmu: read dcache tags @ %x, PC = %x\n", offset, m_cpu->pc());
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return m_cachetags[offset & m_cache_mask];
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LOGMASKED(LOG_CACHE_TAGS, "%s: sun4c_mmu: read dcache tags @ %x, PC = %x\n", machine().describe_context(), offset << 2, m_cpu->pc());
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return m_cachetags[(offset >> 3) & m_cache_tag_mask];
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case 9: // (d-)cache data
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LOGMASKED(LOG_CACHE_DATA, "sun4c_mmu: read dcache data @ %x, PC = %x\n", offset, m_cpu->pc());
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LOGMASKED(LOG_CACHE_DATA, "%s: sun4c_mmu: read dcache data @ %x, PC = %x\n", machine().describe_context(), offset << 2, m_cpu->pc());
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return m_cachedata[offset & m_cache_mask];
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case 0xf: // UART bypass
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@ -401,17 +429,18 @@ void sun4_mmu_base_device::system_w(const uint32_t offset, const uint32_t data,
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}
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case 8: // cache tags
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LOGMASKED(LOG_CACHE_TAGS, "%s: write cache tags %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
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m_cachetags[offset & m_cache_mask] = data & 0x03f8fffc;
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if (m_cpu->pc() == 0xFFE8B940)
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LOGMASKED(LOG_CACHE_TAGS, "%s: write dcache tags %08x = %08x & %08x\n", machine().describe_context(), offset << 2, data, mem_mask);
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m_cachetags[(offset >> 3) & m_cache_tag_mask] = data & 0x03f8fffc;
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/*if (m_cpu->pc() == 0xFFE8B4F8)
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{
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m_log_mem = true;
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}
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}*/
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return;
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case 9: // cache data
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LOGMASKED(LOG_CACHE_DATA, "write cache data %08x = %08x & %08x\n", offset << 2, data, mem_mask);
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m_cachedata[offset & m_cache_mask] = data;
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COMBINE_DATA((&m_cachedata[0] + (offset & m_cache_mask)));
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m_cachetags[(offset >> 3) & m_cache_tag_mask] &= ~(1 << 19);
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return;
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case 0xf: // UART bypass
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@ -532,6 +561,46 @@ void sun4_mmu_base_device::merge_page_entry(uint32_t index, uint32_t data, uint3
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pe.page = (new_value & m_page_entry_mask) << m_seg_entry_shift;
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}
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bool sun4_mmu_base_device::cache_fetch(page_entry &entry, uint32_t vaddr, uint32_t paddr, uint32_t &cached_data)
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{
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const uint32_t cache_entry = (vaddr >> 3) & m_cache_tag_mask;
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if (!(m_cachetags[cache_entry] & (1 << 19)))
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{
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if (entry.valid)
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{
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m_cachetags[cache_entry] = (1 << 19);
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m_cachetags[cache_entry] |= entry.supervisor ? (1 << 20) : (0 << 20);
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m_cachetags[cache_entry] |= entry.writable ? (1 << 21) : (0 << 21);
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}
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else
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{
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return false;
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}
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}
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else if ((m_cachetags[cache_entry] & 0xfffc) == ((vaddr >> 12) & 0xfffc))
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{
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logerror("Cache read: %08x = %08x\n", vaddr << 2, m_cachedata[vaddr & m_cache_mask]);
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cached_data = m_cachedata[vaddr & m_cache_mask];
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return true;
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}
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else if (!entry.valid)
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{
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return false;
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}
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m_cachetags[cache_entry] &= ~0xfffc;
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m_cachetags[cache_entry] |= (vaddr >> 12) & 0xfffc;
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m_cachetags[cache_entry] &= ~(m_ctx_mask << 20);
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m_cachetags[cache_entry] |= (m_context_masked) << 20;
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const uint32_t cache_line_start = (vaddr & ~7) & m_cache_mask;
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const uint32_t mem_line_start = paddr & ~7;
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for (uint32_t i = 0; i < 8; i++)
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{
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m_cachedata[cache_line_start + i] = m_ram_ptr[mem_line_start + i];
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}
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cached_data = m_cachedata[vaddr & m_cache_mask];
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return true;
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}
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template uint32_t sun4_mmu_base_device::insn_data_r<sun4_mmu_base_device::USER_INSN>(const uint32_t, const uint32_t);
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template uint32_t sun4_mmu_base_device::insn_data_r<sun4_mmu_base_device::SUPER_INSN>(const uint32_t, const uint32_t);
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template uint32_t sun4_mmu_base_device::insn_data_r<sun4_mmu_base_device::USER_DATA>(const uint32_t, const uint32_t);
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@ -551,10 +620,11 @@ uint32_t sun4_mmu_base_device::insn_data_r(const uint32_t offset, const uint32_t
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// it's translation time
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const uint32_t pmeg = m_curr_segmap_masked[(offset >> 16) & 0xfff];// & m_pmeg_mask;
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const uint32_t entry_index = pmeg | ((offset >> m_seg_entry_shift) & m_seg_entry_mask);
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page_entry &entry = m_pagemap[entry_index];
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if (m_page_valid[entry_index])
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uint32_t cached_data = 0;
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if (entry.valid)
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{
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page_entry &entry = m_pagemap[entry_index];
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entry.accessed = PM_ACCESSED;
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const uint32_t tmp = entry.page | (offset & m_page_mask);
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@ -589,19 +659,18 @@ uint32_t sun4_mmu_base_device::insn_data_r(const uint32_t offset, const uint32_t
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m_buserr[1] = (offset << 2) | boffs;
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m_host->set_mae();
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}
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if (!entry.uncached)
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{
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const uint32_t cache_entry = (offset >> 2) & 0xfff;
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m_cachetags[cache_entry] |= (1 << 19);
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m_cachetags[cache_entry] &= ~(3 << 20);
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m_cachetags[cache_entry] |= entry.supervisor ? (1 << 20) : (0 << 20);
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m_cachetags[cache_entry] |= entry.writable ? (1 << 21) : (0 << 21);
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}
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const uint32_t set = (tmp >> 22) & 3;
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const uint32_t addr_mask = m_ram_set_mask[set];
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const uint32_t masked_addr = m_ram_set_base[set] + (tmp & addr_mask);
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if (!entry.uncached)
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{
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if (cache_fetch(entry, offset, masked_addr, cached_data))
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{
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return cached_data;
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}
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}
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//if (m_log_mem)
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//logerror("RAM read: %08x (%08x)\n", offset << 2, tmp << 2);
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//logerror("RAM read: %08x = %08x (%08x, %08x)\n", offset << 2, m_ram_ptr[masked_addr], tmp << 2, masked_addr);
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return m_ram_ptr[masked_addr];
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}
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else if (tmp >= 0x4000000 >> 2 && tmp < 0x10000000 >> 2)
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@ -626,6 +695,10 @@ uint32_t sun4_mmu_base_device::insn_data_r(const uint32_t offset, const uint32_t
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{
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if (!machine().side_effects_disabled())
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{
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if (cache_fetch(entry, offset, 0, cached_data))
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{
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return cached_data;
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}
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LOGMASKED(LOG_INVALID_PTE, "read invalid PTE %d (%08x), %08x & %08x, PC=%08x\n", entry_index, page_entry_to_uint(entry_index), offset << 2, mem_mask, m_cpu->pc());
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m_host->set_mae();
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m_buserr[0] |= 0x80; // invalid PTE
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@ -697,13 +770,29 @@ void sun4_mmu_base_device::insn_data_w(const uint32_t offset, const uint32_t dat
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if (ACCESSING_BITS_0_7)
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m_parity_err |= (1 << 3);
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}
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m_cachetags[(offset >> 4) & m_cache_mask] |= (1 << 19);
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const uint32_t set = (tmp >> 22) & 3;
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const uint32_t addr_mask = m_ram_set_mask[set];
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const uint32_t masked_addr = m_ram_set_base[set] + (tmp & addr_mask);
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if (!entry.uncached)
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{
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const uint32_t cache_entry = (offset >> 3) & m_cache_tag_mask;
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if ((m_cachetags[cache_entry] & (1 << 19)) != 0)
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{
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if ((m_cachetags[cache_entry] & 0xfffc) == ((offset >> 12) & 0xfffc))
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{
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logerror("Cache write: %08x (%08x) = %08x\n", (offset & m_cache_mask) << 2, offset, data);
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COMBINE_DATA((&m_cachedata[0] + (offset & m_cache_mask)));
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}
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else
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{
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logerror("Cache invalidate\n");
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m_cachetags[cache_entry] &= ~(1 << 19);
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}
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}
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}
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COMBINE_DATA((m_ram_ptr + masked_addr));
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//if (m_log_mem)
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//logerror("RAM write: %08x (%08x) = %08x\n", offset << 2, tmp << 2, data);
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//logerror("RAM write: %08x (%08x, %08x) = %08x (setting cache entry %08x)\n", offset << 2, tmp << 2, masked_addr, data, offset & m_cache_mask);
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}
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else if (tmp >= 0x4000000 >> 2 && tmp < 0x10000000 >> 2)
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{
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@ -73,6 +73,19 @@ public:
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protected:
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sun4_mmu_base_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);
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struct page_entry
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{
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uint32_t valid;
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uint32_t writable;
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uint32_t supervisor;
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uint32_t uncached;
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uint32_t accessed;
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uint32_t modified;
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uint32_t page;
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uint8_t type;
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uint8_t pad[3];
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};
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static const device_timer_id TIMER_RESET = 0;
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virtual void device_start() override;
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@ -82,8 +95,10 @@ protected:
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uint32_t page_entry_to_uint(uint32_t index);
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void merge_page_entry(uint32_t index, uint32_t data, uint32_t mem_mask);
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uint32_t cache_flush_r();
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void cache_flush_w();
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bool cache_fetch(page_entry &entry, uint32_t vaddr, uint32_t paddr, uint32_t &cached_data);
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void segment_flush_w(const uint32_t vaddr);
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void context_flush_w(const uint32_t vaddr);
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void page_flush_w(const uint32_t vaddr);
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uint32_t system_r(const uint32_t offset, const uint32_t mem_mask);
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void system_w(const uint32_t offset, const uint32_t data, const uint32_t mem_mask);
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uint32_t segment_map_r(const uint32_t offset, const uint32_t mem_mask);
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@ -113,19 +128,6 @@ protected:
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PM_MODIFIED = 0x01000000 // modified flag
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};
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struct page_entry
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{
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uint32_t valid;
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uint32_t writable;
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uint32_t supervisor;
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uint32_t uncached;
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uint32_t accessed;
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uint32_t modified;
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uint32_t page;
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uint8_t type;
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uint8_t pad[3];
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};
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required_device<cpu_device> m_cpu;
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required_device<ram_device> m_ram;
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required_memory_region m_rom;
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@ -172,6 +174,7 @@ protected:
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uint32_t m_seg_entry_mask;
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uint32_t m_page_entry_mask;
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uint32_t m_cache_mask;
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uint32_t m_cache_tag_mask;
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uint32_t m_ram_set_mask[4]; // Used for mirroring within 4 megabyte sets
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uint32_t m_ram_set_base[4];
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uint32_t m_populated_ram_words;
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