mirror of
https://github.com/holub/mame
synced 2025-05-21 21:29:15 +03:00
Sync MAME with latest megadrive code
This commit is contained in:
Angelo Salese
parent
726845063e
commit
b0ea8f45bf
@ -106,25 +106,96 @@ MD side check:
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#38 SH-2 Serial Communication (ERROR - returns a Timeout Error)
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MD & 32x check:
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#39 MD&SH-2 Master Communication (ERROR)
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#40 (something related to SCI) (STALLS)
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#41 MD&SH-2 Master FM Bit R/W (ERROR)
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#42 MD&SH-2 Slave FM Bit R/W (STALLS?)
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#40 MD&SH-2 Slave Communication (STALLS)
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#41 MD&SH-2 Master FM Bit R/W
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#42 MD&SH-2 Slave FM Bit R/W
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#43 MD&SH-2 Master DREQ CTL (ERROR)
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#44 MD&SH-2 Slave DREQ CTL (ERROR)
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#45 MD&SH-2 Master DREQ SRC address (ERROR)
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#46 MD&SH-2 Slave DREQ SRC address (ERROR)
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#47 MD&SH-2 Master DREQ DST address (ERROR)
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#48 MD&SH-2 Slave DREQ DST address (ERROR)
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#49 MD&SH-2 Master DREQ SIZE address (ERROR)
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#50 MD&SH-2 Slave DREQ SIZE address (ERROR)
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#51 SH-2 Master V IRQ (ERROR)
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#52 SH-2 Slave V IRQ (ERROR)
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#45 MD&SH-2 Master DREQ SRC address
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#46 MD&SH-2 Slave DREQ SRC address
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#47 MD&SH-2 Master DREQ DST address
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#48 MD&SH-2 Slave DREQ DST address
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#49 MD&SH-2 Master DREQ SIZE address
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#50 MD&SH-2 Slave DREQ SIZE address
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#51 SH-2 Master V IRQ
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#52 SH-2 Slave V IRQ
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#53 SH2 Master H IRQ (MD 0) (ERROR)
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#54 SH2 Slave H IRQ (MD 0) (ERROR)
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#55 SH2 Master H IRQ (MD 1) (ERROR)
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#56 SH2 Slave H IRQ (MD 1) (ERROR)
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#57 SH2 Master H IRQ (MD 2) (ERROR)
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#58 SH2 Slave H IRQ (MD 2) (ERROR)
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MD VDP check:
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#59 Bitmap Mode Register
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#60 Shift Register
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#61 Auto Fill Length Register
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#62 Auto Fill Start Address Register
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#63 V Blank BIT
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#64 H Blank BIT
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#65 Palette Enable BIT
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SH-2 VDP check:
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#66 Frame Swap BIT
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#67 SH-2 Master Bitmap MD
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#68 SH-2 Slave Bitmap MD
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#69 SH-2 Master Shift
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#70 SH-2 Slave Shift
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#71 SH-2 Master Fill SIZE
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#72 SH-2 Slave Fill SIZE
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#73 SH-2 Master Fill START
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#74 SH-2 Slave Fill START
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#75 SH-2 Master V Blank Bit
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#76 SH-2 Slave V Blank Bit
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#77 SH-2 Master H Blank Bit
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#78 SH-2 Slave H Blank Bit
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#79 SH-2 Master Palette Enable Bit
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#80 SH-2 Slave Palette Enable Bit
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#81 SH-2 Master Frame Swap Bit
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#82 SH-2 Slave Frame Swap Bit
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Framebuffer Check:
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#83 MD Frame Buffer 0
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#84 MD Frame Buffer 1
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#85 SH-2 Master Frame Buffer 0
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#86 SH-2 Slave Frame Buffer 0
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#87 SH-2 Master Frame Buffer 1
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#88 SH-2 Slave Frame Buffer 1
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#89 MD Frame Buffer 0 Overwrite
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#90 MD Frame Buffer 1 Overwrite
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#91 MD Frame Buffer 0 Byte Write
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#92 MD Frame Buffer 1 Byte Write
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#93 SH-2 Master Frame Buffer 0 Overwrite
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#94 SH-2 Slave Frame Buffer 0 Overwrite
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#95 SH-2 Master Frame Buffer 1 Overwrite
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#96 SH-2 Slave Frame Buffer 1 Overwrite
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#97 SH-2 Master Frame Buffer 0 Byte Write
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#98 SH-2 Slave Frame Buffer 0 Byte Write
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#99 SH-2 Master Frame Buffer 1 Byte Write
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#100 SH-2 Slave Frame Buffer 1 Byte Write
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#101 MD Frame Buffer 0 Fill Data
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#102 MD Frame Buffer 1 Fill Data
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#103 MD Frame Buffer 0 Fill Length & Address
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#104 MD Frame Buffer 1 Fill Length & Address
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#105 SH-2 Master Frame Buffer 0 Fill Data
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#106 SH-2 Slave Frame Buffer 0 Fill Data
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#107 SH-2 Master Frame Buffer 1 Fill Data
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#108 SH-2 Slave Frame Buffer 1 Fill Data
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#109 SH-2 Master Frame Buffer 0 Fill Address
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#110 SH-2 Slave Frame Buffer 0 Fill Address
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#111 SH-2 Master Frame Buffer 1 Fill Address
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#112 SH-2 Slave Frame Buffer 1 Fill Address
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#113 MD Palette R/W (Blank Mode)
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#114 MD Palette R/W (Display Mode)
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#115 MD Palette R/W (Fill Mode)
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#116 SH-2 Master Palette R/W (Blank Mode)
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#117 SH-2 Slave Palette R/W (Blank Mode)
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#118 SH-2 Master Palette R/W (Display Mode)
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#119 SH-2 Slave Palette R/W (Display Mode)
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#120 SH-2 Master Palette R/W (Fill Mode)
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#121 SH-2 Slave Palette R/W (Fill Mode)
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MD or SH-2 DMA check:
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#122 SH-2 Master CPU Write DMA (68S) (ERROR)
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#123 SH-2 Slave CPU Write DMA (68S) (ERROR)
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#124 MD ROM to VRAM DMA
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(asserts after this)
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*/
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@ -2824,7 +2895,13 @@ static WRITE16_HANDLER( _32x_68k_commsram_w )
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// access from the SH2 via 4030 - 403f
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/**********************************************************************************************/
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#define PWM_FIFO_SIZE pwm_tm_reg // guess, check this (Doom wants 3, Virtua Racing wants 1 like they sets this register?)
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/*
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TODO:
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- noticeable static noise on Virtua Fighter Sega logo at start-up
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- Understand if Speaker OFF makes the FIFO to advance or not
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*/
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#define PWM_FIFO_SIZE pwm_tm_reg // guess, Marsch calls this register as FIFO width
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static UINT16 pwm_ctrl,pwm_cycle,pwm_tm_reg;
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static UINT16 cur_lch[0x10],cur_rch[0x10];
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@ -2857,7 +2934,14 @@ static TIMER_CALLBACK( _32x_pwm_callback )
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{
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if(lch_index_r < PWM_FIFO_SIZE)
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{
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dac_signed_data_16_w(machine->device("lch_pwm"), cur_lch[lch_index_r++]);
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switch(pwm_ctrl & 3)
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{
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case 0: lch_index_r++; /*Speaker OFF*/ break;
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case 1: dac_signed_data_16_w(machine->device("lch_pwm"), cur_lch[lch_index_r++]); break;
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case 2: dac_signed_data_16_w(machine->device("rch_pwm"), cur_lch[lch_index_r++]); break;
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case 3: popmessage("Undefined PWM Lch value 3, contact MESSdev"); break;
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}
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lch_index_w = 0;
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}
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@ -2865,7 +2949,14 @@ static TIMER_CALLBACK( _32x_pwm_callback )
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if(rch_index_r < PWM_FIFO_SIZE)
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{
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dac_signed_data_16_w(machine->device("rch_pwm"), cur_rch[rch_index_r++]);
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switch((pwm_ctrl & 0xc) >> 2)
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{
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case 0: rch_index_r++; /*Speaker OFF*/ break;
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case 1: dac_signed_data_16_w(machine->device("rch_pwm"), cur_rch[rch_index_r++]); break;
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case 2: dac_signed_data_16_w(machine->device("lch_pwm"), cur_rch[rch_index_r++]); break;
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case 3: popmessage("Undefined PWM Rch value 3, contact MESSdev"); break;
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}
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rch_index_w = 0;
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}
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@ -3596,7 +3687,177 @@ ADDRESS_MAP_END
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*************************************************************************************************/
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static UINT16* segacd_4meg_prgram; // pointer to SubCPU PrgRAM
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static UINT16 a12000_halt_reset_reg = 0x0000;
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static WRITE16_HANDLER( scd_a12000_halt_reset_w )
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{
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COMBINE_DATA(&a12000_halt_reset_reg);
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if (ACCESSING_BITS_0_7)
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{
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// reset line
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if (a12000_halt_reset_reg&0x0001)
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cputag_set_input_line(space->machine, "segacd_68k", INPUT_LINE_RESET, CLEAR_LINE);
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else
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cputag_set_input_line(space->machine, "segacd_68k", INPUT_LINE_RESET, ASSERT_LINE);
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// request BUS
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if (a12000_halt_reset_reg&0x0002)
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cputag_set_input_line(space->machine, "segacd_68k", INPUT_LINE_HALT, ASSERT_LINE);
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else
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cputag_set_input_line(space->machine, "segacd_68k", INPUT_LINE_HALT, CLEAR_LINE);
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}
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if (ACCESSING_BITS_8_15)
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{
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if (a12000_halt_reset_reg&0x0100)
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{
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// check if it's masked! (irq check function?)
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cputag_set_input_line(space->machine, "segacd_68k", 2, ASSERT_LINE);
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}
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if (a12000_halt_reset_reg&0x8000)
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{
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printf("a12000_halt_reset_reg & 0x8000 set\n"); // irq2 mask?
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}
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}
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}
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static READ16_HANDLER( scd_a12000_halt_reset_r )
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{
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return a12000_halt_reset_reg;
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}
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/********************************************************************************
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MEMORY MODE CONTROL
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- main / sub sides differ!
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********************************************************************************/
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//
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// we might need a delay on the segacd_maincpu_has_ram_access registers, as they actually indicate requests being made
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// so probably don't change instantly...
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//
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static UINT8 segacd_ram_writeprotect_bits;
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static int segacd_ram_mode;
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static int segacd_maincpu_has_ram_access = 0;
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static int segacd_4meg_prgbank = 0; // which bank the MainCPU can see of the SubCPU PrgRAM
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static int segacd_memory_priority_mode = 0;
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static READ16_HANDLER( scd_a12002_memory_mode_r )
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{
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return (segacd_ram_writeprotect_bits << 8) |
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(segacd_4meg_prgbank << 6) |
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(segacd_ram_mode << 2) |
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((segacd_maincpu_has_ram_access^1) << 1) |
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((segacd_maincpu_has_ram_access) << 0);
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}
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static WRITE16_HANDLER( scd_a12002_memory_mode_w )
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{
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printf("scd_a12002_memory_mode_w %04x %04x\n", data, mem_mask);
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if (ACCESSING_BITS_0_7)
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{
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if (data&0x0001) printf("ret bit set (invalid? can't set from main68k?)\n");
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if (data&0x0002)
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{
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printf("dmn set (swap requested)\n"); // give ram to sub?
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// this should take some time?
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segacd_maincpu_has_ram_access = 0;
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}
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if (data&0x0004) printf("mode set (invalid? can't set from main68k?)\n");
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if (data&0x0038) printf("unknown bits set\n");
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//if (data&0x00c0)
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{
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printf("bank set to %02x\n", (data&0x00c0)>>6);
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segacd_4meg_prgbank = (data&0x00c0)>>6;
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}
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}
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if (ACCESSING_BITS_8_15)
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{
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if (data & 0xff00)
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{
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printf("write protect bits set %02x\n", data >> 8);
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}
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segacd_ram_writeprotect_bits = data >> 8;
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}
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}
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// can't read the bank?
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static READ16_HANDLER( segacd_sub_memory_mode_r )
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{
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return (segacd_ram_writeprotect_bits << 8) |
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/*(segacd_4meg_prgbank << 6) | */
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(segacd_memory_priority_mode << 3) |
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(segacd_ram_mode << 2) |
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((segacd_maincpu_has_ram_access^1) << 1) |
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((segacd_maincpu_has_ram_access) << 0);
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}
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static WRITE16_HANDLER( segacd_sub_memory_mode_w )
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{
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printf("segacd_sub_memory_mode_w %04x %04x\n", data, mem_mask);
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if (ACCESSING_BITS_0_7)
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{
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if (data&0x0001)
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{
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printf("ret bit set\n");
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segacd_maincpu_has_ram_access = 1;
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}
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if (data&0x0002) printf("dmn set (swap requested) (invalid, can't be set from sub68k?\n");
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//if (data&0x0004)
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{
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segacd_ram_mode = (data&0x0004)>>2;
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printf("mode set %d\n", segacd_ram_mode);
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}
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//if (data&0x0018)
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{
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segacd_memory_priority_mode = (data&0x0018)>>3;
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printf("priority mode bits set to %d\n", segacd_memory_priority_mode);
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}
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if (data&0x00e0) printf("unknown bits set\n");
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}
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if (ACCESSING_BITS_8_15)
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{
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if (data & 0xff00)
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{
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printf("write protect bits set %02x (invalid, can only be set by main68k)\n", data >> 8);
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}
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}
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}
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/********************************************************************************
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END MEMORY MODE CONTROL
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********************************************************************************/
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static WRITE16_HANDLER( scd_4m_prgbank_ram_w )
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@ -3610,6 +3871,21 @@ static WRITE16_HANDLER( scd_4m_prgbank_ram_w )
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}
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/* Callback when the genesis enters interrupt code */
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static IRQ_CALLBACK(segacd_sub_int_callback)
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{
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if (irqline==2)
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{
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// clear this bit
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a12000_halt_reset_reg &= ~0x0100;
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cputag_set_input_line(device->machine, "segacd_68k", 2, CLEAR_LINE);
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}
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return (0x60+irqline*4)/4; // vector address
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}
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/* main CPU map set up in INIT */
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void segacd_init_main_cpu( running_machine* machine )
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{
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@ -3621,6 +3897,10 @@ void segacd_init_main_cpu( running_machine* machine )
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memory_set_bankptr(space->machine, "scd_4m_prgbank", segacd_4meg_prgram + segacd_4meg_prgbank * 0x20000 );
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memory_install_write16_handler (space, 0x0020000, 0x003ffff, 0, 0, scd_4m_prgbank_ram_w );
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memory_install_readwrite16_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa12000, 0xa12001, 0, 0, scd_a12000_halt_reset_r, scd_a12000_halt_reset_w); // sub-cpu control
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memory_install_readwrite16_handler(cputag_get_address_space(space->machine, "maincpu", ADDRESS_SPACE_PROGRAM), 0xa12002, 0xa12003, 0, 0, scd_a12002_memory_mode_r, scd_a12002_memory_mode_w); // memory mode / write protect
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cpu_set_irq_callback(machine->device("segacd_68k"), segacd_sub_int_callback);
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}
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@ -3631,8 +3911,54 @@ static MACHINE_RESET( segacd )
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}
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static int segacd_redled = 0;
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static int segacd_greenled = 0;
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static int segacd_ready = 1; // actually set 100ms after startup?
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static READ16_HANDLER( segacd_sub_led_ready_r )
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{
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UINT16 retdata = 0x0000;
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if (ACCESSING_BITS_0_7)
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{
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retdata |= segacd_ready;
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}
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if (ACCESSING_BITS_8_15)
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{
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retdata |= segacd_redled << 8;
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retdata |= segacd_greenled << 9;
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}
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return retdata;
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}
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static WRITE16_HANDLER( segacd_sub_led_ready_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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if ((data&0x01) == 0x00)
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{
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// reset CD unit
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}
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}
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if (ACCESSING_BITS_8_15)
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{
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segacd_redled = (data >> 8)&1;
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segacd_greenled = (data >> 9)&1;
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}
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}
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static ADDRESS_MAP_START( segacd_map, ADDRESS_SPACE_PROGRAM, 16 )
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AM_RANGE(0x0000000, 0x007ffff) AM_RAM AM_BASE(&segacd_4meg_prgram)
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AM_RANGE(0x0ff8000 ,0x0ff8001) AM_READWRITE(segacd_sub_led_ready_r, segacd_sub_led_ready_w)
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AM_RANGE(0x0ff8002 ,0x0ff8003) AM_READWRITE(segacd_sub_memory_mode_r, segacd_sub_memory_mode_w)
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ADDRESS_MAP_END
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