PowerVR2: Added SPG control register, used to change pixel clock dynamically [Angelo Salese]

This commit is contained in:
Angelo Salese 2013-08-28 19:30:38 +00:00
parent c0ea7213c6
commit b10071c1da
3 changed files with 29 additions and 9 deletions

View File

@ -51,7 +51,7 @@ DEVICE_ADDRESS_MAP_START(ta_map, 32, powervr2_device)
// c4 = spg_trigger_pos
AM_RANGE(0x00c8, 0x00cb) AM_READWRITE(spg_hblank_int_r, spg_hblank_int_w)
AM_RANGE(0x00cc, 0x00cf) AM_READWRITE(spg_vblank_int_r, spg_vblank_int_w)
// d0 = spg_control
AM_RANGE(0x00d0, 0x00d3) AM_READWRITE(spg_control_r, spg_control_w)
AM_RANGE(0x00d4, 0x00d7) AM_READWRITE(spg_hblank_r, spg_hblank_w)
AM_RANGE(0x00d8, 0x00db) AM_READWRITE(spg_load_r, spg_load_w)
AM_RANGE(0x00dc, 0x00df) AM_READWRITE(spg_vblank_r, spg_vblank_w)
@ -1139,6 +1139,23 @@ WRITE32_MEMBER( powervr2_device::spg_vblank_int_w )
// vbout_timer->adjust(m_screen->time_until_pos((spg_vblank_int >> 16) & 0x3ff));
}
READ32_MEMBER( powervr2_device::spg_control_r )
{
return spg_control;
}
WRITE32_MEMBER( powervr2_device::spg_control_w )
{
COMBINE_DATA(&spg_control);
update_screen_format();
if((spg_control & 0xc0) == 0xc0)
popmessage("SPG undocumented pixel clock mode 11, contact MAME/MESSdev");
if((spg_control & 0xd0) == 0x10)
popmessage("SPG enabled VGA mode with interlace, contact MAME/MESSdev");
}
READ32_MEMBER( powervr2_device::spg_hblank_r )
{
return spg_hblank;
@ -1456,6 +1473,8 @@ WRITE32_MEMBER( powervr2_device::palette_w )
void powervr2_device::update_screen_format()
{
/* 00=VGA 01=NTSC 10=PAL, 11=illegal/undocumented */
const int spg_clks[4] = { 26944080, 13458568, 13462800, 26944080 };
INT32 spg_hsize = spg_load & 0x3ff;
INT32 spg_vsize = (spg_load >> 16) & 0x3ff;
INT32 spg_hbstart = spg_hblank & 0x3ff;
@ -1464,8 +1483,9 @@ void powervr2_device::update_screen_format()
INT32 spg_vbend = (spg_vblank >> 16) & 0x3ff;
INT32 vo_horz_start_pos = vo_startx & 0x3ff;
INT32 vo_vert_start_pos_f1 = vo_starty & 0x3ff;
int pclk = spg_clks[(spg_control >> 6) & 3] * (((spg_control & 0x10) >> 4)+1);
attoseconds_t refresh = HZ_TO_ATTOSECONDS(13458568*2) * spg_hsize * spg_vsize;
attoseconds_t refresh = HZ_TO_ATTOSECONDS(pclk) * spg_hsize * spg_vsize;
rectangle visarea = m_screen->visible_area();
/* FIXME: right visible area calculations aren't known yet*/

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@ -170,6 +170,8 @@ public:
DECLARE_WRITE32_MEMBER( spg_hblank_int_w );
DECLARE_READ32_MEMBER( spg_vblank_int_r );
DECLARE_WRITE32_MEMBER( spg_vblank_int_w );
DECLARE_READ32_MEMBER( spg_control_r );
DECLARE_WRITE32_MEMBER( spg_control_w );
DECLARE_READ32_MEMBER( spg_hblank_r );
DECLARE_WRITE32_MEMBER( spg_hblank_w );
DECLARE_READ32_MEMBER( spg_load_r );
@ -282,7 +284,7 @@ private:
UINT32 fb_r_ctrl, fb_w_ctrl, fb_w_linestride, fb_r_sof1, fb_r_sof2, fb_r_size, fb_w_sof1, fb_w_sof2, fb_x_clip, fb_y_clip;
UINT32 fpu_param_cfg;
UINT32 isp_backgnd_t;
UINT32 spg_hblank_int, spg_vblank_int, spg_hblank, spg_load, spg_vblank, spg_width;
UINT32 spg_hblank_int, spg_vblank_int, spg_control, spg_hblank, spg_load, spg_vblank, spg_width;
UINT32 vo_control, vo_startx, vo_starty;
UINT32 text_control;
UINT32 pal_ram_ctrl;

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@ -306,7 +306,7 @@ READ64_MEMBER(dc_cons_state::dc_pdtra_r )
{
UINT64 out = PCTRA<<32;
out |= PDTRA & ~0x0303;
out |= PDTRA & ~0x0103;
// if both bits are inputs
if (!(PCTRA & 0x5))
@ -552,11 +552,9 @@ static INPUT_PORTS_START( dc )
PORT_DIPSETTING( 0x01, DEF_STR( On ) )
PORT_START("SCREEN_TYPE")
PORT_CONFNAME( 0x03, 0x00, "Connection Type" )
PORT_CONFSETTING( 0x00, "NTSC" )
PORT_CONFSETTING( 0x01, "PAL" )
PORT_CONFSETTING( 0x02, "VGA (0)" )
PORT_CONFSETTING( 0x03, "VGA (1)" )
PORT_CONFNAME( 0x01, 0x00, "Screen Connection Type" )
PORT_CONFSETTING( 0x00, "VGA" )
PORT_CONFSETTING( 0x01, "Composite" )
INPUT_PORTS_END
MACHINE_RESET_MEMBER(dc_cons_state,dc_console)