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https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
PowerVR2: Added SPG control register, used to change pixel clock dynamically [Angelo Salese]
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@ -51,7 +51,7 @@ DEVICE_ADDRESS_MAP_START(ta_map, 32, powervr2_device)
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// c4 = spg_trigger_pos
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AM_RANGE(0x00c8, 0x00cb) AM_READWRITE(spg_hblank_int_r, spg_hblank_int_w)
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AM_RANGE(0x00cc, 0x00cf) AM_READWRITE(spg_vblank_int_r, spg_vblank_int_w)
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// d0 = spg_control
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AM_RANGE(0x00d0, 0x00d3) AM_READWRITE(spg_control_r, spg_control_w)
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AM_RANGE(0x00d4, 0x00d7) AM_READWRITE(spg_hblank_r, spg_hblank_w)
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AM_RANGE(0x00d8, 0x00db) AM_READWRITE(spg_load_r, spg_load_w)
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AM_RANGE(0x00dc, 0x00df) AM_READWRITE(spg_vblank_r, spg_vblank_w)
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@ -1139,6 +1139,23 @@ WRITE32_MEMBER( powervr2_device::spg_vblank_int_w )
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// vbout_timer->adjust(m_screen->time_until_pos((spg_vblank_int >> 16) & 0x3ff));
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}
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READ32_MEMBER( powervr2_device::spg_control_r )
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{
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return spg_control;
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}
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WRITE32_MEMBER( powervr2_device::spg_control_w )
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{
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COMBINE_DATA(&spg_control);
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update_screen_format();
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if((spg_control & 0xc0) == 0xc0)
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popmessage("SPG undocumented pixel clock mode 11, contact MAME/MESSdev");
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if((spg_control & 0xd0) == 0x10)
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popmessage("SPG enabled VGA mode with interlace, contact MAME/MESSdev");
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}
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READ32_MEMBER( powervr2_device::spg_hblank_r )
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{
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return spg_hblank;
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@ -1456,6 +1473,8 @@ WRITE32_MEMBER( powervr2_device::palette_w )
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void powervr2_device::update_screen_format()
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{
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/* 00=VGA 01=NTSC 10=PAL, 11=illegal/undocumented */
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const int spg_clks[4] = { 26944080, 13458568, 13462800, 26944080 };
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INT32 spg_hsize = spg_load & 0x3ff;
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INT32 spg_vsize = (spg_load >> 16) & 0x3ff;
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INT32 spg_hbstart = spg_hblank & 0x3ff;
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@ -1464,8 +1483,9 @@ void powervr2_device::update_screen_format()
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INT32 spg_vbend = (spg_vblank >> 16) & 0x3ff;
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INT32 vo_horz_start_pos = vo_startx & 0x3ff;
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INT32 vo_vert_start_pos_f1 = vo_starty & 0x3ff;
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int pclk = spg_clks[(spg_control >> 6) & 3] * (((spg_control & 0x10) >> 4)+1);
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attoseconds_t refresh = HZ_TO_ATTOSECONDS(13458568*2) * spg_hsize * spg_vsize;
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attoseconds_t refresh = HZ_TO_ATTOSECONDS(pclk) * spg_hsize * spg_vsize;
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rectangle visarea = m_screen->visible_area();
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/* FIXME: right visible area calculations aren't known yet*/
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@ -170,6 +170,8 @@ public:
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DECLARE_WRITE32_MEMBER( spg_hblank_int_w );
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DECLARE_READ32_MEMBER( spg_vblank_int_r );
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DECLARE_WRITE32_MEMBER( spg_vblank_int_w );
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DECLARE_READ32_MEMBER( spg_control_r );
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DECLARE_WRITE32_MEMBER( spg_control_w );
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DECLARE_READ32_MEMBER( spg_hblank_r );
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DECLARE_WRITE32_MEMBER( spg_hblank_w );
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DECLARE_READ32_MEMBER( spg_load_r );
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@ -282,7 +284,7 @@ private:
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UINT32 fb_r_ctrl, fb_w_ctrl, fb_w_linestride, fb_r_sof1, fb_r_sof2, fb_r_size, fb_w_sof1, fb_w_sof2, fb_x_clip, fb_y_clip;
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UINT32 fpu_param_cfg;
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UINT32 isp_backgnd_t;
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UINT32 spg_hblank_int, spg_vblank_int, spg_hblank, spg_load, spg_vblank, spg_width;
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UINT32 spg_hblank_int, spg_vblank_int, spg_control, spg_hblank, spg_load, spg_vblank, spg_width;
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UINT32 vo_control, vo_startx, vo_starty;
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UINT32 text_control;
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UINT32 pal_ram_ctrl;
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@ -306,7 +306,7 @@ READ64_MEMBER(dc_cons_state::dc_pdtra_r )
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{
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UINT64 out = PCTRA<<32;
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out |= PDTRA & ~0x0303;
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out |= PDTRA & ~0x0103;
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// if both bits are inputs
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if (!(PCTRA & 0x5))
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@ -552,11 +552,9 @@ static INPUT_PORTS_START( dc )
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PORT_DIPSETTING( 0x01, DEF_STR( On ) )
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PORT_START("SCREEN_TYPE")
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PORT_CONFNAME( 0x03, 0x00, "Connection Type" )
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PORT_CONFSETTING( 0x00, "NTSC" )
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PORT_CONFSETTING( 0x01, "PAL" )
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PORT_CONFSETTING( 0x02, "VGA (0)" )
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PORT_CONFSETTING( 0x03, "VGA (1)" )
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PORT_CONFNAME( 0x01, 0x00, "Screen Connection Type" )
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PORT_CONFSETTING( 0x00, "VGA" )
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PORT_CONFSETTING( 0x01, "Composite" )
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INPUT_PORTS_END
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MACHINE_RESET_MEMBER(dc_cons_state,dc_console)
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