mirror of
https://github.com/holub/mame
synced 2025-04-26 18:23:08 +03:00
Added GRCG capabilities
This commit is contained in:
Angelo Salese
parent
2f85f85034
commit
b11c087619
@ -342,11 +342,15 @@ public:
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UINT8 m_rom_bank;
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UINT8 m_fdc_ctrl;
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UINT32 m_ram_size;
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UINT8 m_ex_video_ff[4];
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UINT8 m_ex_video_ff[128];
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struct {
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UINT8 pal_entry;
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UINT8 r[16],g[16],b[16];
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}m_analog16;
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struct {
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UINT8 mode;
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UINT8 tile[4], tile_index;
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}m_grcg;
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/* PC9821 specific */
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UINT8 m_analog256,m_analog256e;
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@ -377,6 +381,8 @@ public:
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DECLARE_WRITE8_MEMBER(pc9801_video_ff_w);
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DECLARE_READ8_MEMBER(pc9801_70_r);
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DECLARE_WRITE8_MEMBER(pc9801_70_w);
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DECLARE_READ8_MEMBER(pc9801rs_70_r);
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DECLARE_WRITE8_MEMBER(pc9801rs_70_w);
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DECLARE_READ8_MEMBER(pc9801_sasi_r);
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DECLARE_WRITE8_MEMBER(pc9801_sasi_w);
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DECLARE_READ8_MEMBER(pc9801_a0_r);
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@ -391,8 +397,8 @@ public:
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DECLARE_WRITE8_MEMBER(pc9801_gvram_w);
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DECLARE_READ8_MEMBER(pc9801_mouse_r);
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DECLARE_WRITE8_MEMBER(pc9801_mouse_w);
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// DECLARE_READ8_MEMBER(pc9801rs_gvram_r);
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DECLARE_WRITE8_MEMBER(pc9801rs_gvram_w);
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DECLARE_READ8_MEMBER(pc9801rs_grcg_r);
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DECLARE_WRITE8_MEMBER(pc9801rs_grcg_w);
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DECLARE_READ8_MEMBER(pc9801_opn_r);
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DECLARE_WRITE8_MEMBER(pc9801_opn_w);
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DECLARE_READ8_MEMBER(pc9801rs_wram_r);
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@ -533,6 +539,7 @@ public:
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// DECLARE_WRITE_LINE_MEMBER(pc9801rs_fdc_irq);
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void pc9801_fdc_2hd_update_ready(floppy_image_device *, int);
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inline UINT32 m_calc_grcg_addr(int i,UINT32 offset);
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};
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@ -1059,7 +1066,6 @@ READ8_MEMBER(pc9801_state::pc9801_70_r)
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WRITE8_MEMBER(pc9801_state::pc9801_70_w)
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{
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if((offset & 1) == 0)
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{
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printf("Write to display register [%02x] %02x\n",offset+0x70,data);
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@ -1370,9 +1376,62 @@ WRITE8_MEMBER(pc9801_state::pc9801_gvram_w)
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m_video_ram_2[offset+0x08000+m_vram_bank*0x20000] = data;
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}
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WRITE8_MEMBER(pc9801_state::pc9801rs_gvram_w)
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inline UINT32 pc9801_state::m_calc_grcg_addr(int i,UINT32 offset)
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{
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return (offset) + (((i+1)*0x8000) & 0x1ffff) + (m_vram_bank*0x20000);
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}
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READ8_MEMBER(pc9801_state::pc9801rs_grcg_r)
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{
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UINT8 res;
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if((m_grcg.mode & 0x80) == 0 || (m_grcg.mode & 0x40))
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res = m_video_ram_2[offset+0+m_vram_bank*0x20000];
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else
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{
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int i;
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res = 0;
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for(i=0;i<4;i++)
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{
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if((m_grcg.mode & 1 << i) == 0)
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res |= (m_video_ram_2[m_calc_grcg_addr(i,offset)] ^ m_grcg.tile[i]);
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}
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res ^= 0xff;
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}
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return res;
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}
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WRITE8_MEMBER(pc9801_state::pc9801rs_grcg_w)
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{
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if((m_grcg.mode & 0x80) == 0)
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m_video_ram_2[offset+0+m_vram_bank*0x20000] = data;
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else
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{
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int i;
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if(m_grcg.mode & 0x40) // RMW
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{
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for(i=0;i<4;i++)
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{
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if((m_grcg.mode & 1 << i) == 0)
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{
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m_video_ram_2[m_calc_grcg_addr(i,offset)] &= ~data;
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m_video_ram_2[m_calc_grcg_addr(i,offset)] |= m_grcg.tile[i] & data;
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}
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}
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}
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else // TDW
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{
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for(i=0;i<4;i++)
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{
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if((m_grcg.mode & 1 << i) == 0)
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m_video_ram_2[m_calc_grcg_addr(i,offset)] = m_grcg.tile[i];
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}
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}
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}
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}
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@ -1542,6 +1601,43 @@ READ8_MEMBER(pc9801_state::pc9801rs_30_r)
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return pc9801_30_r(space,offset);
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}
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READ8_MEMBER(pc9801_state::pc9801rs_70_r)
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{
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if(offset == 0xc)
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{
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printf("GRCG mode R\n");
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return 0xff;
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}
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else if(offset == 0x0e)
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{
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printf("GRCG tile R\n");
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return 0xff;
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}
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return pc9801_70_r(space,offset);;
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}
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WRITE8_MEMBER(pc9801_state::pc9801rs_70_w)
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{
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if(offset == 0xc)
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{
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// printf("%02x GRCG MODE\n",data);
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m_grcg.mode = data;
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m_grcg.tile_index = 0;
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return;
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}
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else if(offset == 0x0e)
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{
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// printf("%02x GRCG TILE %02x\n",data,m_grcg.tile_index);
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m_grcg.tile[m_grcg.tile_index] = data;
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m_grcg.tile_index ++;
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m_grcg.tile_index &= 3;
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return;
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}
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pc9801_70_w(space,offset,data);
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}
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READ8_MEMBER(pc9801_state::pc9801rs_memory_r)
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{
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if(m_gate_a20 == 0)
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@ -1551,6 +1647,7 @@ READ8_MEMBER(pc9801_state::pc9801rs_memory_r)
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else if(offset >= 0x000a0000 && offset <= 0x000a3fff) { return pc9801_tvram_r(space,offset-0xa0000); }
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else if(offset >= 0x000a4000 && offset <= 0x000a4fff) { return pc9801rs_knjram_r(space,offset & 0xfff); }
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else if(offset >= 0x000a8000 && offset <= 0x000bffff) { return pc9801_gvram_r(space,offset-0xa8000); }
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else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { return pc9801rs_grcg_r(space,offset & 0x7fff); }
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else if(offset >= 0x000e0000 && offset <= 0x000fffff) { return pc9801rs_ipl_r(space,offset & 0x1ffff); }
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else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { return pc9801rs_ex_wram_r(space,offset-0x00100000); }
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else if(offset >= 0xfffe0000 && offset <= 0xffffffff) { return pc9801rs_ipl_r(space,offset & 0x1ffff); }
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@ -1569,7 +1666,7 @@ WRITE8_MEMBER(pc9801_state::pc9801rs_memory_w)
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else if(offset >= 0x000a0000 && offset <= 0x000a3fff) { pc9801_tvram_w(space,offset-0xa0000,data); }
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else if(offset >= 0x000a4000 && offset <= 0x000a4fff) { pc9801rs_knjram_w(space,offset & 0xfff,data); }
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else if(offset >= 0x000a8000 && offset <= 0x000bffff) { pc9801_gvram_w(space,offset-0xa8000,data); }
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else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { pc9801rs_gvram_w(space,offset & 0x7fff,data); }
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else if(offset >= 0x000e0000 && offset <= 0x000e7fff) { pc9801rs_grcg_w(space,offset & 0x7fff,data); }
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else if(offset >= 0x00100000 && offset <= 0x00100000+m_ram_size-1) { pc9801rs_ex_wram_w(space,offset-0x00100000,data); }
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//else
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// printf("%08x %08x\n",offset,data);
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@ -1686,11 +1783,9 @@ WRITE8_MEMBER(pc9801_state::pc9801rs_video_ff_w)
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if(offset == 2)
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{
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if((data & 0xf8) == 0)
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{
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m_ex_video_ff[(data & 0x6) >> 1] = data & 1;
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m_ex_video_ff[(data & 0xfe) >> 1] = data & 1;
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if(1)
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if(0)
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{
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static const char *const ex_video_ff_regnames[] =
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{
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@ -1702,9 +1797,9 @@ WRITE8_MEMBER(pc9801_state::pc9801rs_video_ff_w)
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printf("Write to extend video FF register %s -> %02x\n",ex_video_ff_regnames[(data & 0x06) >> 1],data & 1);
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}
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else
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printf("Write to extend video FF register %02x\n",data);
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}
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//else
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// printf("Write to extend video FF register %02x\n",data);
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return;
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}
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@ -1760,7 +1855,7 @@ static ADDRESS_MAP_START( pc9801rs_io, AS_IO, 32, pc9801_state )
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AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r, pc9801_60_w, 0xffffffff) //upd7220 character ports / <undefined>
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AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffffffff)
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AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0xffffffff) //mode FF / <undefined>
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AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r, pc9801_70_w, 0xffffffff) //display registers "GRCG" / i8253 pit
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AM_RANGE(0x0070, 0x007f) AM_READWRITE8(pc9801rs_70_r, pc9801rs_70_w, 0xffffffff) //display registers "GRCG" / i8253 pit
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AM_RANGE(0x0080, 0x0083) AM_READWRITE8(pc9801_sasi_r, pc9801_sasi_w, 0xffffffff) //HDD SASI interface / <undefined>
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AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r, pc9801rs_2hd_w, 0xffffffff)
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AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r, pc9801rs_a0_w, 0xffffffff) //upd7220 bitmap ports / display registers
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@ -1818,7 +1913,7 @@ static ADDRESS_MAP_START( pc9801ux_io, AS_IO, 16, pc9801_state )
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AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r, pc9801_60_w, 0xffff) //upd7220 character ports / <undefined>
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AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffff)
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AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9801rs_video_ff_w,0xffff) //mode FF / <undefined>
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AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r, pc9801_70_w, 0xffff) //display registers "GRCG" / i8253 pit
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AM_RANGE(0x0070, 0x007f) AM_READWRITE8(pc9801rs_70_r, pc9801rs_70_w, 0xffff) //display registers "GRCG" / i8253 pit
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AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r, pc9801rs_2hd_w, 0xffff)
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AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9801_a0_r, pc9801rs_a0_w, 0xffff) //upd7220 bitmap ports / display registers
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AM_RANGE(0x00bc, 0x00bf) AM_READWRITE8(pc9810rs_fdc_ctrl_r,pc9810rs_fdc_ctrl_w,0xffff)
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@ -2089,7 +2184,7 @@ static ADDRESS_MAP_START( pc9821_io, AS_IO, 32, pc9801_state )
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AM_RANGE(0x0060, 0x0063) AM_READWRITE8(pc9801_60_r, pc9801_60_w, 0xffffffff) //upd7220 character ports / <undefined>
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AM_RANGE(0x0064, 0x0067) AM_WRITE8(pc9801_vrtc_mask_w, 0xffffffff)
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AM_RANGE(0x0068, 0x006b) AM_WRITE8(pc9821_video_ff_w, 0xffffffff) //mode FF / <undefined>
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AM_RANGE(0x0070, 0x007b) AM_READWRITE8(pc9801_70_r, pc9801_70_w, 0xffffffff) //display registers "GRCG" / i8253 pit
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AM_RANGE(0x0070, 0x007f) AM_READWRITE8(pc9801rs_70_r, pc9801rs_70_w, 0xffffffff) //display registers "GRCG" / i8253 pit
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// AM_RANGE(0x0080, 0x0083) SASI interface / <undefined>
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AM_RANGE(0x0090, 0x0097) AM_READWRITE8(pc9801rs_2hd_r, pc9801rs_2hd_w, 0xffffffff)
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AM_RANGE(0x00a0, 0x00af) AM_READWRITE8(pc9821_a0_r, pc9821_a0_w, 0xffffffff) //upd7220 bitmap ports / display registers
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