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aristmk5: hooked-up EEPROMs, UARTs and some inputs also fixed video dma when vidstart != 0
This commit is contained in:
Sandro Ronco
parent
4cb5712cd2
commit
b15200a65f
@ -173,24 +173,33 @@
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#include "includes/archimds.h"
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#include "cpu/arm/arm.h"
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#include "machine/watchdog.h"
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#include "machine/eepromser.h"
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#include "machine/ins8250.h"
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#include "sound/volt_reg.h"
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class aristmk5_state : public archimedes_state
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{
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public:
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aristmk5_state(const machine_config &mconfig, device_type type, const char *tag)
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: archimedes_state(mconfig, type, tag) { }
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: archimedes_state(mconfig, type, tag)
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, m_eeprom(*this, "eeprom%d", 0)
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{ }
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emu_timer *m_mk5_2KHz_timer;
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emu_timer *m_mk5_VSYNC_timer;
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uint8_t m_ext_latch;
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uint8_t m_flyback;
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required_device_array<eeprom_serial_93cxx_device, 2> m_eeprom;
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DECLARE_WRITE32_MEMBER(Ns5w48);
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DECLARE_READ32_MEMBER(Ns5x58);
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DECLARE_READ32_MEMBER(mk5_ioc_r);
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DECLARE_WRITE32_MEMBER(mk5_ioc_w);
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DECLARE_READ32_MEMBER(Ns5r50);
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DECLARE_WRITE32_MEMBER(sram_banksel_w);
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DECLARE_WRITE32_MEMBER(eeprom_w);
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DECLARE_READ32_MEMBER(eeprom_r);
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DECLARE_DRIVER_INIT(aristmk5);
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virtual void machine_start() override;
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virtual void machine_reset() override;
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@ -347,6 +356,28 @@ READ32_MEMBER(aristmk5_state::Ns5r50)
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return 0xf5; // checked inside the CPU check, unknown meaning
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}
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READ32_MEMBER(aristmk5_state::eeprom_r)
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{
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uint8_t data = 0x00;
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if (m_eeprom[0]->do_read() && m_eeprom[1]->do_read())
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data |= 0x04;
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return data;
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}
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WRITE32_MEMBER(aristmk5_state::eeprom_w)
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{
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if (ACCESSING_BITS_0_7)
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{
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m_eeprom[0]->cs_write(BIT(data, 5));
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m_eeprom[1]->cs_write(BIT(data, 6));
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m_eeprom[0]->di_write(BIT(data, 3));
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m_eeprom[1]->di_write(BIT(data, 3));
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m_eeprom[0]->clk_write(BIT(data, 4));
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m_eeprom[1]->clk_write(BIT(data, 4));
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}
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}
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WRITE32_MEMBER(aristmk5_state::sram_banksel_w)
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{
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/*
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@ -413,8 +444,23 @@ static ADDRESS_MAP_START( aristmk5_map, AS_PROGRAM, 32, aristmk5_state )
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/* MK-5 overrides */
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AM_RANGE(0x03010420, 0x03010423) AM_WRITE(sram_banksel_w) // SRAM bank select write
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AM_RANGE(0x03010450, 0x03010453) AM_WRITE(eeprom_w)
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AM_RANGE(0x03010800, 0x03010803) AM_READ(eeprom_r)
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// AM_RANGE(0x0301049c, 0x0301051f) AM_DEVREADWRITE_LEGACY("eeprom", eeprom_r, eeprom_w) // eeprom ???
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AM_RANGE(0x03010580, 0x03010583) AM_READ_PORT("P3")
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AM_RANGE(0x03012000, 0x03012003) AM_READ_PORT("P1")
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AM_RANGE(0x03012010, 0x03012013) AM_READ_PORT("P2")
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AM_RANGE(0x03012200, 0x03012203) AM_READ_PORT("DSW1")
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AM_RANGE(0x03012210, 0x03012213) AM_READ_PORT("DSW2")
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AM_RANGE(0x03010480, 0x0301049f) AM_DEVREADWRITE8("uart_0a", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03010500, 0x0301051f) AM_DEVREADWRITE8("uart_0b", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03010600, 0x0301061f) AM_DEVREADWRITE8("uart_1a", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03010680, 0x0301069f) AM_DEVREADWRITE8("uart_1b", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03012100, 0x0301211f) AM_DEVREADWRITE8("uart_2a", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03012140, 0x0301215f) AM_DEVREADWRITE8("uart_2b", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03012300, 0x0301231f) AM_DEVREADWRITE8("uart_3a", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03012340, 0x0301235f) AM_DEVREADWRITE8("uart_3b", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03010810, 0x03010813) AM_DEVREADWRITE("watchdog", watchdog_timer_device, reset32_r, reset32_w) //MK-5 specific, watchdog
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// System Startup Code Enabled protection appears to be located at 0x3010400 - 0x30104ff
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@ -439,8 +485,23 @@ static ADDRESS_MAP_START( aristmk5_drame_map, AS_PROGRAM, 32, aristmk5_state )
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/* MK-5 overrides */
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AM_RANGE(0x03010420, 0x03010423) AM_WRITE(sram_banksel_w) // SRAM bank select write
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AM_RANGE(0x03010450, 0x03010453) AM_WRITE(eeprom_w)
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AM_RANGE(0x03010800, 0x03010803) AM_READ(eeprom_r)
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// AM_RANGE(0x0301049c, 0x0301051f) AM_DEVREADWRITE_LEGACY("eeprom", eeprom_r, eeprom_w) // eeprom ???
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AM_RANGE(0x03010580, 0x03010583) AM_READ_PORT("P3")
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AM_RANGE(0x03012000, 0x03012003) AM_READ_PORT("P1")
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AM_RANGE(0x03012010, 0x03012013) AM_READ_PORT("P2")
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AM_RANGE(0x03012200, 0x03012203) AM_READ_PORT("DSW1")
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AM_RANGE(0x03012210, 0x03012213) AM_READ_PORT("DSW2")
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AM_RANGE(0x03010480, 0x0301049f) AM_DEVREADWRITE8("uart_0a", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03010500, 0x0301051f) AM_DEVREADWRITE8("uart_0b", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03010600, 0x0301061f) AM_DEVREADWRITE8("uart_1a", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03010680, 0x0301069f) AM_DEVREADWRITE8("uart_1b", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03012100, 0x0301211f) AM_DEVREADWRITE8("uart_2a", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03012140, 0x0301215f) AM_DEVREADWRITE8("uart_2b", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03012300, 0x0301231f) AM_DEVREADWRITE8("uart_3a", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03012340, 0x0301235f) AM_DEVREADWRITE8("uart_3b", ins8250_uart_device, ins8250_r, ins8250_w, 0x000000ff)
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AM_RANGE(0x03010810, 0x03010813) AM_DEVREADWRITE("watchdog", watchdog_timer_device, reset32_r, reset32_w) //MK-5 specific, watchdog
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// System Startup Code Enabled protection appears to be located at 0x3010400 - 0x30104ff
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@ -468,6 +529,56 @@ static INPUT_PORTS_START( aristmk5 )
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PORT_CONFSETTING( 0x01, "Set Chip v4.4 Mode" )
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PORT_CONFSETTING( 0x02, "Clear Chip Mode" )
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PORT_CONFSETTING( 0x03, "Game Mode" )
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PORT_START("DSW1")
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PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "DSW1:1")
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PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "DSW1:2")
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PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "DSW1:3")
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PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "DSW1:4")
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PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "DSW1:5")
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PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "DSW1:6")
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PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "DSW1:7")
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PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "DSW1:8")
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PORT_START("DSW2")
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PORT_DIPUNKNOWN_DIPLOC(0x01, 0x01, "DSW2:1")
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PORT_DIPUNKNOWN_DIPLOC(0x02, 0x02, "DSW2:2")
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PORT_DIPUNKNOWN_DIPLOC(0x04, 0x04, "DSW2:3")
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PORT_DIPUNKNOWN_DIPLOC(0x08, 0x08, "DSW2:4")
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PORT_DIPUNKNOWN_DIPLOC(0x10, 0x10, "DSW2:5")
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PORT_DIPUNKNOWN_DIPLOC(0x20, 0x20, "DSW2:6")
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PORT_DIPUNKNOWN_DIPLOC(0x40, 0x40, "DSW2:7")
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PORT_DIPUNKNOWN_DIPLOC(0x80, 0x80, "DSW2:8")
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PORT_START("P1")
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PORT_BIT(0x00000001, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_Q)
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PORT_BIT(0x00000002, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_W)
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PORT_BIT(0x00000004, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_E)
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PORT_BIT(0x00000008, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_R)
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PORT_BIT(0x00000010, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_T)
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PORT_BIT(0x00000020, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_Y)
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PORT_BIT(0x00000040, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_U)
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PORT_BIT(0x00000080, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_I)
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PORT_START("P2")
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PORT_BIT(0x00000001, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_A)
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PORT_BIT(0x00000002, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_S)
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PORT_BIT(0x00000004, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_D)
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PORT_BIT(0x00000008, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_F)
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PORT_BIT(0x00000010, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_G)
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PORT_BIT(0x00000020, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_H)
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PORT_BIT(0x00000040, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_J)
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PORT_BIT(0x00000080, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_K)
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PORT_START("P3")
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PORT_BIT(0x00000001, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_Z)
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PORT_BIT(0x00000002, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_X)
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PORT_BIT(0x00000004, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_C)
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PORT_BIT(0x00000008, IP_ACTIVE_HIGH, IPT_SERVICE)
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PORT_BIT(0x00000010, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_V)
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PORT_BIT(0x00000020, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_B) // Bill acceptor door
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PORT_BIT(0x00000040, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_N) // Main door
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PORT_BIT(0x00000080, IP_ACTIVE_HIGH, IPT_KEYPAD) PORT_CODE(KEYCODE_M) // Cashbox door
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INPUT_PORTS_END
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DRIVER_INIT_MEMBER(aristmk5_state,aristmk5)
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@ -545,6 +656,33 @@ static MACHINE_CONFIG_START( aristmk5, aristmk5_state )
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MCFG_PALETTE_ADD("palette", 0x200)
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MCFG_EEPROM_SERIAL_93C56_ADD("eeprom0")
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MCFG_EEPROM_SERIAL_93C56_ADD("eeprom1")
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// TL16C452FN U71
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MCFG_DEVICE_ADD("uart_0a", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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MCFG_DEVICE_ADD("uart_0b", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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// TL16C452FN U72
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MCFG_DEVICE_ADD("uart_1a", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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MCFG_DEVICE_ADD("uart_1b", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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// COMM port 4 - 5
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MCFG_DEVICE_ADD("uart_2a", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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MCFG_DEVICE_ADD("uart_2b", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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// COMM port 6 - 7
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MCFG_DEVICE_ADD("uart_3a", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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MCFG_DEVICE_ADD("uart_3b", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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MCFG_SPEAKER_STANDARD_MONO("speaker")
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MCFG_SOUND_ADD("dac0", DAC_16BIT_R2R_TWOS_COMPLEMENT, 0) MCFG_SOUND_ROUTE(0, "speaker", 0.1) // unknown DAC
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MCFG_SOUND_ADD("dac1", DAC_16BIT_R2R_TWOS_COMPLEMENT, 0) MCFG_SOUND_ROUTE(0, "speaker", 0.1) // unknown DAC
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@ -587,6 +725,33 @@ static MACHINE_CONFIG_START( aristmk5_usa, aristmk5_state )
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MCFG_PALETTE_ADD("palette", 0x200)
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MCFG_EEPROM_SERIAL_93C56_ADD("eeprom0")
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MCFG_EEPROM_SERIAL_93C56_ADD("eeprom1")
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// TL16C452FN U71
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MCFG_DEVICE_ADD("uart_0a", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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MCFG_DEVICE_ADD("uart_0b", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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// TL16C452FN U72
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MCFG_DEVICE_ADD("uart_1a", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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MCFG_DEVICE_ADD("uart_1b", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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// COMM port 4 - 5
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MCFG_DEVICE_ADD("uart_2a", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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MCFG_DEVICE_ADD("uart_2b", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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// COMM port 6 - 7
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MCFG_DEVICE_ADD("uart_3a", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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MCFG_DEVICE_ADD("uart_3b", NS16450, MASTER_CLOCK / 9)
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// MCFG_INS8250_OUT_INT_CB(WRITELINE(aristmk5_state, uart_irq_callback))
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MCFG_SPEAKER_STANDARD_MONO("speaker")
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MCFG_SOUND_ADD("dac0", DAC_16BIT_R2R_TWOS_COMPLEMENT, 0) MCFG_SOUND_ROUTE(0, "speaker", 0.1) // unknown DAC
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MCFG_SOUND_ADD("dac1", DAC_16BIT_R2R_TWOS_COMPLEMENT, 0) MCFG_SOUND_ROUTE(0, "speaker", 0.1) // unknown DAC
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@ -624,7 +789,9 @@ MACHINE_CONFIG_END
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ROM_REGION( 0x600, "gals", 0 ) \
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ROM_LOAD( "a562837.u36", 0x000000, 0x000157, CRC(1f269234) SHA1(29940dd50fb55c632935f62ff44ca724379c7a43) ) \
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ROM_LOAD( "a562838.u65", 0x000200, 0x000157, CRC(f2f3c40a) SHA1(b795dfa5cc4e8127c3f3a0906664910d1325ec92) ) \
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ROM_LOAD( "a562840.u22", 0x000400, 0x000157, CRC(941d4cdb) SHA1(1ca091fba69e92f262dbb3d40f515703c8981793) )
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ROM_LOAD( "a562840.u22", 0x000400, 0x000157, CRC(941d4cdb) SHA1(1ca091fba69e92f262dbb3d40f515703c8981793) ) \
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ROM_REGION16_BE( 0x100, "eeprom0", ROMREGION_ERASEFF ) \
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ROM_REGION16_BE( 0x100, "eeprom1", ROMREGION_ERASEFF ) \
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ROM_START( aristmk5 )
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ARISTOCRAT_MK5_BIOS
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@ -133,7 +133,7 @@ void archimedes_state::vidc_video_tick()
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size = m_vidc_vidend-m_vidc_vidstart+0x10;
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offset_ptr = m_vidc_vidstart+m_vidc_vidinit;
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offset_ptr = m_vidc_vidinit;
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if(offset_ptr >= m_vidc_vidend+0x10) // TODO: correct?
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offset_ptr = m_vidc_vidstart;
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@ -1055,7 +1055,7 @@ WRITE32_MEMBER(archimedes_state::archimedes_memc_w)
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{
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case 0: /* video init */
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m_cursor_enabled = false;
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m_vidc_vidinit = ((data>>2)&0x7fff)*16;
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m_vidc_vidinit = 0x2000000 | ((data>>2)&0x7fff)*16;
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//printf("MEMC: VIDINIT %08x\n",m_vidc_vidinit);
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break;
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