mirror of
https://github.com/holub/mame
synced 2025-04-23 00:39:36 +03:00
naomi video: Pretend-modernize the powervr2 [O. Galibert]
This commit is contained in:
Olivier Galibert
parent
d19ce43601
commit
b15438cbde
2
.gitattributes
vendored
2
.gitattributes
vendored
@ -5349,7 +5349,6 @@ src/mame/video/darkmist.c svneol=native#text/plain
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src/mame/video/darkseal.c svneol=native#text/plain
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src/mame/video/dassault.c svneol=native#text/plain
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src/mame/video/dbz.c svneol=native#text/plain
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src/mame/video/dc.c svneol=native#text/plain
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src/mame/video/dcheese.c svneol=native#text/plain
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src/mame/video/dcon.c svneol=native#text/plain
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src/mame/video/dday.c svneol=native#text/plain
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@ -5682,6 +5681,7 @@ src/mame/video/popeye.c svneol=native#text/plain
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src/mame/video/popper.c svneol=native#text/plain
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src/mame/video/portrait.c svneol=native#text/plain
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src/mame/video/powerins.c svneol=native#text/plain
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src/mame/video/powervr2.c svneol=native#text/plain
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src/mame/video/powervr2.h svneol=native#text/plain
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src/mame/video/ppu2c0x.c svneol=native#text/plain
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src/mame/video/ppu2c0x.h svneol=native#text/plain
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@ -566,8 +566,10 @@ protected:
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static delegate_generic_class *late_bind_helper(delegate_late_bind &object)
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{
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_FunctionClass *result = dynamic_cast<_FunctionClass *>(&object);
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if (result == NULL)
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if (result == NULL) {
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abort();
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throw binding_type_exception(typeid(_FunctionClass), typeid(object));
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}
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return reinterpret_cast<delegate_generic_class *>(result);
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}
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@ -232,6 +232,7 @@ void devcb2_read_base::resolve()
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}
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catch (binding_type_exception &binderr)
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{
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abort();
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throw emu_fatalerror("Error performing a late bind of type %s to %s\n", binderr.m_actual_type.name(), binderr.m_target_type.name());
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}
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}
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@ -449,6 +450,7 @@ void devcb2_write_base::resolve()
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}
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catch (binding_type_exception &binderr)
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{
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abort();
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throw emu_fatalerror("Error performing a late bind of type %s to %s\n", binderr.m_actual_type.name(), binderr.m_target_type.name());
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}
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}
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@ -1519,36 +1519,6 @@ WRITE64_MEMBER(naomi_state::eeprom_93c46a_w )
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* Common address map for Naomi 1, Naomi GD-Rom, Naomi 2, Atomiswave ...
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*/
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// SB_LMMODE0
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WRITE64_MEMBER(naomi_state::ta_texture_directpath0_w )
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{
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int mode = pvrctrl_regs[SB_LMMODE0]&1;
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if (mode&1)
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{
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printf("ta_texture_directpath0_w 32-bit access!\n");
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COMBINE_DATA(&dc_framebuffer_ram[offset]);
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}
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else
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{
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COMBINE_DATA(&dc_texture_ram[offset]);
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}
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}
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// SB_LMMODE1
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WRITE64_MEMBER(naomi_state::ta_texture_directpath1_w )
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{
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int mode = pvrctrl_regs[SB_LMMODE1]&1;
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if (mode&1)
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{
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printf("ta_texture_directpath1_w 32-bit access!\n");
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COMBINE_DATA(&dc_framebuffer_ram[offset]);
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}
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else
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{
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COMBINE_DATA(&dc_texture_ram[offset]);
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}
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}
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/*
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* Naomi 1 address map
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@ -1564,8 +1534,8 @@ static ADDRESS_MAP_START( naomi_map, AS_PROGRAM, 64, naomi_state )
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AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", naomi_board, submap, U64(0x0000ffff0000ffff) )
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AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
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AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
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AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_READWRITE(pvr_ctrl_r, pvr_ctrl_w )
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AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_READWRITE_LEGACY(pvr_ta_r, pvr_ta_w )
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AM_RANGE(0x005f7c00, 0x005f7cff) AM_MIRROR(0x02000000) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w)
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AM_RANGE(0x005f8000, 0x005f9fff) AM_MIRROR(0x02000000) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w )
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AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w )
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AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
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AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE(dc_rtc_r, dc_rtc_w )
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@ -1586,11 +1556,11 @@ static ADDRESS_MAP_START( naomi_map, AS_PROGRAM, 64, naomi_state )
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AM_RANGE(0x0c000000, 0x0dffffff) AM_MIRROR(0xa2000000) AM_RAM AM_SHARE("dc_ram")
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/* Area 4 */
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AM_RANGE(0x10000000, 0x107fffff) AM_MIRROR(0x02000000) AM_WRITE_LEGACY(ta_fifo_poly_w )
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AM_RANGE(0x10800000, 0x10ffffff) AM_MIRROR(0x02000000) AM_WRITE_LEGACY(ta_fifo_yuv_w )
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AM_RANGE(0x11000000, 0x11ffffff) AM_WRITE(ta_texture_directpath0_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue)
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AM_RANGE(0x10000000, 0x107fffff) AM_MIRROR(0x02000000) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_poly_w)
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AM_RANGE(0x10800000, 0x10ffffff) AM_MIRROR(0x02000000) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_yuv_w)
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AM_RANGE(0x11000000, 0x11ffffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath0_w) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue)
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/* 0x12000000 -0x13ffffff Mirror area of 0x10000000 -0x11ffffff */
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AM_RANGE(0x13000000, 0x13ffffff) AM_WRITE(ta_texture_directpath1_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)
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AM_RANGE(0x13000000, 0x13ffffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath1_w) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)
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/* Area 5 */
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//AM_RANGE(0x14000000, 0x17ffffff) AM_NOP // MPX Ext.
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@ -1616,8 +1586,8 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, naomi_state )
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AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", naomi_board, submap, U64(0x0000ffff0000ffff) )
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AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
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AM_RANGE(0x005f7800, 0x005f78ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
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AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE(pvr_ctrl_r, pvr_ctrl_w )
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AM_RANGE(0x005f8000, 0x005f9fff) AM_READWRITE_LEGACY(pvr_ta_r, pvr_ta_w )
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AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w)
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AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w )
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AM_RANGE(0x00600000, 0x006007ff) AM_MIRROR(0x02000000) AM_READWRITE(dc_modem_r, dc_modem_w )
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AM_RANGE(0x00700000, 0x00707fff) AM_MIRROR(0x02000000) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
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AM_RANGE(0x00710000, 0x0071000f) AM_MIRROR(0x02000000) AM_READWRITE(dc_rtc_r, dc_rtc_w )
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@ -1628,8 +1598,8 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, naomi_state )
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AM_RANGE(0x0103ff00, 0x0103ffff) AM_MIRROR(0x02000000) AM_READWRITE(naomi_unknown1_r, naomi_unknown1_w ) // bios uses it, actual start and end addresses not known
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// AM_RANGE(0x025f6800, 0x025f69ff) AM_READWRITE_LEGACY(dc_sysctrl_r, dc_sysctrl_w ) // second PVR DMA!
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// AM_RANGE(0x025f7c00, 0x025f7cff) AM_READWRITE(pvr_ctrl_r, pvr_ctrl_w )
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AM_RANGE(0x025f8000, 0x025f9fff) AM_READWRITE_LEGACY(pvr2_ta_r, pvr2_ta_w )
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// AM_RANGE(0x025f7c00, 0x025f7cff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w)
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AM_RANGE(0x025f8000, 0x025f9fff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr2_ta_r, pvr2_ta_w )
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/* Area 1 */
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AM_RANGE(0x04000000, 0x04ffffff) AM_RAM AM_SHARE("dc_texture_ram") // texture memory 64 bit access
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@ -1639,8 +1609,8 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, naomi_state )
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/* Area 2*/
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AM_RANGE(0x085f6800, 0x085f69ff) AM_WRITE(dc_sysctrl_w ) // writes to BOTH PVRs
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AM_RANGE(0x085f8000, 0x085f9fff) AM_WRITE_LEGACY(pvrs_ta_w ) // writes to BOTH PVRs
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AM_RANGE(0x08800000, 0x088000ff) AM_READWRITE32_LEGACY(elan_regs_r, elan_regs_w, U64(0xffffffffffffffff) ) // T&L chip registers
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AM_RANGE(0x085f8000, 0x085f9fff) AM_DEVWRITE("powervr2", powervr2_device, pvrs_ta_w ) // writes to BOTH PVRs
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AM_RANGE(0x08800000, 0x088000ff) AM_DEVREADWRITE32("powervr2", powervr2_device, elan_regs_r, elan_regs_w, U64(0xffffffffffffffff) ) // T&L chip registers
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// AM_RANGE(0x09000000, 0x09??????) T&L command processing
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AM_RANGE(0x0a000000, 0x0bffffff) AM_RAM AM_SHARE("elan_ram") // T&L chip RAM
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@ -1648,11 +1618,11 @@ static ADDRESS_MAP_START( naomi2_map, AS_PROGRAM, 64, naomi_state )
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AM_RANGE(0x0c000000, 0x0dffffff) AM_MIRROR(0xa2000000) AM_RAM AM_SHARE("dc_ram")
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/* Area 4 */
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AM_RANGE(0x10000000, 0x107fffff) AM_WRITE_LEGACY(ta_fifo_poly_w )
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AM_RANGE(0x10800000, 0x10ffffff) AM_WRITE_LEGACY(ta_fifo_yuv_w )
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AM_RANGE(0x11000000, 0x11ffffff) AM_WRITE(ta_texture_directpath0_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue)
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AM_RANGE(0x10000000, 0x107fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_poly_w)
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AM_RANGE(0x10800000, 0x10ffffff) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_yuv_w)
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AM_RANGE(0x11000000, 0x11ffffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath0_w) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue)
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/* 0x12000000 -0x13ffffff Mirror area of 0x10000000 -0x11ffffff */
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AM_RANGE(0x13000000, 0x13ffffff) AM_WRITE(ta_texture_directpath1_w ) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)
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AM_RANGE(0x13000000, 0x13ffffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath1_w) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue)
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/* Area 5 */
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//AM_RANGE(0x14000000, 0x17ffffff) AM_NOP // MPX Ext.
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@ -1769,8 +1739,8 @@ static ADDRESS_MAP_START( aw_map, AS_PROGRAM, 64, naomi_state )
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AM_RANGE(0x005f7000, 0x005f70ff) AM_MIRROR(0x02000000) AM_DEVICE16( "rom_board", aw_rom_board, submap, U64(0x0000ffff0000ffff) )
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AM_RANGE(0x005f7400, 0x005f74ff) AM_MIRROR(0x02000000) AM_DEVICE32( "rom_board", naomi_g1_device, amap, U64(0xffffffffffffffff) )
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AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
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AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE(pvr_ctrl_r, pvr_ctrl_w )
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AM_RANGE(0x005f8000, 0x005f9fff) AM_READWRITE_LEGACY(pvr_ta_r, pvr_ta_w )
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AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w)
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AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w )
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AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(aw_modem_r, aw_modem_w )
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AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
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AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE(dc_rtc_r, dc_rtc_w )
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@ -1796,11 +1766,11 @@ static ADDRESS_MAP_START( aw_map, AS_PROGRAM, 64, naomi_state )
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AM_RANGE(0x8d000000, 0x8dffffff) AM_RAM AM_SHARE("dc_ram") // RAM access through cache
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/* Area 4 - half the texture memory, like dreamcast, not naomi */
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AM_RANGE(0x10000000, 0x107fffff) AM_MIRROR(0x02000000) AM_WRITE_LEGACY(ta_fifo_poly_w )
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AM_RANGE(0x10800000, 0x10ffffff) AM_MIRROR(0x02000000) AM_WRITE_LEGACY(ta_fifo_yuv_w )
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AM_RANGE(0x11000000, 0x117fffff) AM_WRITE(ta_texture_directpath0_w ) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue
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AM_RANGE(0x10000000, 0x107fffff) AM_MIRROR(0x02000000) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_poly_w)
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AM_RANGE(0x10800000, 0x10ffffff) AM_MIRROR(0x02000000) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_yuv_w)
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AM_RANGE(0x11000000, 0x117fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath0_w) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue
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/* 0x12000000 -0x13ffffff Mirror area of 0x10000000 -0x11ffffff */
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AM_RANGE(0x13000000, 0x137fffff) AM_WRITE(ta_texture_directpath1_w ) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
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AM_RANGE(0x13000000, 0x137fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath1_w) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
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/* Area 5 */
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@ -2526,9 +2496,9 @@ static MACHINE_CONFIG_START( naomi_aw_base, naomi_state )
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MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
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MCFG_SCREEN_SIZE(640, 480)
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MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
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MCFG_SCREEN_UPDATE_DRIVER(naomi_state, screen_update_dc)
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MCFG_SCREEN_UPDATE_DEVICE("powervr2", powervr2_device, screen_update)
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MCFG_PALETTE_LENGTH(0x1000)
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MCFG_POWERVR2_ADD("powervr2")
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MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
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@ -7,6 +7,8 @@
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#ifndef __DC_H__
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#define __DC_H__
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#include "video/powervr2.h"
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class dc_state : public driver_device
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{
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public:
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@ -17,7 +19,8 @@ class dc_state : public driver_device
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dc_sound_ram(*this, "dc_sound_ram"),
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dc_ram(*this, "dc_ram"),
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m_maincpu(*this, "maincpu"),
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m_soundcpu(*this, "soundcpu") { }
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m_soundcpu(*this, "soundcpu"),
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m_powervr2(*this, "powervr2") { }
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required_shared_ptr<UINT64> dc_framebuffer_ram; // '32-bit access area'
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required_shared_ptr<UINT64> dc_texture_ram; // '64-bit access area'
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@ -44,56 +47,20 @@ class dc_state : public driver_device
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UINT8 sel;
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}m_wave_dma;
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struct {
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UINT32 pvr_addr;
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UINT32 sys_addr;
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UINT32 size;
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UINT8 sel;
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UINT8 dir;
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UINT8 flag;
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UINT8 start;
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}m_pvr_dma;
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/* video related */
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UINT32 pvrta_regs[0x2000/4];
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UINT32 pvrctrl_regs[0x100/4];
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UINT32 debug_dip_status;
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emu_timer *vbout_timer;
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emu_timer *vbin_timer;
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emu_timer *hbin_timer;
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emu_timer *endofrender_timer_isp;
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emu_timer *endofrender_timer_tsp;
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emu_timer *endofrender_timer_video;
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UINT32 tafifo_buff[32];
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int scanline;
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int next_y;
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virtual void machine_start();
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virtual void machine_reset();
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virtual void video_start();
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UINT32 screen_update_dc(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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TIMER_CALLBACK_MEMBER(aica_dma_irq);
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TIMER_CALLBACK_MEMBER(pvr_dma_irq);
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TIMER_CALLBACK_MEMBER(ch2_dma_irq);
|
||||
TIMER_CALLBACK_MEMBER(yuv_fifo_irq);
|
||||
TIMER_CALLBACK_MEMBER(dc_rtc_increment);
|
||||
TIMER_CALLBACK_MEMBER(transfer_opaque_list_irq);
|
||||
TIMER_CALLBACK_MEMBER(transfer_opaque_modifier_volume_list_irq);
|
||||
TIMER_CALLBACK_MEMBER(transfer_translucent_list_irq);
|
||||
TIMER_CALLBACK_MEMBER(transfer_translucent_modifier_volume_list_irq);
|
||||
TIMER_CALLBACK_MEMBER(transfer_punch_through_list_irq);
|
||||
TIMER_CALLBACK_MEMBER(vbin);
|
||||
TIMER_CALLBACK_MEMBER(vbout);
|
||||
TIMER_CALLBACK_MEMBER(hbin);
|
||||
TIMER_CALLBACK_MEMBER(endofrender_video);
|
||||
TIMER_CALLBACK_MEMBER(endofrender_tsp);
|
||||
TIMER_CALLBACK_MEMBER(endofrender_isp);
|
||||
DECLARE_READ64_MEMBER(dc_aica_reg_r);
|
||||
DECLARE_WRITE64_MEMBER(dc_aica_reg_w);
|
||||
DECLARE_READ32_MEMBER(dc_arm_aica_r);
|
||||
DECLARE_WRITE32_MEMBER(dc_arm_aica_w);
|
||||
void wave_dma_execute(address_space &space);
|
||||
void pvr_dma_execute(address_space &space);
|
||||
inline int decode_reg32_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift);
|
||||
inline int decode_reg3216_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift);
|
||||
int dc_compute_interrupt_level();
|
||||
@ -106,8 +73,6 @@ class dc_state : public driver_device
|
||||
DECLARE_WRITE64_MEMBER( dc_gdrom_w );
|
||||
DECLARE_READ64_MEMBER( dc_g2_ctrl_r );
|
||||
DECLARE_WRITE64_MEMBER( dc_g2_ctrl_w );
|
||||
DECLARE_READ64_MEMBER( pvr_ctrl_r );
|
||||
DECLARE_WRITE64_MEMBER( pvr_ctrl_w );
|
||||
DECLARE_READ64_MEMBER( dc_modem_r );
|
||||
DECLARE_WRITE64_MEMBER( dc_modem_w );
|
||||
DECLARE_READ64_MEMBER( dc_rtc_r );
|
||||
@ -115,6 +80,7 @@ class dc_state : public driver_device
|
||||
|
||||
required_device<cpu_device> m_maincpu;
|
||||
required_device<cpu_device> m_soundcpu;
|
||||
required_device<powervr2_device> m_powervr2;
|
||||
};
|
||||
|
||||
/*--------- Ch2-DMA Control Registers ----------*/
|
||||
@ -276,29 +242,6 @@ class dc_state : public driver_device
|
||||
#define RTC3 ((0x00710008-0x00710000)/4)
|
||||
|
||||
|
||||
/*----------- defined in video/dc.c -----------*/
|
||||
|
||||
extern UINT32 pvrctrl_regs[0x100/4];
|
||||
extern UINT64 *dc_texture_ram;
|
||||
extern UINT64 *dc_framebuffer_ram;
|
||||
|
||||
extern UINT64 *pvr2_texture_ram;
|
||||
extern UINT64 *pvr2_framebuffer_ram;
|
||||
extern UINT64 *elan_ram;
|
||||
|
||||
DECLARE_READ64_HANDLER( pvr_ta_r );
|
||||
DECLARE_WRITE64_HANDLER( pvr_ta_w );
|
||||
DECLARE_READ64_HANDLER( pvr2_ta_r );
|
||||
DECLARE_WRITE64_HANDLER( pvr2_ta_w );
|
||||
DECLARE_READ64_HANDLER( pvrs_ta_r );
|
||||
DECLARE_WRITE64_HANDLER( pvrs_ta_w );
|
||||
DECLARE_READ32_HANDLER( elan_regs_r );
|
||||
DECLARE_WRITE32_HANDLER( elan_regs_w );
|
||||
DECLARE_WRITE64_HANDLER( ta_fifo_poly_w );
|
||||
DECLARE_WRITE64_HANDLER( ta_fifo_yuv_w );
|
||||
|
||||
|
||||
|
||||
/*--------------- CORE registers --------------*/
|
||||
#define PVRID ((0x005f8000-0x005f8000)/4)
|
||||
#define REVISION ((0x005f8004-0x005f8000)/4)
|
||||
|
||||
@ -56,8 +56,6 @@ class naomi_state : public dc_state
|
||||
DECLARE_WRITE64_MEMBER( naomi_unknown1_w );
|
||||
DECLARE_READ64_MEMBER( eeprom_93c46a_r );
|
||||
DECLARE_WRITE64_MEMBER( eeprom_93c46a_w );
|
||||
DECLARE_WRITE64_MEMBER( ta_texture_directpath0_w );
|
||||
DECLARE_WRITE64_MEMBER( ta_texture_directpath1_w );
|
||||
DECLARE_READ64_MEMBER( aw_flash_r );
|
||||
DECLARE_WRITE64_MEMBER( aw_flash_w );
|
||||
DECLARE_READ64_MEMBER( aw_modem_r );
|
||||
|
||||
@ -17,7 +17,6 @@
|
||||
|
||||
#define DEBUG_SYSCTRL (0)
|
||||
#define DEBUG_AICA_DMA (0)
|
||||
#define DEBUG_PVRCTRL (0)
|
||||
|
||||
#if DEBUG_SYSCTRL
|
||||
static const char *const sysctrl_names[] =
|
||||
@ -82,13 +81,6 @@ TIMER_CALLBACK_MEMBER(dc_state::aica_dma_irq)
|
||||
dc_update_interrupt_status();
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(dc_state::pvr_dma_irq)
|
||||
{
|
||||
m_pvr_dma.start = pvrctrl_regs[SB_PDST] = 0;
|
||||
dc_sysctrl_regs[SB_ISTNRM] |= IST_DMA_PVR;
|
||||
dc_update_interrupt_status();
|
||||
}
|
||||
|
||||
void naomi_g1_irq(running_machine &machine)
|
||||
{
|
||||
dc_state *state = machine.driver_data<dc_state>();
|
||||
@ -158,44 +150,6 @@ void dc_state::wave_dma_execute(address_space &space)
|
||||
machine().scheduler().timer_set(attotime::from_usec(300), timer_expired_delegate(FUNC(dc_state::aica_dma_irq),this));
|
||||
}
|
||||
|
||||
void dc_state::pvr_dma_execute(address_space &space)
|
||||
{
|
||||
UINT32 src,dst,size;
|
||||
dst = m_pvr_dma.pvr_addr;
|
||||
src = m_pvr_dma.sys_addr;
|
||||
size = 0;
|
||||
|
||||
/* used so far by usagui and sprtjam*/
|
||||
//printf("PVR-DMA start\n");
|
||||
//printf("%08x %08x %08x\n",m_pvr_dma.pvr_addr,m_pvr_dma.sys_addr,m_pvr_dma.size);
|
||||
//printf("src %s dst %08x\n",m_pvr_dma.dir ? "->" : "<-",m_pvr_dma.sel);
|
||||
|
||||
/* 0 rounding size = 16 Mbytes */
|
||||
if(m_pvr_dma.size == 0) { m_pvr_dma.size = 0x100000; }
|
||||
|
||||
if(m_pvr_dma.dir == 0)
|
||||
{
|
||||
for(;size<m_pvr_dma.size;size+=4)
|
||||
{
|
||||
space.write_dword(dst,space.read_dword(src));
|
||||
src+=4;
|
||||
dst+=4;
|
||||
}
|
||||
}
|
||||
else
|
||||
{
|
||||
for(;size<m_pvr_dma.size;size+=4)
|
||||
{
|
||||
space.write_dword(src,space.read_dword(dst));
|
||||
src+=4;
|
||||
dst+=4;
|
||||
}
|
||||
}
|
||||
/* Note: do not update the params, since this DMA type doesn't support it. */
|
||||
/* TODO: timing of this */
|
||||
machine().scheduler().timer_set(attotime::from_usec(250), timer_expired_delegate(FUNC(dc_state::pvr_dma_irq),this));
|
||||
}
|
||||
|
||||
// register decode helpers
|
||||
|
||||
// this accepts only 32-bit accesses
|
||||
@ -314,14 +268,14 @@ void dc_state::dc_update_interrupt_status()
|
||||
}
|
||||
|
||||
/* PVR-DMA HW trigger */
|
||||
if(m_pvr_dma.flag && ((m_pvr_dma.sel & 1) == 1))
|
||||
if(m_powervr2->m_pvr_dma.flag && ((m_powervr2->m_pvr_dma.sel & 1) == 1))
|
||||
{
|
||||
if((dc_sysctrl_regs[SB_PDTNRM] & dc_sysctrl_regs[SB_ISTNRM]) || (dc_sysctrl_regs[SB_PDTEXT] & dc_sysctrl_regs[SB_ISTEXT]))
|
||||
{
|
||||
address_space &space = m_maincpu->space(AS_PROGRAM);
|
||||
|
||||
printf("PVR-DMA HW trigger\n");
|
||||
pvr_dma_execute(space);
|
||||
m_powervr2->pvr_dma_execute(space);
|
||||
}
|
||||
}
|
||||
}
|
||||
@ -582,60 +536,6 @@ int dc_state::decode_reg_64(UINT32 offset, UINT64 mem_mask, UINT64 *shift)
|
||||
return reg;
|
||||
}
|
||||
|
||||
READ64_MEMBER(dc_state::pvr_ctrl_r )
|
||||
{
|
||||
int reg;
|
||||
UINT64 shift;
|
||||
|
||||
reg = decode_reg_64(offset, mem_mask, &shift);
|
||||
|
||||
#if DEBUG_PVRCTRL
|
||||
mame_printf_verbose("PVRCTRL: [%08x] read %x @ %x (reg %x), mask %" I64FMT "x (PC=%x)\n", 0x5f7c00+reg*4, pvrctrl_regs[reg], offset, reg, mem_mask, space.device().safe_pc());
|
||||
#endif
|
||||
|
||||
return (UINT64)pvrctrl_regs[reg] << shift;
|
||||
}
|
||||
|
||||
WRITE64_MEMBER(dc_state::pvr_ctrl_w )
|
||||
{
|
||||
int reg;
|
||||
UINT64 shift;
|
||||
UINT32 dat;
|
||||
UINT8 old;
|
||||
|
||||
reg = decode_reg_64(offset, mem_mask, &shift);
|
||||
dat = (UINT32)(data >> shift);
|
||||
|
||||
switch (reg)
|
||||
{
|
||||
case SB_PDSTAP: m_pvr_dma.pvr_addr = dat; break;
|
||||
case SB_PDSTAR: m_pvr_dma.sys_addr = dat; break;
|
||||
case SB_PDLEN: m_pvr_dma.size = dat; break;
|
||||
case SB_PDDIR: m_pvr_dma.dir = dat & 1; break;
|
||||
case SB_PDTSEL:
|
||||
m_pvr_dma.sel = dat & 1;
|
||||
//if(m_pvr_dma.sel & 1)
|
||||
// printf("Warning: Unsupported irq mode trigger PVR-DMA\n");
|
||||
break;
|
||||
case SB_PDEN: m_pvr_dma.flag = dat & 1; break;
|
||||
case SB_PDST:
|
||||
old = m_pvr_dma.start & 1;
|
||||
m_pvr_dma.start = dat & 1;
|
||||
|
||||
if(((old & 1) == 0) && m_pvr_dma.flag && m_pvr_dma.start && ((m_pvr_dma.sel & 1) == 0)) // 0 -> 1
|
||||
pvr_dma_execute(space);
|
||||
break;
|
||||
}
|
||||
|
||||
#if DEBUG_PVRCTRL
|
||||
mame_printf_verbose("PVRCTRL: [%08x=%x] write %" I64FMT "x to %x (reg %x), mask %" I64FMT "x\n", 0x5f7c00+reg*4, dat, data>>shift, offset, reg, mem_mask);
|
||||
#endif
|
||||
|
||||
// pvrctrl_regs[reg] |= dat;
|
||||
pvrctrl_regs[reg] = dat;
|
||||
|
||||
}
|
||||
|
||||
READ64_MEMBER(dc_state::dc_modem_r )
|
||||
{
|
||||
int reg;
|
||||
@ -770,19 +670,6 @@ void dc_state::machine_start()
|
||||
save_item(NAME(m_wave_dma.indirect));
|
||||
save_item(NAME(m_wave_dma.start));
|
||||
save_item(NAME(m_wave_dma.sel));
|
||||
save_item(NAME(m_pvr_dma.pvr_addr));
|
||||
save_item(NAME(m_pvr_dma.sys_addr));
|
||||
save_item(NAME(m_pvr_dma.size));
|
||||
save_item(NAME(m_pvr_dma.sel));
|
||||
save_item(NAME(m_pvr_dma.dir));
|
||||
save_item(NAME(m_pvr_dma.flag));
|
||||
save_item(NAME(m_pvr_dma.start));
|
||||
save_pointer(NAME(pvrta_regs),0x2000/4);
|
||||
save_pointer(NAME(pvrctrl_regs),0x100/4);
|
||||
save_item(NAME(debug_dip_status));
|
||||
save_pointer(NAME(tafifo_buff),32);
|
||||
save_item(NAME(scanline));
|
||||
save_item(NAME(next_y));
|
||||
save_pointer(NAME(dc_sound_ram.target()),dc_sound_ram.bytes());
|
||||
}
|
||||
|
||||
|
||||
@ -1501,7 +1501,7 @@ $(MAMEOBJ)/sega.a: \
|
||||
$(AUDIO)/dsbz80.o \
|
||||
$(DRIVERS)/model2.o $(VIDEO)/model2.o \
|
||||
$(DRIVERS)/model3.o $(VIDEO)/model3.o $(MACHINE)/model3.o \
|
||||
$(DRIVERS)/naomi.o $(MACHINE)/dc.o $(VIDEO)/dc.o $(MACHINE)/naomi.o \
|
||||
$(DRIVERS)/naomi.o $(MACHINE)/dc.o $(VIDEO)/powervr2.o $(MACHINE)/naomi.o \
|
||||
$(MACHINE)/naomig1.o $(MACHINE)/naomibd.o $(MACHINE)/naomirom.o $(MACHINE)/naomigd.o \
|
||||
$(MACHINE)/naomicrypt.o $(MACHINE)/naomim1.o $(MACHINE)/naomim2.o $(MACHINE)/naomim4.o \
|
||||
$(MACHINE)/awboard.o \
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,286 @@
|
||||
#ifndef __POWERVR2_H__
|
||||
#define __POWERVR2_H__
|
||||
|
||||
#define MCFG_POWERVR2_ADD(_tag) \
|
||||
MCFG_DEVICE_ADD(_tag, POWERVR2, 0)
|
||||
|
||||
class powervr2_device : public device_t
|
||||
{
|
||||
public:
|
||||
enum { NUM_BUFFERS = 4 };
|
||||
|
||||
struct {
|
||||
UINT32 pvr_addr;
|
||||
UINT32 sys_addr;
|
||||
UINT32 size;
|
||||
UINT8 sel;
|
||||
UINT8 dir;
|
||||
UINT8 flag;
|
||||
UINT8 start;
|
||||
} m_pvr_dma;
|
||||
|
||||
static const int pvr_parconfseq[];
|
||||
static const int pvr_wordsvertex[24];
|
||||
static const int pvr_wordspolygon[24];
|
||||
int pvr_parameterconfig[128];
|
||||
UINT32 dilated0[15][1024];
|
||||
UINT32 dilated1[15][1024];
|
||||
int dilatechose[64];
|
||||
float wbuffer[480][640];
|
||||
|
||||
|
||||
// the real accumulation buffer is a 32x32x8bpp buffer into which tiles get rendered before they get copied to the framebuffer
|
||||
// our implementation is not currently tile based, and thus the accumulation buffer is screen sized
|
||||
bitmap_rgb32 *fake_accumulationbuffer_bitmap;
|
||||
|
||||
struct texinfo {
|
||||
UINT32 address, vqbase;
|
||||
int textured, sizex, sizey, stride, sizes, pf, palette, mode, mipmapped, blend_mode, filter_mode, flip_u, flip_v;
|
||||
|
||||
UINT32 (powervr2_device::*r)(struct texinfo *t, float x, float y);
|
||||
UINT32 (*blend)(UINT32 s, UINT32 d);
|
||||
int palbase, cd;
|
||||
};
|
||||
|
||||
typedef struct
|
||||
{
|
||||
float x, y, w, u, v;
|
||||
} vert;
|
||||
|
||||
struct strip
|
||||
{
|
||||
int svert, evert;
|
||||
texinfo ti;
|
||||
};
|
||||
|
||||
struct receiveddata {
|
||||
vert verts[65536];
|
||||
strip strips[65536];
|
||||
|
||||
int verts_size, strips_size;
|
||||
UINT32 ispbase;
|
||||
UINT32 fbwsof1;
|
||||
UINT32 fbwsof2;
|
||||
int busy;
|
||||
int valid;
|
||||
};
|
||||
|
||||
enum {
|
||||
TEX_FILTER_NEAREST = 0,
|
||||
TEX_FILTER_BILINEAR,
|
||||
TEX_FILTER_TRILINEAR_A,
|
||||
TEX_FILTER_TRILINEAR_B
|
||||
};
|
||||
|
||||
int tafifo_pos, tafifo_mask, tafifo_vertexwords, tafifo_listtype;
|
||||
int start_render_received;
|
||||
int renderselect;
|
||||
int listtype_used;
|
||||
int alloc_ctrl_OPB_Mode, alloc_ctrl_PT_OPB, alloc_ctrl_TM_OPB, alloc_ctrl_T_OPB, alloc_ctrl_OM_OPB, alloc_ctrl_O_OPB;
|
||||
receiveddata grab[NUM_BUFFERS];
|
||||
int grabsel;
|
||||
int grabsellast;
|
||||
UINT32 paracontrol,paratype,endofstrip,listtype,global_paratype,parameterconfig;
|
||||
UINT32 groupcontrol,groupen,striplen,userclip;
|
||||
UINT32 objcontrol,shadow,volume,coltype,texture,offfset,gouraud,uv16bit;
|
||||
UINT32 texturesizes,textureaddress,scanorder,pixelformat;
|
||||
UINT32 blend_mode, srcselect,dstselect,fogcontrol,colorclamp, use_alpha;
|
||||
UINT32 ignoretexalpha,flipuv,clampuv,filtermode,sstexture,mmdadjust,tsinstruction;
|
||||
UINT32 depthcomparemode,cullingmode,zwritedisable,cachebypass,dcalcctrl,volumeinstruction,mipmapped,vqcompressed,strideselect,paletteselector;
|
||||
|
||||
|
||||
UINT64 *dc_texture_ram;
|
||||
UINT64 *dc_framebuffer_ram;
|
||||
|
||||
UINT64 *pvr2_texture_ram;
|
||||
UINT64 *pvr2_framebuffer_ram;
|
||||
UINT64 *elan_ram;
|
||||
|
||||
UINT32 pvrta_regs[0x2000/4];
|
||||
UINT32 pvrctrl_regs[0x100/4];
|
||||
UINT32 debug_dip_status;
|
||||
emu_timer *vbout_timer;
|
||||
emu_timer *vbin_timer;
|
||||
emu_timer *hbin_timer;
|
||||
emu_timer *endofrender_timer_isp;
|
||||
emu_timer *endofrender_timer_tsp;
|
||||
emu_timer *endofrender_timer_video;
|
||||
UINT32 tafifo_buff[32];
|
||||
int scanline;
|
||||
int next_y;
|
||||
|
||||
powervr2_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
|
||||
|
||||
DECLARE_READ64_MEMBER( pvr_ctrl_r );
|
||||
DECLARE_WRITE64_MEMBER( pvr_ctrl_w );
|
||||
DECLARE_READ64_MEMBER( pvr_ta_r );
|
||||
DECLARE_WRITE64_MEMBER( pvr_ta_w );
|
||||
DECLARE_READ64_MEMBER( pvr2_ta_r );
|
||||
DECLARE_WRITE64_MEMBER( pvr2_ta_w );
|
||||
DECLARE_READ64_MEMBER( pvrs_ta_r );
|
||||
DECLARE_WRITE64_MEMBER( pvrs_ta_w );
|
||||
DECLARE_READ32_MEMBER( elan_regs_r );
|
||||
DECLARE_WRITE32_MEMBER( elan_regs_w );
|
||||
DECLARE_WRITE64_MEMBER( ta_fifo_poly_w );
|
||||
DECLARE_WRITE64_MEMBER( ta_fifo_yuv_w );
|
||||
DECLARE_WRITE64_MEMBER( ta_texture_directpath0_w );
|
||||
DECLARE_WRITE64_MEMBER( ta_texture_directpath1_w );
|
||||
|
||||
TIMER_CALLBACK_MEMBER(vbin);
|
||||
TIMER_CALLBACK_MEMBER(vbout);
|
||||
TIMER_CALLBACK_MEMBER(hbin);
|
||||
TIMER_CALLBACK_MEMBER(endofrender_video);
|
||||
TIMER_CALLBACK_MEMBER(endofrender_tsp);
|
||||
TIMER_CALLBACK_MEMBER(endofrender_isp);
|
||||
TIMER_CALLBACK_MEMBER(transfer_opaque_list_irq);
|
||||
TIMER_CALLBACK_MEMBER(transfer_opaque_modifier_volume_list_irq);
|
||||
TIMER_CALLBACK_MEMBER(transfer_translucent_list_irq);
|
||||
TIMER_CALLBACK_MEMBER(transfer_translucent_modifier_volume_list_irq);
|
||||
TIMER_CALLBACK_MEMBER(transfer_punch_through_list_irq);
|
||||
TIMER_CALLBACK_MEMBER(pvr_dma_irq);
|
||||
|
||||
void pvr_dma_execute(address_space &space);
|
||||
UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
|
||||
protected:
|
||||
virtual void device_start();
|
||||
virtual void device_reset();
|
||||
|
||||
private:
|
||||
static UINT32 (*const blend_functions[64])(UINT32 s, UINT32 d);
|
||||
|
||||
static inline INT32 clamp(INT32 in, INT32 min, INT32 max);
|
||||
static inline UINT32 bilinear_filter(UINT32 c0, UINT32 c1, UINT32 c2, UINT32 c3, float u, float v);
|
||||
static inline UINT32 bla(UINT32 c, UINT32 a);
|
||||
static inline UINT32 blia(UINT32 c, UINT32 a);
|
||||
static inline UINT32 blc(UINT32 c1, UINT32 c2);
|
||||
static inline UINT32 blic(UINT32 c1, UINT32 c2);
|
||||
static inline UINT32 bls(UINT32 c1, UINT32 c2);
|
||||
static UINT32 bl00(UINT32 s, UINT32 d);
|
||||
static UINT32 bl01(UINT32 s, UINT32 d);
|
||||
static UINT32 bl02(UINT32 s, UINT32 d);
|
||||
static UINT32 bl03(UINT32 s, UINT32 d);
|
||||
static UINT32 bl04(UINT32 s, UINT32 d);
|
||||
static UINT32 bl05(UINT32 s, UINT32 d);
|
||||
static UINT32 bl06(UINT32 s, UINT32 d);
|
||||
static UINT32 bl07(UINT32 s, UINT32 d);
|
||||
static UINT32 bl10(UINT32 s, UINT32 d);
|
||||
static UINT32 bl11(UINT32 s, UINT32 d);
|
||||
static UINT32 bl12(UINT32 s, UINT32 d);
|
||||
static UINT32 bl13(UINT32 s, UINT32 d);
|
||||
static UINT32 bl14(UINT32 s, UINT32 d);
|
||||
static UINT32 bl15(UINT32 s, UINT32 d);
|
||||
static UINT32 bl16(UINT32 s, UINT32 d);
|
||||
static UINT32 bl17(UINT32 s, UINT32 d);
|
||||
static UINT32 bl20(UINT32 s, UINT32 d);
|
||||
static UINT32 bl21(UINT32 s, UINT32 d);
|
||||
static UINT32 bl22(UINT32 s, UINT32 d);
|
||||
static UINT32 bl23(UINT32 s, UINT32 d);
|
||||
static UINT32 bl24(UINT32 s, UINT32 d);
|
||||
static UINT32 bl25(UINT32 s, UINT32 d);
|
||||
static UINT32 bl26(UINT32 s, UINT32 d);
|
||||
static UINT32 bl27(UINT32 s, UINT32 d);
|
||||
static UINT32 bl30(UINT32 s, UINT32 d);
|
||||
static UINT32 bl31(UINT32 s, UINT32 d);
|
||||
static UINT32 bl32(UINT32 s, UINT32 d);
|
||||
static UINT32 bl33(UINT32 s, UINT32 d);
|
||||
static UINT32 bl34(UINT32 s, UINT32 d);
|
||||
static UINT32 bl35(UINT32 s, UINT32 d);
|
||||
static UINT32 bl36(UINT32 s, UINT32 d);
|
||||
static UINT32 bl37(UINT32 s, UINT32 d);
|
||||
static UINT32 bl40(UINT32 s, UINT32 d);
|
||||
static UINT32 bl41(UINT32 s, UINT32 d);
|
||||
static UINT32 bl42(UINT32 s, UINT32 d);
|
||||
static UINT32 bl43(UINT32 s, UINT32 d);
|
||||
static UINT32 bl44(UINT32 s, UINT32 d);
|
||||
static UINT32 bl45(UINT32 s, UINT32 d);
|
||||
static UINT32 bl46(UINT32 s, UINT32 d);
|
||||
static UINT32 bl47(UINT32 s, UINT32 d);
|
||||
static UINT32 bl50(UINT32 s, UINT32 d);
|
||||
static UINT32 bl51(UINT32 s, UINT32 d);
|
||||
static UINT32 bl52(UINT32 s, UINT32 d);
|
||||
static UINT32 bl53(UINT32 s, UINT32 d);
|
||||
static UINT32 bl54(UINT32 s, UINT32 d);
|
||||
static UINT32 bl55(UINT32 s, UINT32 d);
|
||||
static UINT32 bl56(UINT32 s, UINT32 d);
|
||||
static UINT32 bl57(UINT32 s, UINT32 d);
|
||||
static UINT32 bl60(UINT32 s, UINT32 d);
|
||||
static UINT32 bl61(UINT32 s, UINT32 d);
|
||||
static UINT32 bl62(UINT32 s, UINT32 d);
|
||||
static UINT32 bl63(UINT32 s, UINT32 d);
|
||||
static UINT32 bl64(UINT32 s, UINT32 d);
|
||||
static UINT32 bl65(UINT32 s, UINT32 d);
|
||||
static UINT32 bl66(UINT32 s, UINT32 d);
|
||||
static UINT32 bl67(UINT32 s, UINT32 d);
|
||||
static UINT32 bl70(UINT32 s, UINT32 d);
|
||||
static UINT32 bl71(UINT32 s, UINT32 d);
|
||||
static UINT32 bl72(UINT32 s, UINT32 d);
|
||||
static UINT32 bl73(UINT32 s, UINT32 d);
|
||||
static UINT32 bl74(UINT32 s, UINT32 d);
|
||||
static UINT32 bl75(UINT32 s, UINT32 d);
|
||||
static UINT32 bl76(UINT32 s, UINT32 d);
|
||||
static UINT32 bl77(UINT32 s, UINT32 d);
|
||||
static inline UINT32 cv_1555(UINT16 c);
|
||||
static inline UINT32 cv_1555z(UINT16 c);
|
||||
static inline UINT32 cv_565(UINT16 c);
|
||||
static inline UINT32 cv_565z(UINT16 c);
|
||||
static inline UINT32 cv_4444(UINT16 c);
|
||||
static inline UINT32 cv_4444z(UINT16 c);
|
||||
static inline UINT32 cv_yuv(UINT16 c1, UINT16 c2, int x);
|
||||
UINT32 tex_r_yuv_n(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_1555_n(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_1555_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_1555_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_565_n(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_565_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_565_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_4444_n(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_4444_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_4444_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p4_1555_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p4_1555_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p4_565_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p4_565_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p4_4444_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p4_4444_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p4_8888_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p4_8888_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p8_1555_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p8_1555_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p8_565_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p8_565_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p8_4444_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p8_4444_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p8_8888_tw(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_p8_8888_vq(texinfo *t, float x, float y);
|
||||
UINT32 tex_r_default(texinfo *t, float x, float y);
|
||||
void tex_get_info(texinfo *t);
|
||||
|
||||
void render_hline(bitmap_rgb32 &bitmap, texinfo *ti, int y, float xl, float xr, float ul, float ur, float vl, float vr, float wl, float wr);
|
||||
void render_span(bitmap_rgb32 &bitmap, texinfo *ti,
|
||||
float y0, float y1,
|
||||
float xl, float xr,
|
||||
float ul, float ur,
|
||||
float vl, float vr,
|
||||
float wl, float wr,
|
||||
float dxldy, float dxrdy,
|
||||
float duldy, float durdy,
|
||||
float dvldy, float dvrdy,
|
||||
float dwldy, float dwrdy);
|
||||
void sort_vertices(const vert *v, int *i0, int *i1, int *i2);
|
||||
void render_tri_sorted(bitmap_rgb32 &bitmap, texinfo *ti, const vert *v0, const vert *v1, const vert *v2);
|
||||
void render_tri(bitmap_rgb32 &bitmap, texinfo *ti, const vert *v);
|
||||
void render_to_accumulation_buffer(bitmap_rgb32 &bitmap, const rectangle &cliprect);
|
||||
void pvr_accumulationbuffer_to_framebuffer(address_space &space, int x, int y);
|
||||
void pvr_drawframebuffer(bitmap_rgb32 &bitmap,const rectangle &cliprect);
|
||||
static UINT32 dilate0(UINT32 value,int bits);
|
||||
static UINT32 dilate1(UINT32 value,int bits);
|
||||
void computedilated();
|
||||
void pvr_build_parameterconfig();
|
||||
void process_ta_fifo();
|
||||
void debug_paletteram();
|
||||
};
|
||||
|
||||
extern const device_type POWERVR2;
|
||||
|
||||
#endif
|
||||
@ -110,37 +110,6 @@ WRITE64_MEMBER(dc_cons_state::dc_arm_w )
|
||||
COMBINE_DATA((UINT64 *)dc_sound_ram.target() + offset);
|
||||
}
|
||||
|
||||
|
||||
// SB_LMMODE0
|
||||
WRITE64_MEMBER(dc_cons_state::ta_texture_directpath0_w )
|
||||
{
|
||||
int mode = pvrctrl_regs[SB_LMMODE0]&1;
|
||||
if (mode&1)
|
||||
{
|
||||
printf("ta_texture_directpath0_w 32-bit access!\n");
|
||||
COMBINE_DATA(&dc_framebuffer_ram[offset]);
|
||||
}
|
||||
else
|
||||
{
|
||||
COMBINE_DATA(&dc_texture_ram[offset]);
|
||||
}
|
||||
}
|
||||
|
||||
// SB_LMMODE1
|
||||
WRITE64_MEMBER(dc_cons_state::ta_texture_directpath1_w )
|
||||
{
|
||||
int mode = pvrctrl_regs[SB_LMMODE1]&1;
|
||||
if (mode&1)
|
||||
{
|
||||
printf("ta_texture_directpath1_w 32-bit access!\n");
|
||||
COMBINE_DATA(&dc_framebuffer_ram[offset]);
|
||||
}
|
||||
else
|
||||
{
|
||||
COMBINE_DATA(&dc_texture_ram[offset]);
|
||||
}
|
||||
}
|
||||
|
||||
static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_cons_state )
|
||||
AM_RANGE(0x00000000, 0x001fffff) AM_ROM AM_WRITENOP // BIOS
|
||||
AM_RANGE(0x00200000, 0x0021ffff) AM_ROM AM_REGION("maincpu", 0x200000) // flash
|
||||
@ -149,8 +118,8 @@ static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_cons_state )
|
||||
AM_RANGE(0x005f7000, 0x005f70ff) AM_READWRITE(dc_mess_gdrom_r, dc_mess_gdrom_w )
|
||||
AM_RANGE(0x005f7400, 0x005f74ff) AM_READWRITE(dc_mess_g1_ctrl_r, dc_mess_g1_ctrl_w )
|
||||
AM_RANGE(0x005f7800, 0x005f78ff) AM_READWRITE(dc_g2_ctrl_r, dc_g2_ctrl_w )
|
||||
AM_RANGE(0x005f7c00, 0x005f7cff) AM_READWRITE(pvr_ctrl_r, pvr_ctrl_w )
|
||||
AM_RANGE(0x005f8000, 0x005f9fff) AM_READWRITE_LEGACY(pvr_ta_r, pvr_ta_w )
|
||||
AM_RANGE(0x005f7c00, 0x005f7cff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ctrl_r, pvr_ctrl_w)
|
||||
AM_RANGE(0x005f8000, 0x005f9fff) AM_DEVREADWRITE("powervr2", powervr2_device, pvr_ta_r, pvr_ta_w )
|
||||
AM_RANGE(0x00600000, 0x006007ff) AM_READWRITE(dc_modem_r, dc_modem_w )
|
||||
AM_RANGE(0x00700000, 0x00707fff) AM_READWRITE(dc_aica_reg_r, dc_aica_reg_w )
|
||||
AM_RANGE(0x00710000, 0x0071000f) AM_READWRITE(dc_rtc_r, dc_rtc_w )
|
||||
@ -167,13 +136,13 @@ static ADDRESS_MAP_START( dc_map, AS_PROGRAM, 64, dc_cons_state )
|
||||
AM_RANGE(0x0f000000, 0x0fffffff) AM_RAM AM_SHARE("dc_ram")// mirror
|
||||
|
||||
/* Area 4 */
|
||||
AM_RANGE(0x10000000, 0x107fffff) AM_WRITE_LEGACY(ta_fifo_poly_w )
|
||||
AM_RANGE(0x10800000, 0x10ffffff) AM_WRITE_LEGACY(ta_fifo_yuv_w )
|
||||
AM_RANGE(0x11000000, 0x117fffff) AM_WRITE(ta_texture_directpath0_w ) AM_MIRROR(0x00800000) // access to texture / fraembfufer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue
|
||||
AM_RANGE(0x10000000, 0x107fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_poly_w)
|
||||
AM_RANGE(0x10800000, 0x10ffffff) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_yuv_w)
|
||||
AM_RANGE(0x11000000, 0x117fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath0_w) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE0 register - cannot be written directly, only through dma / store queue
|
||||
|
||||
AM_RANGE(0x12000000, 0x127fffff) AM_WRITE_LEGACY(ta_fifo_poly_w )
|
||||
AM_RANGE(0x12800000, 0x12ffffff) AM_WRITE_LEGACY(ta_fifo_yuv_w )
|
||||
AM_RANGE(0x13000000, 0x137fffff) AM_WRITE(ta_texture_directpath1_w ) AM_MIRROR(0x00800000) // access to texture / fraembfufer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
|
||||
AM_RANGE(0x12000000, 0x127fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_poly_w)
|
||||
AM_RANGE(0x12800000, 0x12ffffff) AM_DEVWRITE("powervr2", powervr2_device, ta_fifo_yuv_w)
|
||||
AM_RANGE(0x13000000, 0x137fffff) AM_DEVWRITE("powervr2", powervr2_device, ta_texture_directpath1_w) AM_MIRROR(0x00800000) // access to texture / framebuffer memory (either 32-bit or 64-bit area depending on SB_LMMODE1 register - cannot be written directly, only through dma / store queue
|
||||
|
||||
AM_RANGE(0x8c000000, 0x8cffffff) AM_RAM AM_SHARE("dc_ram") // another RAM mirror
|
||||
|
||||
@ -235,10 +204,9 @@ static MACHINE_CONFIG_START( dc, dc_cons_state )
|
||||
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500) /* not accurate */)
|
||||
MCFG_SCREEN_SIZE(640, 480)
|
||||
MCFG_SCREEN_VISIBLE_AREA(0, 640-1, 0, 480-1)
|
||||
MCFG_SCREEN_UPDATE_DRIVER(dc_cons_state, screen_update_dc)
|
||||
|
||||
MCFG_SCREEN_UPDATE_DEVICE("powervr2", powervr2_device, screen_update)
|
||||
MCFG_PALETTE_LENGTH(0x1000)
|
||||
|
||||
MCFG_POWERVR2_ADD("powervr2")
|
||||
|
||||
MCFG_SPEAKER_STANDARD_STEREO("lspeaker", "rspeaker")
|
||||
MCFG_SOUND_ADD("aica", AICA, 0)
|
||||
|
||||
@ -20,8 +20,6 @@ public:
|
||||
DECLARE_WRITE64_MEMBER(dc_pdtra_w);
|
||||
DECLARE_READ64_MEMBER(dc_arm_r);
|
||||
DECLARE_WRITE64_MEMBER(dc_arm_w);
|
||||
DECLARE_WRITE64_MEMBER(ta_texture_directpath0_w);
|
||||
DECLARE_WRITE64_MEMBER(ta_texture_directpath1_w);
|
||||
DECLARE_WRITE_LINE_MEMBER(aica_irq);
|
||||
void gdrom_raise_irq();
|
||||
TIMER_CALLBACK_MEMBER( atapi_xfer_end );
|
||||
|
||||
@ -683,8 +683,7 @@ $(MESSOBJ)/mame.a: \
|
||||
$(MAME_DRIVERS)/megatech.o \
|
||||
$(MAME_MACHINE)/dc.o \
|
||||
$(MAME_DRIVERS)/naomi.o \
|
||||
$(MAME_MACHINE)/dc.o \
|
||||
$(MAME_VIDEO)/dc.o \
|
||||
$(MAME_VIDEO)/powervr2.o \
|
||||
$(MAME_MACHINE)/naomi.o \
|
||||
$(MAME_MACHINE)/naomig1.o \
|
||||
$(MAME_MACHINE)/naomibd.o \
|
||||
@ -699,7 +698,6 @@ $(MESSOBJ)/mame.a: \
|
||||
$(MAME_MACHINE)/mapledev.o \
|
||||
$(MAME_MACHINE)/dc-ctrl.o \
|
||||
$(MAME_MACHINE)/jvs13551.o \
|
||||
$(MAME_VIDEO)/dc.o \
|
||||
$(MAME_VIDEO)/neogeo.o \
|
||||
$(MAME_MACHINE)/neoprot.o \
|
||||
$(MAME_MACHINE)/neocrypt.o \
|
||||
|
||||
Loading…
Reference in New Issue
Block a user