init vars for coverity (bus/l-w)

This commit is contained in:
Robbbert 2022-04-02 02:16:51 +11:00
parent 5a29819506
commit b206c1c7bd
80 changed files with 319 additions and 319 deletions

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@ -78,7 +78,7 @@ protected:
uint8_t m_channel_check; uint8_t m_channel_check;
uint8_t m_nmi_enabled; uint8_t m_nmi_enabled;
bool m_ide_io_ports_enabled; bool m_ide_io_ports_enabled;
address_space *spaceio; address_space *spaceio = nullptr;
void pc_select_dma_channel(int channel, bool state); void pc_select_dma_channel(int channel, bool state);

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@ -101,8 +101,8 @@ private:
memory_share_creator<u8> m_share; memory_share_creator<u8> m_share;
memory_view m_view; memory_view m_view;
memory_bank_array_creator<8> m_bank; memory_bank_array_creator<8> m_bank;
uint8_t ram_bank_cr; uint8_t ram_bank_cr = 0;
uint8_t rom_map_cr; uint8_t rom_map_cr = 0;
void update_banks(); void update_banks();

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@ -204,20 +204,20 @@ private:
std::vector<uint8_t> m_sram; std::vector<uint8_t> m_sram;
// EEPROM runtime vars // EEPROM runtime vars
uint8_t m_eeprom_sda; // current SDA uint8_t m_eeprom_sda = 0; // current SDA
uint8_t m_eeprom_prev_sda; // previous SDA uint8_t m_eeprom_prev_sda = 0; // previous SDA
uint8_t m_eeprom_scl; // current SCL uint8_t m_eeprom_scl = 0; // current SCL
uint8_t m_eeprom_prev_scl; // previous SCL uint8_t m_eeprom_prev_scl = 0; // previous SCL
uint8_t m_eeprom_cnt; // operation count in 0-9 uint8_t m_eeprom_cnt = 0; // operation count in 0-9
uint8_t m_eeprom_readwrite; // read/write bit uint8_t m_eeprom_readwrite = 0; // read/write bit
uint16_t m_eeprom_slave_mask; // dev addr uint16_t m_eeprom_slave_mask = 0; // dev addr
uint16_t m_eeprom_word_address; // memory addr uint16_t m_eeprom_word_address = 0; // memory addr
uint16_t m_eeprom_devsel; // selected device uint16_t m_eeprom_devsel = 0; // selected device
uint16_t m_eeprom_byte; // byte to be written uint16_t m_eeprom_byte = 0; // byte to be written
int m_eeprom_cur_state; // current state int m_eeprom_cur_state = 0; // current state
// EEPROM physical characteristics (configured at init) // EEPROM physical characteristics (configured at init)
uint16_t m_eeprom_mask; // size of the memory - 1 uint16_t m_eeprom_mask = 0; // size of the memory - 1
uint16_t m_eeprom_pagewrite_mask; // max number of bytes that can be written in a single write cycle uint16_t m_eeprom_pagewrite_mask = 0; // max number of bytes that can be written in a single write cycle
}; };

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@ -501,7 +501,7 @@ protected:
virtual void device_reset() override; virtual void device_reset() override;
private: private:
uint16_t m_retvalue; uint16_t m_retvalue = 0;
}; };

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@ -30,7 +30,7 @@ private:
uint32_t m_total_size; uint32_t m_total_size;
uint8_t m_bank_mask; uint8_t m_bank_mask;
uint8_t m_bank_selected[4]; uint8_t m_bank_selected[4];
uint8_t *m_bank_base[4]; uint8_t *m_bank_base[4]{};
uint8_t m_ramio_set_bits; uint8_t m_ramio_set_bits;
}; };

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@ -100,38 +100,38 @@ private:
cpu_device *m_cpu; // When != nullptr: CPU is suspended in wait state cpu_device *m_cpu; // When != nullptr: CPU is suspended in wait state
bool m_cpu_rd; bool m_cpu_rd;
uint8_t m_ready_in; uint8_t m_ready_in;
uint8_t m_ready_ff; // I-A44 & I-A43 uint8_t m_ready_ff = 0; // I-A44 & I-A43
bool m_gate_lower; // I-A58-9 bool m_gate_lower = false; // I-A58-9
bool m_irq; // C-A37-9 bool m_irq = false; // C-A37-9
uint8_t m_data_low_out; // C-A43 uint8_t m_data_low_out = 0; // C-A43
uint8_t m_data_low_in; // C-A25 uint8_t m_data_low_in = 0; // C-A25
uint8_t m_cpu_data; uint8_t m_cpu_data = 0;
uint8_t m_addr_low_out; // C-A41 uint8_t m_addr_low_out = 0; // C-A41
bool m_mem_wrt; // I-A58-4 bool m_mem_wrt = false; // I-A58-4
bool m_wrt_inh; // I-A46-13 bool m_wrt_inh = false; // I-A46-13
bool m_direction; // I-A58-11 bool m_direction = false; // I-A58-11
bool m_ibus_cached; bool m_ibus_cached = false;
uint8_t m_ibus; uint8_t m_ibus = 0;
uint16_t m_crc; // I-A62 uint16_t m_crc = 0; // I-A62
bool m_crc_enabled; // I-A58-13 bool m_crc_enabled = false; // I-A58-13
bool m_crc_out; // C-A16-2 bool m_crc_out = false; // C-A16-2
bool m_reading; // I-A46-9 bool m_reading = false; // I-A46-9
bool m_writing; // C-A16-4 bool m_writing = false; // C-A16-4
uint16_t m_data_sr; // C-A36 & C-A29 (MSB), next byte in LSB uint16_t m_data_sr = 0; // C-A36 & C-A29 (MSB), next byte in LSB
bool m_last_data_bit; // I-A48-6 bool m_last_data_bit = false; // I-A48-6
uint16_t m_clock_sr; // C-A34 & C-A27 (MSB), next byte in LSB uint16_t m_clock_sr = 0; // C-A34 & C-A27 (MSB), next byte in LSB
attotime m_last_f_time; attotime m_last_f_time;
bool m_clock_gate; // I-A10-8 bool m_clock_gate = false; // I-A10-8
bool m_amwrt; // I-A58-6 bool m_amwrt = false; // I-A58-6
bool m_dlyd_amwrt; bool m_dlyd_amwrt = false;
// PLL // PLL
fdc_pll_t m_pll; fdc_pll_t m_pll;
// Timers // Timers
emu_timer *m_timeout_timer; emu_timer *m_timeout_timer = nullptr;
emu_timer *m_byte_timer; emu_timer *m_byte_timer = nullptr;
emu_timer *m_f_timer; emu_timer *m_f_timer = nullptr;
void set_output(); void set_output();
unsigned selected_drive() const; unsigned selected_drive() const;

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@ -36,10 +36,10 @@ protected:
virtual void device_add_mconfig(machine_config &config) override; virtual void device_add_mconfig(machine_config &config) override;
private: private:
uint8_t* m_fixed; uint8_t* m_fixed = nullptr;
uint32_t m_special_bank; uint32_t m_special_bank = 0;
uint16_t m_cart_ram[0x1000]; uint16_t m_cart_ram[0x1000]{};
uint16_t m_cart_ram2[0x10000]; uint16_t m_cart_ram2[0x10000]{};
}; };
// device type definition // device type definition

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@ -29,9 +29,9 @@ protected:
virtual void device_reset() override; virtual void device_reset() override;
private: private:
uint16_t m_overlay; uint16_t m_overlay = 0;
uint32_t m_bank_base; uint32_t m_bank_base = 0;
uint16_t m_cartridge_ram[0x1000]; // bootlegs uint16_t m_cartridge_ram[0x1000]{}; // bootlegs
}; };
#endif // MAME_BUS_NEOGEO_PROT_KOF2K3BL_H #endif // MAME_BUS_NEOGEO_PROT_KOF2K3BL_H

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@ -334,7 +334,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
int m_type; int m_type = 0;
device_neogeo_cart_interface* m_cart; device_neogeo_cart_interface* m_cart;
}; };

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@ -40,7 +40,7 @@ protected:
private: private:
required_ioport_array<4> m_joy; required_ioport_array<4> m_joy;
required_ioport_array<2> m_ss; required_ioport_array<2> m_ss;
uint8_t m_ctrl_sel; uint8_t m_ctrl_sel = 0;
}; };

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@ -57,7 +57,7 @@ private:
uint16_t m_irq_count, m_irq_count_latch; uint16_t m_irq_count, m_irq_count_latch;
int m_irq_enable, m_irq_repeat, m_irq_transfer; int m_irq_enable, m_irq_repeat, m_irq_transfer;
int m_disk_reg_enable; int m_disk_reg_enable;
bool m_sound_en; bool m_sound_en = false;
uint8_t m_fds_motor_on; uint8_t m_fds_motor_on;
uint8_t m_fds_door_closed; uint8_t m_fds_door_closed;

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@ -42,27 +42,27 @@ protected:
virtual void update_mirror() { update_mirror_typea(); } virtual void update_mirror() { update_mirror_typea(); }
inline uint8_t unscramble(uint8_t bank); inline uint8_t unscramble(uint8_t bank);
uint8_t m_mul[2]; uint8_t m_mul[2]{};
uint8_t m_latch; uint8_t m_latch = 0;
uint8_t m_reg[4]; uint8_t m_reg[4]{};
uint8_t m_chr_latch[2]; // type C uses a more complex CHR 4K mode, and these vars are only changed for those games uint8_t m_chr_latch[2]{}; // type C uses a more complex CHR 4K mode, and these vars are only changed for those games
uint8_t m_mmc_prg_bank[4]; uint8_t m_mmc_prg_bank[4]{};
uint16_t m_mmc_nt_bank[4]; uint16_t m_mmc_nt_bank[4]{};
uint16_t m_mmc_vrom_bank[8]; uint16_t m_mmc_vrom_bank[8]{};
uint16_t m_extra_chr_bank; uint16_t m_extra_chr_bank = 0;
uint16_t m_extra_chr_mask; uint16_t m_extra_chr_mask = 0;
int m_bank_6000; int m_bank_6000 = 0;
uint8_t m_irq_mode; uint8_t m_irq_mode = 0;
uint8_t m_irq_count; uint8_t m_irq_count = 0;
uint8_t m_irq_prescale; uint8_t m_irq_prescale = 0;
uint8_t m_irq_prescale_mask; uint8_t m_irq_prescale_mask = 0;
uint8_t m_irq_flip; uint8_t m_irq_flip = 0;
int m_irq_enable; int m_irq_enable = 0;
int m_irq_up, m_irq_down; int m_irq_up = 0, m_irq_down = 0;
static const device_timer_id TIMER_IRQ = 0; static const device_timer_id TIMER_IRQ = 0;
emu_timer *irq_timer; emu_timer *irq_timer = nullptr;
attotime timer_freq; attotime timer_freq;
}; };

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@ -23,7 +23,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
u8 m_latch; u8 m_latch = 0;
}; };
@ -63,7 +63,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
uint8_t m_latch; uint8_t m_latch = 0;
}; };
@ -88,11 +88,11 @@ protected:
virtual void device_start() override; virtual void device_start() override;
virtual void device_timer(emu_timer &timer, device_timer_id id, int param) override; virtual void device_timer(emu_timer &timer, device_timer_id id, int param) override;
u8 m_reg[8]; u8 m_reg[8]{};
private: private:
void prg_update(); void prg_update();
u8 m_latch; u8 m_latch = 0;
u16 m_irq_count, m_irq_count_latch; u16 m_irq_count, m_irq_count_latch;
int m_irq_enable; int m_irq_enable;
@ -136,7 +136,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
u8 m_latch; u8 m_latch = 0;
const u8 m_a15_flip; const u8 m_a15_flip;
}; };
@ -171,7 +171,7 @@ protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param) override; virtual void device_timer(emu_timer &timer, device_timer_id id, int param) override;
private: private:
uint8_t m_latch; uint8_t m_latch = 0;
uint16_t m_irq_count; uint16_t m_irq_count;
uint8_t m_irq_status; uint8_t m_irq_status;
@ -218,7 +218,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
u8 m_latch; u8 m_latch = 0;
}; };
@ -327,7 +327,7 @@ protected:
private: private:
void update_prg(); void update_prg();
uint8_t m_latch; uint8_t m_latch = 0;
uint8_t m_reg[8]; uint8_t m_reg[8];
}; };

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@ -187,7 +187,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
int m_prot; int m_prot = 0;
}; };
@ -320,7 +320,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
uint8_t m_prot; uint8_t m_prot = 0;
}; };

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@ -314,7 +314,7 @@ public:
// PRG // PRG
inline int prg_8k_bank_num(int bank); inline int prg_8k_bank_num(int bank);
inline void update_prg_banks(int prg_bank_start, int prg_bank_end); inline void update_prg_banks(int prg_bank_start, int prg_bank_end);
memory_bank *m_prg_bank_mem[4]; memory_bank *m_prg_bank_mem[4]{};
int m_prg_bank[4]; int m_prg_bank[4];
uint32_t m_prg_chunks; uint32_t m_prg_chunks;
uint32_t m_prg_mask; uint32_t m_prg_mask;
@ -337,7 +337,7 @@ public:
//because some of these change multiple times per scanline! //because some of these change multiple times per scanline!
int m_chr_src[8]; //defines source of base pointer int m_chr_src[8]; //defines source of base pointer
int m_chr_orig[8]; //defines offset of 0x400 byte segment at base pointer int m_chr_orig[8]; //defines offset of 0x400 byte segment at base pointer
uint8_t *m_chr_access[8]; //source translated + origin -> valid pointer! uint8_t *m_chr_access[8]{}; //source translated + origin -> valid pointer!
uint32_t m_vrom_chunks; uint32_t m_vrom_chunks;
uint32_t m_vram_chunks; uint32_t m_vram_chunks;
@ -371,7 +371,7 @@ public:
int m_nt_src[4]; int m_nt_src[4];
int m_nt_orig[4]; int m_nt_orig[4];
int m_nt_writable[4]; int m_nt_writable[4];
uint8_t *m_nt_access[4]; //quick banking structure for a maximum of 4K of RAM/ROM/ExRAM uint8_t *m_nt_access[4]{}; //quick banking structure for a maximum of 4K of RAM/ROM/ExRAM
void set_nt_page(int page, int source, int bank, int writable); void set_nt_page(int page, int source, int bank, int writable);
void set_nt_mirroring(int mirroring); void set_nt_mirroring(int mirroring);

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@ -64,7 +64,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
uint8_t m_latch; uint8_t m_latch = 0;
uint8_t m_ram[0xb00]; uint8_t m_ram[0xb00];
}; };
@ -174,7 +174,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
uint8_t m_latch; uint8_t m_latch = 0;
}; };
@ -198,7 +198,7 @@ protected:
private: private:
void update_banks(); void update_banks();
u8 m_latch; u8 m_latch = 0;
u8 m_reg[6]; u8 m_reg[6];
u16 m_irq_count, m_irq_count_latch; u16 m_irq_count, m_irq_count_latch;
@ -224,7 +224,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
uint16_t m_latch; uint16_t m_latch = 0;
}; };
@ -247,7 +247,7 @@ protected:
private: private:
u8 m_jumper; u8 m_jumper;
u16 m_latch; u16 m_latch = 0;
u8 m_reg; u8 m_reg;
}; };
@ -272,7 +272,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
uint8_t m_latch; uint8_t m_latch = 0;
}; };
#endif #endif

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@ -148,7 +148,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
u8 m_reg; u8 m_reg = 0;
}; };
@ -203,7 +203,7 @@ protected:
private: private:
u16 m_irq_count; u16 m_irq_count;
u8 m_irq_latch; u8 m_irq_latch = 0;
int m_irq_enable; int m_irq_enable;
static const device_timer_id TIMER_IRQ = 0; static const device_timer_id TIMER_IRQ = 0;
@ -230,7 +230,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
private: private:
u8 m_chr_mask, m_chr_match; u8 m_chr_mask = 0, m_chr_match;
}; };
// ======================> nes_hengg_shjy3_device // ======================> nes_hengg_shjy3_device

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@ -62,12 +62,12 @@ private:
void moton(int state); void moton(int state);
int m_paging; int m_paging = 0;
int m_ma16; int m_ma16 = 0;
int m_mpm; int m_mpm = 0;
int m_fdc_att; int m_fdc_att = 0;
int m_fdc_int; int m_fdc_int = 0;
int m_pa15; int m_pa15 = 0;
}; };

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@ -46,13 +46,13 @@ private:
uint32_t bytes_per_block; uint32_t bytes_per_block;
int lba, cur_sector; int lba, cur_sector;
required_device<cdrom_image_device> image; required_device<cdrom_image_device> image;
uint8_t mode_data[12]; uint8_t mode_data[12]{};
char manufacturer[8]; char manufacturer[8]{};
char product[16]; char product[16]{};
char revision[4]; char revision[4]{};
uint8_t inquiry_data; uint8_t inquiry_data = 0;
uint8_t compliance; uint8_t compliance = 0;
void return_no_cd(); void return_no_cd();
static int to_msf(int frame); static int to_msf(int frame);

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@ -32,7 +32,7 @@ private:
required_device<m37710s4_device> m_cdcpu; required_device<m37710s4_device> m_cdcpu;
u8 m_mystery_address; u8 m_mystery_address = 0;
}; };
class cdr4210_device : public cw7501_device class cdr4210_device : public cw7501_device

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@ -40,8 +40,8 @@ private:
std::vector<uint8_t> m_vram; std::vector<uint8_t> m_vram;
uint32_t m_vbl_disable, m_palette[2]; uint32_t m_vbl_disable, m_palette[2];
int m_prot_state; int m_prot_state = 0;
int m_toggle; int m_toggle = 0;
}; };
// device type definition // device type definition

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@ -37,13 +37,13 @@ protected:
struct nbfilectx struct nbfilectx
{ {
uint32_t curcmd; uint32_t curcmd = 0;
char filename[128]; char filename[128]{};
std::string curdir; std::string curdir;
osd::directory::ptr dirp; osd::directory::ptr dirp;
osd_file::ptr fd; osd_file::ptr fd;
uint64_t filelen; uint64_t filelen = 0;
uint32_t bytecount; uint32_t bytecount = 0;
}; };
nubus_image_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock); nubus_image_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock);

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@ -46,8 +46,8 @@ private:
required_ioport_array<16> m_matrix; required_ioport_array<16> m_matrix;
output_finder<3> m_leds; output_finder<3> m_leds;
u8 m_porta; u8 m_porta = 0;
u8 m_portc; u8 m_portc = 0;
}; };
// device type definition // device type definition

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@ -103,7 +103,7 @@ private:
const uint32_t m_bram_size = 0x800*4; const uint32_t m_bram_size = 0x800*4;
uint8_t m_bram[0x800*4]; uint8_t m_bram[0x800*4];
uint8_t m_bram_locked; uint8_t m_bram_locked = false;
}; };

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@ -48,7 +48,7 @@ protected:
private: private:
required_device<ins8250_device> m_uart; required_device<ins8250_device> m_uart;
uint8_t m_vector; uint8_t m_vector = 0;
}; };

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@ -60,8 +60,8 @@ private:
memory_share_creator<uint8_t> m_nvram; memory_share_creator<uint8_t> m_nvram;
required_ioport m_io_sw1; required_ioport m_io_sw1;
bool m_sw1; bool m_sw1 = false;
bool m_ncc1_out; bool m_ncc1_out = false;
}; };

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@ -50,12 +50,12 @@ protected:
private: private:
std::unique_ptr<uint8_t[]> m_videoram_base; std::unique_ptr<uint8_t[]> m_videoram_base;
uint8_t *m_videoram; uint8_t *m_videoram = nullptr;
uint16_t m_cr; uint16_t m_cr = 0;
uint16_t m_dr; uint16_t m_dr = 0;
uint16_t m_ar; uint16_t m_ar = 0;
uint16_t m_ct; uint16_t m_ct = 0;
}; };

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@ -61,17 +61,17 @@ private:
int m_rxvec; int m_rxvec;
int m_txvec; int m_txvec;
device_image_interface *m_fd; device_image_interface *m_fd = nullptr;
line_state m_rxrdy; line_state m_rxrdy{};
line_state m_txrdy; line_state m_txrdy{};
uint16_t m_rcsr; uint16_t m_rcsr = 0;
uint16_t m_rbuf; uint16_t m_rbuf = 0;
uint16_t m_tcsr; uint16_t m_tcsr = 0;
uint16_t m_tbuf; uint16_t m_tbuf = 0;
const char *pc11_regnames[4]; const char *pc11_regnames[4]{};
}; };

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@ -57,8 +57,8 @@ private:
void c000_w(u8 data) { m_c000_latch = data; }; void c000_w(u8 data) { m_c000_latch = data; };
void m6803_mem(address_map &map); void m6803_mem(address_map &map);
int m_rx_state; int m_rx_state = 0;
u8 m_c000_latch; u8 m_c000_latch = 0;
}; };
mockingboard_d_device::mockingboard_d_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock) mockingboard_d_device::mockingboard_d_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)

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@ -36,10 +36,10 @@ private:
required_ioport_array<8> m_matrix[4]; required_ioport_array<8> m_matrix[4];
output_finder<3> m_leds; output_finder<3> m_leds;
bool m_t1; bool m_t1 = false;
u8 m_bus; u8 m_bus = 0;
u8 m_p1; u8 m_p1 = 0;
u8 m_p2; u8 m_p2 = 0;
}; };
DECLARE_DEVICE_TYPE(RTPC_KBD, rtpc_kbd_device) DECLARE_DEVICE_TYPE(RTPC_KBD, rtpc_kbd_device)

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@ -34,7 +34,7 @@ public:
protected: protected:
device_saturn_control_port_interface(const machine_config &mconfig, device_t &device); device_saturn_control_port_interface(const machine_config &mconfig, device_t &device);
uint8_t m_ctrl_id; uint8_t m_ctrl_id = 0;
saturn_control_port_device *m_port; saturn_control_port_device *m_port;
}; };

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@ -470,36 +470,36 @@ protected:
uint32_t m_itri_relx; uint32_t m_itri_relx;
uint32_t m_itri_rely; uint32_t m_itri_rely;
uint32_t m_itri_relz; uint32_t m_itri_relz;
uint32_t m_itri_r; uint32_t m_itri_r = 0;
uint32_t m_itri_g; uint32_t m_itri_g = 0;
uint32_t m_itri_b; uint32_t m_itri_b = 0;
uint32_t m_itri_a; uint32_t m_itri_a = 0;
uint32_t m_iquad_absx; uint32_t m_iquad_absx = 0;
uint32_t m_iquad_absy; uint32_t m_iquad_absy = 0;
uint32_t m_iquad_absz; uint32_t m_iquad_absz = 0;
uint32_t m_iquad_relx; uint32_t m_iquad_relx = 0;
uint32_t m_iquad_rely; uint32_t m_iquad_rely = 0;
uint32_t m_iquad_relz; uint32_t m_iquad_relz = 0;
uint32_t m_iquad_r; uint32_t m_iquad_r = 0;
uint32_t m_iquad_g; uint32_t m_iquad_g = 0;
uint32_t m_iquad_b; uint32_t m_iquad_b = 0;
uint32_t m_iquad_a; uint32_t m_iquad_a = 0;
uint32_t m_irect_absx; uint32_t m_irect_absx = 0;
uint32_t m_irect_absy; uint32_t m_irect_absy = 0;
uint32_t m_irect_absz; uint32_t m_irect_absz = 0;
uint32_t m_irect_relx; uint32_t m_irect_relx = 0;
uint32_t m_irect_rely; uint32_t m_irect_rely = 0;
uint32_t m_irect_relz; uint32_t m_irect_relz = 0;
uint32_t m_irect_r; uint32_t m_irect_r = 0;
uint32_t m_irect_g; uint32_t m_irect_g = 0;
uint32_t m_irect_b; uint32_t m_irect_b = 0;
uint32_t m_irect_a; uint32_t m_irect_a = 0;
std::unique_ptr<vertex[]> m_prim_buf; std::unique_ptr<vertex[]> m_prim_buf;
uint32_t m_vertex_count; uint32_t m_vertex_count = 0;
uint32_t m_curr_prim_type; uint32_t m_curr_prim_type = 0;
}; };
uint32_t m_thc_misc; uint32_t m_thc_misc;

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@ -100,12 +100,12 @@ protected:
// internal state // internal state
required_device<sparc_base_device> m_maincpu; required_device<sparc_base_device> m_maincpu;
required_address_space m_type1space; required_address_space m_type1space;
address_space *m_space; address_space *m_space = nullptr;
devcb_write_line::array<7> m_irq_cb; devcb_write_line::array<7> m_irq_cb;
devcb_write32 m_buserr; devcb_write32 m_buserr;
device_sbus_card_interface *m_device_list[3]; device_sbus_card_interface *m_device_list[3]{};
private: private:
void slot1_timeout_map(address_map &map); void slot1_timeout_map(address_map &map);
@ -148,7 +148,7 @@ protected:
optional_device<sbus_device> m_sbus_finder; optional_device<sbus_device> m_sbus_finder;
sbus_device *m_sbus; sbus_device *m_sbus;
const char *m_sbus_slottag; const char *m_sbus_slottag = nullptr;
int m_slot; int m_slot;
uint32_t m_base; uint32_t m_base;
}; };

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@ -24,7 +24,7 @@ protected:
private: private:
required_device<harddisk_image_device> m_image0; required_device<harddisk_image_device> m_image0;
required_device<harddisk_image_device> m_image1; required_device<harddisk_image_device> m_image1;
hard_disk_file::info m_param[2]; hard_disk_file::info m_param[2]{};
}; };
DECLARE_DEVICE_TYPE(OMTI5100, omti5100_device) DECLARE_DEVICE_TYPE(OMTI5100, omti5100_device)

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@ -195,7 +195,7 @@ protected:
int m_msg; int m_msg;
int m_req; int m_req;
int m_ack; int m_ack;
int m_atn; int m_atn = 0;
int m_rst; int m_rst;
int m_data0; int m_data0;
int m_data1; int m_data1;

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@ -37,7 +37,7 @@ protected:
char m_manufacturer[8]; char m_manufacturer[8];
char m_product[16]; char m_product[16];
char m_revision[4]; char m_revision[4];
uint8_t m_data; uint8_t m_data = 0;
}; };
class dec_rrd45_device : public scsicd512_device class dec_rrd45_device : public scsicd512_device

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@ -392,8 +392,8 @@ protected:
virtual void device_start() override; virtual void device_start() override;
virtual void device_reset() override; virtual void device_reset() override;
uint8_t m_gamesel; uint8_t m_gamesel = 0;
uint8_t m_readxor; uint8_t m_readxor = 0;
}; };
@ -420,7 +420,7 @@ protected:
virtual void device_reset() override; virtual void device_reset() override;
private: private:
uint8_t m_block; uint8_t m_block = 0;
}; };
@ -447,7 +447,7 @@ protected:
virtual void device_reset() override; virtual void device_reset() override;
private: private:
uint8_t m_block; uint8_t m_block = 0;
}; };
class sega8_x_terminator_device : public sega8_rom_device class sega8_x_terminator_device : public sega8_rom_device

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@ -72,7 +72,7 @@ public:
protected: protected:
device_sg1000_expansion_slot_interface(const machine_config &mconfig, device_t &device); device_sg1000_expansion_slot_interface(const machine_config &mconfig, device_t &device);
sg1000_expansion_slot_device *m_port; sg1000_expansion_slot_device *m_port = nullptr;
}; };

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@ -139,8 +139,8 @@ private:
u8 m_iram_write_snes, m_iram_write_sa1; u8 m_iram_write_snes, m_iram_write_sa1;
// $2230-$2231 // $2230-$2231
u8 m_dma_ctrl, m_dma_ccparam; u8 m_dma_ctrl, m_dma_ccparam;
u8 m_dma_cconv_size; u8 m_dma_cconv_size = 0;
u8 m_dma_cconv_bits; u8 m_dma_cconv_bits = 8;
// DMA Control (DCNT) // DMA Control (DCNT)
inline const bool DCNT_DMAEN() { return BIT(m_dma_ctrl, 7); } // DMA Enable control inline const bool DCNT_DMAEN() { return BIT(m_dma_ctrl, 7); } // DMA Enable control
//inline const bool DCNT_DPRIO() { return BIT(m_dma_ctrl, 6); } // Processing priority between SA-1 CPU and DMA; Not emulated currently //inline const bool DCNT_DPRIO() { return BIT(m_dma_ctrl, 6); } // Processing priority between SA-1 CPU and DMA; Not emulated currently

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@ -73,8 +73,8 @@ protected:
struct SDD1_PEM_ContextInfo struct SDD1_PEM_ContextInfo
{ {
uint8_t status; uint8_t status = 0;
uint8_t MPS; uint8_t MPS = 0;
}; };
class SDD1_PEM //Probability Estimation Module class SDD1_PEM //Probability Estimation Module
@ -167,8 +167,8 @@ protected:
struct struct
{ {
uint32_t addr; // $43x2-$43x4 -- DMA transfer address uint32_t addr = 0; // $43x2-$43x4 -- DMA transfer address
uint16_t size; // $43x5-$43x6 -- DMA transfer size uint16_t size = 0; // $43x5-$43x6 -- DMA transfer size
} m_dma[8]; } m_dma[8];
std::unique_ptr<SDD1_emu> m_sdd1emu; std::unique_ptr<SDD1_emu> m_sdd1emu;
@ -176,9 +176,9 @@ protected:
struct struct
{ {
std::unique_ptr<uint8_t[]> data; // pointer to decompressed S-DD1 data (65536 bytes) std::unique_ptr<uint8_t[]> data; // pointer to decompressed S-DD1 data (65536 bytes)
uint16_t offset; // read index into S-DD1 decompression buffer uint16_t offset = 0; // read index into S-DD1 decompression buffer
uint32_t size; // length of data buffer; reads decrement counter, set ready to false at 0 uint32_t size = 0; // length of data buffer; reads decrement counter, set ready to false at 0
uint8_t ready; // 1 when data[] is valid; 0 to invoke sdd1emu.decompress() uint8_t ready = 0; // 1 when data[] is valid; 0 to invoke sdd1emu.decompress()
} m_buffer; } m_buffer;
}; };

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@ -60,10 +60,10 @@ protected:
required_device_array<floppy_connector, 4> m_floppy; required_device_array<floppy_connector, 4> m_floppy;
required_device<spectrum_expansion_slot_device> m_exp; required_device<spectrum_expansion_slot_device> m_exp;
int m_romcs; int m_romcs = 0;
u8 m_masterdisable; u8 m_masterdisable = 0;
u8 m_control; u8 m_control;
bool m_motor_active; bool m_motor_active = false;
void fdc_hld_w(int state); void fdc_hld_w(int state);
virtual void motors_control(); virtual void motors_control();

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@ -86,9 +86,9 @@ protected:
void fdc_drq_w(int state); void fdc_drq_w(int state);
virtual void nmi_check() override; virtual void nmi_check() override;
uint8_t m_control; uint8_t m_control = 0;
int m_intrq; int m_intrq = 0;
int m_drq; int m_drq = 0;
}; };
class spectrum_d80_device : class spectrum_d80_device :

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@ -56,8 +56,8 @@ protected:
required_device_array<floppy_connector, 4> m_floppy; required_device_array<floppy_connector, 4> m_floppy;
required_device<spectrum_expansion_slot_device> m_exp; required_device<spectrum_expansion_slot_device> m_exp;
int m_romcs; int m_romcs = 0;
// u8 m_control; // u8 m_control = 0;
}; };
class spectrum_spdos_device : class spectrum_spdos_device :

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@ -46,8 +46,8 @@ protected:
required_memory_region m_rom; required_memory_region m_rom;
required_device<centronics_device> m_centronics; required_device<centronics_device> m_centronics;
int m_romcs; int m_romcs = 0;
int m_busy; int m_busy = 0;
}; };
class spectrum_lprint3_device : class spectrum_lprint3_device :
@ -87,8 +87,8 @@ protected:
required_device<rs232_port_device> m_rs232; required_device<rs232_port_device> m_rs232;
required_device<spectrum_expansion_slot_device> m_exp; required_device<spectrum_expansion_slot_device> m_exp;
int m_romcs; int m_romcs = 0;
int m_busy; int m_busy = 0;
}; };
class spectrum_kempcentrs_device : class spectrum_kempcentrs_device :
@ -115,7 +115,7 @@ protected:
required_device<centronics_device> m_centronics; required_device<centronics_device> m_centronics;
int m_busy; int m_busy = 0;
}; };
class spectrum_kempcentre_device : class spectrum_kempcentre_device :
@ -150,9 +150,9 @@ protected:
required_memory_region m_rom; required_memory_region m_rom;
required_device<centronics_device> m_centronics; required_device<centronics_device> m_centronics;
int m_active; int m_active = 0;
int m_romcs; int m_romcs = 0;
int m_busy; int m_busy = 0;
}; };
class spectrum_kempcentreu_device : class spectrum_kempcentreu_device :

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@ -53,8 +53,8 @@ protected:
required_memory_region m_rom; required_memory_region m_rom;
required_device<spectrum_expansion_slot_device> m_exp; required_device<spectrum_expansion_slot_device> m_exp;
int m_romcs; int m_romcs = 0;
int m_nmi_pending; int m_nmi_pending = 0;
std::unique_ptr<uint8_t[]> m_ram; std::unique_ptr<uint8_t[]> m_ram;
}; };
@ -143,7 +143,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
virtual void device_reset() override; virtual void device_reset() override;
int m_hidden; int m_hidden = 0;
}; };
class spectrum_mface128v1_device : public spectrum_mface128_base_device class spectrum_mface128v1_device : public spectrum_mface128_base_device
@ -163,7 +163,7 @@ protected:
virtual uint8_t iorq_r(offs_t offset) override; virtual uint8_t iorq_r(offs_t offset) override;
virtual void iorq_w(offs_t offset, uint8_t data) override; virtual void iorq_w(offs_t offset, uint8_t data) override;
int m_d3_ff; // no initial state int m_d3_ff = 0; // no initial state
}; };
class spectrum_mface128_device : public spectrum_mface128v1_device class spectrum_mface128_device : public spectrum_mface128v1_device
@ -200,8 +200,8 @@ protected:
virtual void iorq_w(offs_t offset, uint8_t data) override; virtual void iorq_w(offs_t offset, uint8_t data) override;
private: private:
uint8_t m_reg_file[4]; // no initial state uint8_t m_reg_file[4]{}; // no initial state
int m_disable; int m_disable = 0;
}; };
class spectrum_mprint_device : public spectrum_mface128_base_device class spectrum_mprint_device : public spectrum_mface128_base_device
@ -227,7 +227,7 @@ private:
required_device<centronics_device> m_centronics; required_device<centronics_device> m_centronics;
int m_busy; int m_busy = 0;
}; };

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@ -60,7 +60,7 @@ protected:
required_device_array<floppy_connector, 2> m_floppy; required_device_array<floppy_connector, 2> m_floppy;
required_device<centronics_device> m_centronics; required_device<centronics_device> m_centronics;
int m_romcs; int m_romcs = 0;
uint8_t m_ram[8 * 1024]; uint8_t m_ram[8 * 1024];
bool m_centronics_busy; bool m_centronics_busy;
}; };

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@ -64,10 +64,10 @@ protected:
required_device<rs232_port_device> m_rs232; required_device<rs232_port_device> m_rs232;
required_ioport m_joy; required_ioport m_joy;
int m_romcs; int m_romcs = 0;
u8 m_ram[0x2000]; u8 m_ram[0x2000]{};
u16 m_rombank; u16 m_rombank = 0;
u8 m_control; u8 m_control = 0;
}; };
class spectrum_swiftdisc2_device : class spectrum_swiftdisc2_device :

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@ -70,8 +70,8 @@ private:
optional_device<pia6821_device> m_pia; optional_device<pia6821_device> m_pia;
optional_device<ide_controller_device> m_ide; optional_device<ide_controller_device> m_ide;
uint8_t m_pia_porta; uint8_t m_pia_porta = 0;
uint8_t m_pia_portb; uint8_t m_pia_portb = 0;
uint8_t pia_a_r(); uint8_t pia_a_r();
uint8_t pia_b_r(); uint8_t pia_b_r();

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@ -64,8 +64,8 @@ private:
int m_beeper_state; int m_beeper_state;
uint8_t m_drive_control; uint8_t m_drive_control;
int m_irq_enable; int m_irq_enable = 0;
int m_drq_enable; int m_drq_enable = 0;
}; };

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@ -51,7 +51,7 @@ protected:
private: private:
required_device<tanbus_device> m_tanbus; required_device<tanbus_device> m_tanbus;
int m_bus_num; int m_bus_num = 0;
}; };
// device type definition // device type definition

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@ -112,7 +112,7 @@ private:
const std::string m_pathname; const std::string m_pathname;
}; };
bool m_readrom; bool m_readrom = false;
int m_pcbtype; int m_pcbtype;
int m_slot; int m_slot;
int get_index_from_tagname(); int get_index_from_tagname();
@ -155,12 +155,12 @@ protected:
template <typename Format, typename... Params> void logerror(Format &&fmt, Params &&... args) const { m_cart->logerror(fmt, args...); } template <typename Format, typename... Params> void logerror(Format &&fmt, Params &&... args) const { m_cart->logerror(fmt, args...); }
ti99_cartridge_device* m_cart; ti99_cartridge_device* m_cart;
tmc0430_device* m_grom[5]; tmc0430_device* m_grom[5]{};
bool m_grom_idle; bool m_grom_idle;
int m_grom_size; int m_grom_size;
int m_rom_size; int m_rom_size;
int m_ram_size; int m_ram_size;
int m_bank_mask; int m_bank_mask = 0;
uint8_t* m_rom_ptr; uint8_t* m_rom_ptr;
uint8_t* m_ram_ptr; uint8_t* m_ram_ptr;

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@ -99,7 +99,7 @@ protected:
virtual void device_config_complete() override; virtual void device_config_complete() override;
gromport_device* m_gromport; gromport_device* m_gromport;
bool m_grom_selected; bool m_grom_selected = false;
}; };
} // end namespace bus::ti99::gromport } // end namespace bus::ti99::gromport

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@ -45,11 +45,11 @@ protected:
virtual ioport_constructor device_input_ports() const override; virtual ioport_constructor device_input_ports() const override;
private: private:
bool m_readrom; bool m_readrom = false;
int m_active_slot; int m_active_slot;
int m_fixed_slot; int m_fixed_slot;
int m_next_free_slot; int m_next_free_slot;
ti99_cartridge_device* m_cartridge[NUMBER_OF_CARTRIDGE_SLOTS]; ti99_cartridge_device* m_cartridge[NUMBER_OF_CARTRIDGE_SLOTS]{};
void set_slot(int slotnumber); void set_slot(int slotnumber);
int get_active_slot(bool changebase, offs_t offset); int get_active_slot(bool changebase, offs_t offset);

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@ -236,7 +236,7 @@ private:
video_waitstate_generator m_vidws; video_waitstate_generator m_vidws;
// Pointer to mainboard // Pointer to mainboard
mainboard8_device* m_mainboard; mainboard8_device* m_mainboard = nullptr;
}; };
/* /*
@ -323,7 +323,7 @@ private:
int m_msast = 0; int m_msast = 0;
// Pointer to mainboard // Pointer to mainboard
mainboard8_device* m_mainboard; mainboard8_device* m_mainboard = nullptr;
}; };
/* /*
@ -381,7 +381,7 @@ private:
uint8_t* m_sram = nullptr; uint8_t* m_sram = nullptr;
// Pointer to mainboard // Pointer to mainboard
mainboard8_device* m_mainboard; mainboard8_device* m_mainboard = nullptr;
// Keep the system ready state // Keep the system ready state
int m_srdy = 0; int m_srdy = 0;

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@ -40,8 +40,8 @@ protected:
virtual DECLARE_WRITE_LINE_MEMBER( data_write ) override; virtual DECLARE_WRITE_LINE_MEMBER( data_write ) override;
private: private:
emu_timer *m_poll_timer; emu_timer *m_poll_timer = nullptr;
emu_timer *m_send_timer; emu_timer *m_send_timer = nullptr;
static constexpr unsigned KEYQUEUESIZE = 256; static constexpr unsigned KEYQUEUESIZE = 256;
static constexpr unsigned MAXKEYMSGLENGTH = 10; static constexpr unsigned MAXKEYMSGLENGTH = 10;
@ -55,7 +55,7 @@ private:
required_ioport_array<8> m_keys; required_ioport_array<8> m_keys;
int m_queue_length; int m_queue_length;
int m_queue_head; int m_queue_head = 0;
uint8_t m_queue[KEYQUEUESIZE]; uint8_t m_queue[KEYQUEUESIZE];
uint32_t m_key_state_save[4]; uint32_t m_key_state_save[4];
int m_autorepeat_code; int m_autorepeat_code;
@ -63,22 +63,22 @@ private:
bool m_fake_shift_state; bool m_fake_shift_state;
bool m_fake_unshift_state; bool m_fake_unshift_state;
bool m_left_shift; bool m_left_shift = false;
bool m_right_shift; bool m_right_shift = false;
bool m_left_ctrl; bool m_left_ctrl = false;
bool m_right_ctrl; bool m_right_ctrl = false;
bool m_left_alt; bool m_left_alt = false;
bool m_altgr; bool m_altgr = false;
bool m_numlock; bool m_numlock = false;
bool m_resetting; bool m_resetting;
line_state m_clock_line; line_state m_clock_line;
line_state m_data_line; line_state m_data_line;
int m_reset_timer; int m_reset_timer = 0;
int m_shift_reg; int m_shift_reg = 0;
int m_shift_count; int m_shift_count = 0;
}; };

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@ -113,7 +113,7 @@ private:
required_device<ram_device> m_buffer_ram; required_device<ram_device> m_buffer_ram;
// Link to the attached floppy drives // Link to the attached floppy drives
floppy_image_device* m_floppy[4]; floppy_image_device* m_floppy[4]{};
// Currently selected floppy drive (1-4, 0=none) // Currently selected floppy drive (1-4, 0=none)
int m_sel_floppy; int m_sel_floppy;

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@ -90,7 +90,7 @@ protected:
void operate_ready_line(); void operate_ready_line();
// Link to the attached floppy drives // Link to the attached floppy drives
floppy_image_device* m_floppy[4]; floppy_image_device* m_floppy[4]{};
// Motor monoflop // Motor monoflop
required_device<ttl74123_device> m_motormf; required_device<ttl74123_device> m_motormf;

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@ -42,11 +42,11 @@ public:
protected: protected:
struct evpc_palette struct evpc_palette
{ {
uint8_t read_index, write_index, mask; uint8_t read_index = 0, write_index = 0, mask = 0;
int read; int read = 0;
int state; int state = 0;
struct { uint8_t red, green, blue; } color[0x100]; struct { uint8_t red = 0, green = 0, blue = 0; } color[0x100];
//int dirty; //int dirty = 0;
}; };
void device_start() override; void device_start() override;
@ -66,7 +66,7 @@ private:
DECLARE_WRITE_LINE_MEMBER( video_interrupt_in ); DECLARE_WRITE_LINE_MEMBER( video_interrupt_in );
int m_address; int m_address = 0;
int m_dsr_page; int m_dsr_page;
bool m_inDsrArea; bool m_inDsrArea;
bool m_novram_accessed; bool m_novram_accessed;

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@ -100,10 +100,10 @@ private:
required_device<mm58274c_device> m_clock; required_device<mm58274c_device> m_clock;
// Link to the attached floppy drives // Link to the attached floppy drives
floppy_image_device* m_floppy_unit[4]; floppy_image_device* m_floppy_unit[4]{};
// Link to the attached hard disks // Link to the attached hard disks
mfm_harddisk_device* m_harddisk_unit[3]; mfm_harddisk_device* m_harddisk_unit[3]{};
// Currently selected floppy drive // Currently selected floppy drive
floppy_image_device* m_current_floppy; floppy_image_device* m_current_floppy;

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@ -77,8 +77,8 @@ private:
int m_cru_base_phoenix; int m_cru_base_phoenix;
// Debugging // Debugging
int m_current_bank; int m_current_bank = 0;
int m_current_page; int m_current_page = 0;
}; };
} // end namespace bus::ti99::peb } // end namespace bus::ti99::peb

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@ -39,7 +39,7 @@ protected:
private: private:
bool access_enabled(offs_t offset); bool access_enabled(offs_t offset);
required_device<ram_device> m_ram; required_device<ram_device> m_ram;
uint8_t m_switches; uint8_t m_switches = 0;
}; };
} // end namespace bus::ti99::peb } // end namespace bus::ti99::peb

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@ -86,7 +86,7 @@ private:
uint8_t* m_dsrrom; uint8_t* m_dsrrom;
// Link to the attached floppy drives // Link to the attached floppy drives
floppy_image_device* m_floppy[4]; floppy_image_device* m_floppy[4]{};
// Debugger accessors // Debugger accessors
void debug_read(offs_t offset, uint8_t* value); void debug_read(offs_t offset, uint8_t* value);

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@ -191,7 +191,7 @@ protected:
device_ti99_peribox_card_interface(const machine_config &mconfig, device_t &device); device_ti99_peribox_card_interface(const machine_config &mconfig, device_t &device);
virtual void interface_config_complete() override; virtual void interface_config_complete() override;
peribox_slot_device *m_slot; // using a link to the slot for callbacks peribox_slot_device *m_slot = nullptr; // using a link to the slot for callbacks
int m_senila; int m_senila;
int m_senilb; int m_senilb;

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@ -43,9 +43,9 @@ private:
void device_add_mconfig(machine_config &config) override; void device_add_mconfig(machine_config &config) override;
// Settings // Settings
bool m_active; bool m_active = false;
uint16_t m_crubase; uint16_t m_crubase = 0;
bool m_pgramplus; bool m_pgramplus = false;
ioport_constructor device_input_ports() const override; ioport_constructor device_input_ports() const override;

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@ -61,13 +61,13 @@ private:
required_device<nscsi_bus_device> m_scsibus; required_device<nscsi_bus_device> m_scsibus;
// DSR ROM // DSR ROM
uint8_t* m_eprom; uint8_t* m_eprom = nullptr;
// Recent address // Recent address
int m_address; int m_address = 0;
// Settings // Settings
int m_sw2; int m_sw2 = 0;
// Latches for the lines // Latches for the lines
// Should be removed and accessor functions be added to ncr5380 // Should be removed and accessor functions be added to ncr5380

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@ -87,7 +87,7 @@ private:
bool m_inDsrArea; bool m_inDsrArea;
// When true the CPU is halted while DRQ/IRQ are true. // When true the CPU is halted while DRQ/IRQ are true.
bool m_WAITena; bool m_WAITena = false;
// WD chip selected // WD chip selected
bool m_WDsel; bool m_WDsel;
@ -105,7 +105,7 @@ private:
uint8_t* m_dsrrom; uint8_t* m_dsrrom;
// Link to the attached floppy drives // Link to the attached floppy drives
floppy_image_device* m_floppy[3]; floppy_image_device* m_floppy[3]{};
// Currently selected floppy drive // Currently selected floppy drive
int m_sel_floppy; int m_sel_floppy;

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@ -64,23 +64,23 @@ private:
bool m_portaccess; bool m_portaccess;
// DSR ROM // DSR ROM
uint8_t* m_eprom; uint8_t* m_eprom = nullptr;
// Websocket support // Websocket support
std::unique_ptr<webpp::ws_client> m_wsclient; std::unique_ptr<webpp::ws_client> m_wsclient;
std::shared_ptr<webpp::ws_client::SendStream> m_send_stream; std::shared_ptr<webpp::ws_client::SendStream> m_send_stream;
std::unique_ptr<u8[]> m_rpimessage; std::unique_ptr<u8[]> m_rpimessage;
int m_msgindex; int m_msgindex = 0;
int m_msglength; int m_msglength = 0;
emu_timer* m_restart_timer; emu_timer* m_restart_timer = nullptr;
int m_attempts; int m_attempts = 0;
bool m_connected; bool m_connected = 0;
// Computer interface // Computer interface
u8 m_tc; u8 m_tc = 0;
u8 m_td; u8 m_td = 0;
u8 m_rc; u8 m_rc = 0;
u8 m_rd; u8 m_rd = 0;
}; };
/* /*

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@ -63,7 +63,7 @@ private:
int m_page; int m_page;
// Is the SRAM buffered? // Is the SRAM buffered?
bool m_srammap; bool m_srammap = false;
// RTC type // RTC type
int m_rtctype; int m_rtctype;
@ -77,7 +77,7 @@ private:
void decode(offs_t offset, bool& mmap, bool& sramsel, bool& xramsel, bool& rtcsel, bool& cs1fx, bool& cs3fx); void decode(offs_t offset, bool& mmap, bool& sramsel, bool& xramsel, bool& rtcsel, bool& cs1fx, bool& cs3fx);
int m_rtc_int; int m_rtc_int = 0;
}; };
} // end namespace bus::ti99::peb } // end namespace bus::ti99::peb

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@ -91,7 +91,7 @@ protected:
// device-level overrides // device-level overrides
virtual void device_start() override; virtual void device_start() override;
device_tmc600_eurobus_card_interface *m_card; device_tmc600_eurobus_card_interface *m_card = nullptr;
}; };

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@ -30,13 +30,13 @@ protected:
static constexpr device_timer_id TIMER_OSC = 0; static constexpr device_timer_id TIMER_OSC = 0;
struct df_t { struct df_t {
uint8_t top; uint8_t top = 0;
uint8_t bottom; uint8_t bottom = 0;
uint8_t low; uint8_t low = 0;
uint8_t high; uint8_t high = 0;
uint8_t flag; uint8_t flag = 0;
uint8_t music_mode; /* Only used by data fetchers 5,6, and 7 */ uint8_t music_mode = 0; /* Only used by data fetchers 5,6, and 7 */
uint8_t osc_clk; /* Only used by data fetchers 5,6, and 7 */ uint8_t osc_clk = 0; /* Only used by data fetchers 5,6, and 7 */
}; };
// device-level overrides // device-level overrides

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@ -118,7 +118,7 @@ protected:
// callbacks // callbacks
devcb_write_line m_vme_j1_callback; devcb_write_line m_vme_j1_callback;
device_vme_card_interface *m_card; device_vme_card_interface *m_card = nullptr;
}; };
DECLARE_DEVICE_TYPE(VME, vme_device) DECLARE_DEVICE_TYPE(VME, vme_device)
@ -195,12 +195,12 @@ protected:
virtual space_config_vector memory_space_config() const override; virtual space_config_vector memory_space_config() const override;
// internal state // internal state
cpu_device *m_maincpu; cpu_device *m_maincpu = nullptr;
// address spaces // address spaces
address_space *m_prgspace; address_space *m_prgspace = nullptr;
int m_prgwidth; int m_prgwidth = 0;
bool m_allocspaces; bool m_allocspaces = false;
const char *m_cputag; const char *m_cputag;

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@ -46,11 +46,11 @@ private:
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses // Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
memory_passthrough_handler m_rom_shadow_tap; memory_passthrough_handler m_rom_shadow_tap;
bool m_bus_error; bool m_bus_error = false;
emu_timer *m_bus_error_timer; emu_timer *m_bus_error_timer = nullptr;
uint8_t bim_irq_state; uint8_t bim_irq_state = 0;
int bim_irq_level; int bim_irq_level = 0;
DECLARE_WRITE_LINE_MEMBER(bim_irq_callback); DECLARE_WRITE_LINE_MEMBER(bim_irq_callback);
void update_irq_to_maincpu(); void update_irq_to_maincpu();

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@ -49,10 +49,10 @@ protected:
virtual void device_add_mconfig(machine_config &config) override; virtual void device_add_mconfig(machine_config &config) override;
virtual const tiny_rom_entry *device_rom_region() const override; virtual const tiny_rom_entry *device_rom_region() const override;
uint8_t bim_irq_state; uint8_t bim_irq_state = 0;
int bim_irq_level; int bim_irq_level = 0;
emu_timer *m_arbiter_start; // Need a startup delay because it is hooked up to the sense inputs of the PIT emu_timer *m_arbiter_start = nullptr; // Need a startup delay because it is hooked up to the sense inputs of the PIT
required_device<cpu_device> m_maincpu; required_device<cpu_device> m_maincpu;
@ -78,7 +78,7 @@ private:
required_device<mpcc68561_device> m_mpcc3; required_device<mpcc68561_device> m_mpcc3;
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses // Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
uint32_t *m_sysrom; uint32_t *m_sysrom = nullptr;
uint32_t m_sysram[2]; uint32_t m_sysram[2];
void update_irq_to_maincpu(); void update_irq_to_maincpu();
const fc_board_t m_board_id; const fc_board_t m_board_id;

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@ -48,7 +48,7 @@ private:
required_device<bim68153_device> m_bim; required_device<bim68153_device> m_bim;
// Pointer to System ROMs needed by bootvect_r // Pointer to System ROMs needed by bootvect_r
uint16_t *m_sysrom; uint16_t *m_sysrom = nullptr;
}; };
#endif // MAME_BUS_VME_VME_FCISIO_H #endif // MAME_BUS_VME_VME_FCISIO_H

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@ -30,8 +30,8 @@ protected:
void update_irq_to_maincpu(); void update_irq_to_maincpu();
uint8_t fdc_irq_state; uint8_t fdc_irq_state = 0;
uint8_t dmac_irq_state; uint8_t dmac_irq_state = 0;
private: private:
//dmac //dmac
@ -66,7 +66,7 @@ private:
uint8_t m_tcr; uint8_t m_tcr;
// Pointer to System ROMs needed by bootvect_r // Pointer to System ROMs needed by bootvect_r
uint16_t *m_sysrom; uint16_t *m_sysrom = nullptr;
}; };
#endif // MAME_BUS_VME_VME_FCSCSI_H #endif // MAME_BUS_VME_VME_FCSCSI_H

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@ -62,13 +62,13 @@ private:
// Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses // Pointer to System ROMs needed by bootvect_r and masking RAM buffer for post reset accesses
memory_passthrough_handler m_rom_shadow_tap; memory_passthrough_handler m_rom_shadow_tap;
uint16_t m_irq_state; uint16_t m_irq_state = 0;
uint16_t m_irq_mask; uint16_t m_irq_mask = 0;
uint8_t m_rtc_reg[16]; uint8_t m_rtc_reg[16]{};
bool m_rtc_hack; bool m_rtc_hack = false;
int m_fdcdrq_hack; int m_fdcdrq_hack = 0;
bool m_bus_error; bool m_bus_error = false;
emu_timer *m_bus_error_timer; emu_timer *m_bus_error_timer = nullptr;
uint32_t irq_state_r(offs_t offset); uint32_t irq_state_r(offs_t offset);
void irq_mask_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0); void irq_mask_w(offs_t offset, uint32_t data, uint32_t mem_mask = ~0);

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@ -31,7 +31,7 @@ protected:
virtual void device_start() override; virtual void device_start() override;
virtual void device_resolve_objects() override; virtual void device_resolve_objects() override;
uint32_t m_bank_offset; uint32_t m_bank_offset = 0;
}; };

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@ -66,7 +66,7 @@ protected:
private: private:
required_address_space m_iospace; required_address_space m_iospace;
device_vtech_ioexp_interface *m_module; device_vtech_ioexp_interface *m_module = nullptr;
}; };
// class representing interface-specific live ioexp device // class representing interface-specific live ioexp device

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@ -89,7 +89,7 @@ private:
devcb_write_line m_nmi_handler; devcb_write_line m_nmi_handler;
devcb_write_line m_reset_handler; devcb_write_line m_reset_handler;
device_vtech_memexp_interface *m_module; device_vtech_memexp_interface *m_module = nullptr;
}; };
// class representing interface-specific live memexp device // class representing interface-specific live memexp device

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@ -34,7 +34,7 @@ protected:
u16 m_io_regs[8]; u16 m_io_regs[8];
u32 m_base20, m_base30, m_base40; u32 m_base20, m_base30, m_base40;
u32 m_rom_mask; u32 m_rom_mask = 0;
// RTC // RTC
u8 m_rtc_setting; /* Timer setting byte */ u8 m_rtc_setting; /* Timer setting byte */
@ -122,14 +122,14 @@ private:
READ_MODE = 0, READ_MODE = 0,
COMMAND_MODE COMMAND_MODE
}; };
u8 m_flash_seq; u8 m_flash_seq = 0;
u8 m_flash_command; u8 m_flash_command = 0;
bool m_write_flash; bool m_write_flash = false;
bool m_writing_flash; bool m_writing_flash = false;
bool m_write_resetting; bool m_write_resetting = false;
u8 m_flash_mode; u8 m_flash_mode = 0;
u8 m_flash_status; u8 m_flash_status = 0;
u8 m_flash_count; u8 m_flash_count = 0;
}; };