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Implemented specific SH3/SH4 chips & pass the required endian into the constructor, SH4 internal registers now work when using big endian. The debugger is now aware that the SH3/SH4 has an MMU. [smf]

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smf- 2025-04-17 18:29:05 +01:00
parent 7fc77f3f4c
commit b26662f1bb
31 changed files with 7459 additions and 2109 deletions
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2367
src/devices/cpu/sh/sh3comn.cpp
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File diff suppressed because it is too large Load Diff

73
src/devices/cpu/sh/sh3comn.h
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@ -22,77 +22,4 @@
#define SH3_PORT_K (0x19*8)
#define SH3_PORT_L (0x1a*8)
/* SH3 lower area regs */
#define SH3_LOWER_REGBASE (0x04000000)
#define SH3_LOWER_REGEND (0x07ffffff)
#define INTEVT2 ((0x4000000 - SH3_LOWER_REGBASE)/4)
#define IRR0_IRR1 ((0x4000004 - SH3_LOWER_REGBASE)/4)
#define PINTER_IPRC ((0x4000014 - SH3_LOWER_REGBASE)/4)
#define SH3_SAR0_ADDR ((0x4000020 - SH3_LOWER_REGBASE)/4)
#define SH3_DAR0_ADDR ((0x4000024 - SH3_LOWER_REGBASE)/4)
#define SH3_DMATCR0_ADDR ((0x4000028 - SH3_LOWER_REGBASE)/4)
#define SH3_CHCR0_ADDR ((0x400002c - SH3_LOWER_REGBASE)/4)
#define SH3_SAR1_ADDR ((0x4000030 - SH3_LOWER_REGBASE)/4)
#define SH3_DAR1_ADDR ((0x4000034 - SH3_LOWER_REGBASE)/4)
#define SH3_DMATCR1_ADDR ((0x4000038 - SH3_LOWER_REGBASE)/4)
#define SH3_CHCR1_ADDR ((0x400003c - SH3_LOWER_REGBASE)/4)
#define SH3_SAR2_ADDR ((0x4000040 - SH3_LOWER_REGBASE)/4)
#define SH3_DAR2_ADDR ((0x4000044 - SH3_LOWER_REGBASE)/4)
#define SH3_DMATCR2_ADDR ((0x4000048 - SH3_LOWER_REGBASE)/4)
#define SH3_CHCR2_ADDR ((0x400004c - SH3_LOWER_REGBASE)/4)
#define SH3_SAR3_ADDR ((0x4000050 - SH3_LOWER_REGBASE)/4)
#define SH3_DAR3_ADDR ((0x4000054 - SH3_LOWER_REGBASE)/4)
#define SH3_DMATCR3_ADDR ((0x4000058 - SH3_LOWER_REGBASE)/4)
#define SH3_CHCR3_ADDR ((0x400005c - SH3_LOWER_REGBASE)/4)
#define SH3_DMAOR_ADDR ((0x4000060 - SH3_LOWER_REGBASE)/4)
#define PCCR_PDCR ((0x4000104 - SH3_LOWER_REGBASE)/4)
#define PECR_PFCR ((0x4000108 - SH3_LOWER_REGBASE)/4)
#define PGCR_PHCR ((0x400010c - SH3_LOWER_REGBASE)/4)
#define PJCR_PKCR ((0x4000110 - SH3_LOWER_REGBASE)/4)
#define PLCR_SCPCR ((0x4000114 - SH3_LOWER_REGBASE)/4)
#define PADR_PBDR ((0x4000120 - SH3_LOWER_REGBASE)/4)
#define PCDR_PDDR ((0x4000124 - SH3_LOWER_REGBASE)/4)
#define PEDR_PFDR ((0x4000128 - SH3_LOWER_REGBASE)/4)
#define PGDR_PHDR ((0x400012c - SH3_LOWER_REGBASE)/4)
#define PJDR_PKDR ((0x4000130 - SH3_LOWER_REGBASE)/4)
#define PLDR_SCPDR ((0x4000134 - SH3_LOWER_REGBASE)/4)
#define SCSMR2_SCBRR2 ((0x4000150 - SH3_LOWER_REGBASE)/4)
#define SCSCR2_SCFTDR2 ((0x4000154 - SH3_LOWER_REGBASE)/4)
#define SCSSR2_SCFRDR2 ((0x4000158 - SH3_LOWER_REGBASE)/4)
#define SCFCR2_SCFDR2 ((0x400015c - SH3_LOWER_REGBASE)/4)
/* SH3 upper area */
#define SH3_UPPER_REGBASE (0xffffd000)
#define SH3_UPPER_REGEND (0xffffffff)
#define SH3_ICR0_IPRA_ADDR ((0xfffffee0 - SH3_UPPER_REGBASE)/4)
#define SH3_IPRB_ADDR ((0xfffffee4 - SH3_UPPER_REGBASE)/4)
#define SH3_SCSSR_ADDR ((0xfffffe88 - SH3_UPPER_REGBASE)/4)
#define SH3_TOCR_TSTR_ADDR ((0xfffffe90 - SH3_UPPER_REGBASE)/4)
#define SH3_TCOR0_ADDR ((0xfffffe94 - SH3_UPPER_REGBASE)/4)
#define SH3_TCNT0_ADDR ((0xfffffe98 - SH3_UPPER_REGBASE)/4)
#define SH3_TCR0_ADDR ((0xfffffe9c - SH3_UPPER_REGBASE)/4)
#define SH3_TCOR1_ADDR ((0xfffffea0 - SH3_UPPER_REGBASE)/4)
#define SH3_TCNT1_ADDR ((0xfffffea4 - SH3_UPPER_REGBASE)/4)
#define SH3_TCR1_ADDR ((0xfffffea8 - SH3_UPPER_REGBASE)/4)
#define SH3_TCOR2_ADDR ((0xfffffeac - SH3_UPPER_REGBASE)/4)
#define SH3_TCNT2_ADDR ((0xfffffeb0 - SH3_UPPER_REGBASE)/4)
#define SH3_TCR2_ADDR ((0xfffffeb4 - SH3_UPPER_REGBASE)/4)
#define SH3_TCPR2_ADDR ((0xfffffeb8 - SH3_UPPER_REGBASE)/4)
#define SH3_TRA_ADDR ((0xffffffd0 - SH3_UPPER_REGBASE)/4)
#define SH3_EXPEVT_ADDR ((0xffffffd4 - SH3_UPPER_REGBASE)/4)
#define SH3_INTEVT_ADDR ((0xffffffd8 - SH3_UPPER_REGBASE)/4)
#endif // MAME_CPU_SH_SH3COMN_H

2001
src/devices/cpu/sh/sh4.cpp
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File diff suppressed because it is too large Load Diff

1543
src/devices/cpu/sh/sh4.h
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File diff suppressed because it is too large Load Diff

2653
src/devices/cpu/sh/sh4comn.cpp
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File diff suppressed because it is too large Load Diff

360
src/devices/cpu/sh/sh4dmac.cpp
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@ -21,27 +21,27 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_dmac_callback )
switch (channel)
{
case 0:
m_SH4_DMATCR0 = 0;
m_SH4_CHCR0 |= CHCR_TE;
if (m_SH4_CHCR0 & CHCR_IE)
m_dmatcr0 = 0;
m_chcr0 |= CHCR_TE;
if (m_chcr0 & CHCR_IE)
sh4_exception_request(SH4_INTC_DMTE0);
break;
case 1:
m_SH4_DMATCR1 = 0;
m_SH4_CHCR1 |= CHCR_TE;
if (m_SH4_CHCR1 & CHCR_IE)
m_dmatcr1 = 0;
m_chcr1 |= CHCR_TE;
if (m_chcr1 & CHCR_IE)
sh4_exception_request(SH4_INTC_DMTE1);
break;
case 2:
m_SH4_DMATCR2 = 0;
m_SH4_CHCR2 |= CHCR_TE;
if (m_SH4_CHCR2 & CHCR_IE)
m_dmatcr2 = 0;
m_chcr2 |= CHCR_TE;
if (m_chcr2 & CHCR_IE)
sh4_exception_request(SH4_INTC_DMTE2);
break;
case 3:
m_SH4_DMATCR3 = 0;
m_SH4_CHCR3 |= CHCR_TE;
if (m_SH4_CHCR3 & CHCR_IE)
m_dmatcr3 = 0;
m_chcr3 |= CHCR_TE;
if (m_chcr3 & CHCR_IE)
sh4_exception_request(SH4_INTC_DMTE3);
break;
}
@ -99,7 +99,7 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src --;
if (incd == 2)
dst --;
m_program->write_byte(dst, m_program->read_byte(src));
m_program->write_byte(dst & SH34_AM, m_program->read_byte(src & SH34_AM));
if (incs == 1)
src ++;
if (incd == 1)
@ -115,7 +115,7 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src -= 2;
if (incd == 2)
dst -= 2;
m_program->write_word(dst, m_program->read_word(src));
m_program->write_word(dst & SH34_AM, m_program->read_word(src & SH34_AM));
if (incs == 1)
src += 2;
if (incd == 1)
@ -131,7 +131,7 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src -= 8;
if (incd == 2)
dst -= 8;
m_program->write_qword(dst, m_program->read_qword(src));
m_program->write_qword(dst & SH34_AM, m_program->read_qword(src & SH34_AM));
if (incs == 1)
src += 8;
if (incd == 1)
@ -148,7 +148,7 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src -= 4;
if (incd == 2)
dst -= 4;
m_program->write_dword(dst, m_program->read_dword(src));
m_program->write_dword(dst & SH34_AM, m_program->read_dword(src & SH34_AM));
if (incs == 1)
src += 4;
if (incd == 1)
@ -165,10 +165,10 @@ int sh34_base_device::sh4_dma_transfer(int channel, int timermode, uint32_t chcr
src -= 32;
if (incd == 2)
dst -= 32;
m_program->write_qword(dst, m_program->read_qword(src));
m_program->write_qword(dst + 8, m_program->read_qword(src + 8));
m_program->write_qword(dst + 16, m_program->read_qword(src + 16));
m_program->write_qword(dst + 24, m_program->read_qword(src + 24));
m_program->write_qword(dst & SH34_AM, m_program->read_qword(src & SH34_AM));
m_program->write_qword((dst + 8) & SH34_AM, m_program->read_qword((src + 8) & SH34_AM));
m_program->write_qword((dst + 16) & SH34_AM, m_program->read_qword((src + 16) & SH34_AM));
m_program->write_qword((dst + 24) & SH34_AM, m_program->read_qword((src + 24) & SH34_AM));
if (incs == 1)
src += 32;
if (incd == 1)
@ -238,41 +238,41 @@ void sh34_base_device::sh4_dmac_check(int channel)
switch (channel)
{
case 0:
sar = m_SH4_SAR0;
dar = m_SH4_DAR0;
chcr = m_SH4_CHCR0;
dmatcr = m_SH4_DMATCR0;
sar = m_sar0;
dar = m_dar0;
chcr = m_chcr0;
dmatcr = m_dmatcr0;
break;
case 1:
sar = m_SH4_SAR1;
dar = m_SH4_DAR1;
chcr = m_SH4_CHCR1;
dmatcr = m_SH4_DMATCR1;
sar = m_sar1;
dar = m_dar1;
chcr = m_chcr1;
dmatcr = m_dmatcr1;
break;
case 2:
sar = m_SH4_SAR2;
dar = m_SH4_DAR2;
chcr = m_SH4_CHCR2;
dmatcr = m_SH4_DMATCR2;
sar = m_sar2;
dar = m_dar2;
chcr = m_chcr2;
dmatcr = m_dmatcr2;
break;
case 3:
sar = m_SH4_SAR3;
dar = m_SH4_DAR3;
chcr = m_SH4_CHCR3;
dmatcr = m_SH4_DMATCR3;
sar = m_sar3;
dar = m_dar3;
chcr = m_chcr3;
dmatcr = m_dmatcr3;
break;
default:
return;
}
if (chcr & m_SH4_DMAOR & DMAOR_DME)
if (chcr & m_dmaor & DMAOR_DME)
{
if ((((chcr & CHCR_RS) >> 8) < 2) || (((chcr & CHCR_RS) >> 8) > 6))
return;
if (!m_dma_timer_active[channel] && !(chcr & CHCR_TE) && !(m_SH4_DMAOR & (DMAOR_AE | DMAOR_NMIF)))
if (!m_dma_timer_active[channel] && !(chcr & CHCR_TE) && !(m_dmaor & (DMAOR_AE | DMAOR_NMIF)))
{
if (((chcr & CHCR_RS) >> 8) > 3)
sh4_dma_transfer(channel, 1, chcr, &sar, &dar, &dmatcr);
else if ((m_SH4_DMAOR & DMAOR_DDT) == 0)
else if ((m_dmaor & DMAOR_DDT) == 0)
sh4_dma_transfer_device(channel, chcr, &sar, &dar, &dmatcr); // tell device we are ready to transfer
}
}
@ -311,38 +311,38 @@ int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s)
case 8:
if (m_dma_source_increment[channel] == 2)
m_dma_source[channel] -= 8;
*(uint64_t *)data = m_program->read_qword(m_dma_source[channel] & ~7);
*(uint64_t *)data = m_program->read_qword(m_dma_source[channel] & SH34_AM & ~7);
if (m_dma_source_increment[channel] == 1)
m_dma_source[channel] += 8;
break;
case 1:
if (m_dma_source_increment[channel] == 2)
m_dma_source[channel]--;
*(uint8_t *)data = m_program->read_byte(m_dma_source[channel]);
*(uint8_t *)data = m_program->read_byte(m_dma_source[channel] & SH34_AM);
if (m_dma_source_increment[channel] == 1)
m_dma_source[channel]++;
break;
case 2:
if (m_dma_source_increment[channel] == 2)
m_dma_source[channel] -= 2;
*(uint16_t *)data = m_program->read_word(m_dma_source[channel] & ~1);
*(uint16_t *)data = m_program->read_word(m_dma_source[channel] & SH34_AM & ~1);
if (m_dma_source_increment[channel] == 1)
m_dma_source[channel] += 2;
break;
case 4:
if (m_dma_source_increment[channel] == 2)
m_dma_source[channel] -= 4;
*(uint32_t *)data = m_program->read_dword(m_dma_source[channel] & ~3);
*(uint32_t *)data = m_program->read_dword(m_dma_source[channel] & SH34_AM & ~3);
if (m_dma_source_increment[channel] == 1)
m_dma_source[channel] += 4;
break;
case 32:
if (m_dma_source_increment[channel] == 2)
m_dma_source[channel] -= 32;
*(uint64_t *)data = m_program->read_qword(m_dma_source[channel] & ~31);
*((uint64_t *)data+1) = m_program->read_qword((m_dma_source[channel] & ~31)+8);
*((uint64_t *)data+2) = m_program->read_qword((m_dma_source[channel] & ~31)+16);
*((uint64_t *)data+3) = m_program->read_qword((m_dma_source[channel] & ~31)+24);
*(uint64_t *)data = m_program->read_qword(m_dma_source[channel] & SH34_AM & ~31);
*((uint64_t *)data+1) = m_program->read_qword((m_dma_source[channel] & SH34_AM & ~31)+8);
*((uint64_t *)data+2) = m_program->read_qword((m_dma_source[channel] & SH34_AM & ~31)+16);
*((uint64_t *)data+3) = m_program->read_qword((m_dma_source[channel] & SH34_AM & ~31)+24);
if (m_dma_source_increment[channel] == 1)
m_dma_source[channel] += 32;
break;
@ -370,38 +370,38 @@ int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s)
case 8:
if (m_dma_destination_increment[channel] == 2)
m_dma_destination[channel]-=8;
m_program->write_qword(m_dma_destination[channel] & ~7, *(uint64_t *)data);
m_program->write_qword(m_dma_destination[channel] & SH34_AM & ~7, *(uint64_t *)data);
if (m_dma_destination_increment[channel] == 1)
m_dma_destination[channel]+=8;
break;
case 1:
if (m_dma_destination_increment[channel] == 2)
m_dma_destination[channel]--;
m_program->write_byte(m_dma_destination[channel], *(uint8_t *)data);
m_program->write_byte(m_dma_destination[channel] & SH34_AM, *(uint8_t *)data);
if (m_dma_destination_increment[channel] == 1)
m_dma_destination[channel]++;
break;
case 2:
if (m_dma_destination_increment[channel] == 2)
m_dma_destination[channel]-=2;
m_program->write_word(m_dma_destination[channel] & ~1, *(uint16_t *)data);
m_program->write_word(m_dma_destination[channel] & SH34_AM & ~1, *(uint16_t *)data);
if (m_dma_destination_increment[channel] == 1)
m_dma_destination[channel]+=2;
break;
case 4:
if (m_dma_destination_increment[channel] == 2)
m_dma_destination[channel]-=4;
m_program->write_dword(m_dma_destination[channel] & ~3, *(uint32_t *)data);
m_program->write_dword(m_dma_destination[channel] & SH34_AM & ~3, *(uint32_t *)data);
if (m_dma_destination_increment[channel] == 1)
m_dma_destination[channel]+=4;
break;
case 32:
if (m_dma_destination_increment[channel] == 2)
m_dma_destination[channel]-=32;
m_program->write_qword(m_dma_destination[channel] & ~31, *(uint64_t *)data);
m_program->write_qword((m_dma_destination[channel] & ~31)+8, *((uint64_t *)data+1));
m_program->write_qword((m_dma_destination[channel] & ~31)+16, *((uint64_t *)data+2));
m_program->write_qword((m_dma_destination[channel] & ~31)+24, *((uint64_t *)data+3));
m_program->write_qword(m_dma_destination[channel] & SH34_AM & ~31, *(uint64_t *)data);
m_program->write_qword((m_dma_destination[channel] & SH34_AM & ~31)+8, *((uint64_t *)data+1));
m_program->write_qword((m_dma_destination[channel] & SH34_AM & ~31)+16, *((uint64_t *)data+2));
m_program->write_qword((m_dma_destination[channel] & SH34_AM & ~31)+24, *((uint64_t *)data+3));
if (m_dma_destination_increment[channel] == 1)
m_dma_destination[channel]+=32;
break;
@ -434,44 +434,44 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
{
case 0:
if (s->mode & 1)
s->source = m_SH4_SAR0;
s->source = m_sar0;
if (s->mode & 2)
m_SH4_SAR0 = s->source;
m_sar0 = s->source;
if (s->mode & 4)
s->destination = m_SH4_DAR0;
s->destination = m_dar0;
if (s->mode & 8)
m_SH4_DAR0 = s->destination;
m_dar0 = s->destination;
break;
case 1:
if (s->mode & 1)
s->source = m_SH4_SAR1;
s->source = m_sar1;
if (s->mode & 2)
m_SH4_SAR1 = s->source;
m_sar1 = s->source;
if (s->mode & 4)
s->destination = m_SH4_DAR1;
s->destination = m_dar1;
if (s->mode & 8)
m_SH4_DAR1 = s->destination;
m_dar1 = s->destination;
break;
case 2:
if (s->mode & 1)
s->source = m_SH4_SAR2;
s->source = m_sar2;
if (s->mode & 2)
m_SH4_SAR2 = s->source;
m_sar2 = s->source;
if (s->mode & 4)
s->destination = m_SH4_DAR2;
s->destination = m_dar2;
if (s->mode & 8)
m_SH4_DAR2 = s->destination;
m_dar2 = s->destination;
break;
case 3:
default:
if (s->mode & 1)
s->source = m_SH4_SAR3;
s->source = m_sar3;
if (s->mode & 2)
m_SH4_SAR3 = s->source;
m_sar3 = s->source;
if (s->mode & 4)
s->destination = m_SH4_DAR3;
s->destination = m_dar3;
if (s->mode & 8)
m_SH4_DAR3 = s->destination;
m_dar3 = s->destination;
break;
}
uint32_t len;
@ -479,21 +479,21 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
switch (s->channel)
{
case 0:
chcr = m_SH4_CHCR0;
len = m_SH4_DMATCR0;
chcr = m_chcr0;
len = m_dmatcr0;
break;
case 1:
chcr = m_SH4_CHCR1;
len = m_SH4_DMATCR1;
chcr = m_chcr1;
len = m_dmatcr1;
break;
case 2:
chcr = m_SH4_CHCR2;
len = m_SH4_DMATCR2;
chcr = m_chcr2;
len = m_dmatcr2;
break;
case 3:
default:
chcr = m_SH4_CHCR3;
len = m_SH4_DMATCR3;
chcr = m_chcr3;
len = m_dmatcr3;
break;
}
@ -528,7 +528,7 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
uint32_t *p32bits = (uint32_t *)s->buffer;
for (uint32_t pos = 0; pos < s->length; pos++)
{
*p32bits++ = m_program->read_dword(s->source);
*p32bits++ = m_program->read_dword(s->source & SH34_AM);
s->source = s->source + 4;
}
}
@ -537,7 +537,7 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
uint32_t *p32bits = (uint32_t *)s->buffer;
for (uint32_t pos = 0; pos < s->length; pos++)
{
m_program->write_dword(s->destination, *p32bits);
m_program->write_dword(s->destination & SH34_AM, *p32bits);
p32bits++;
s->destination = s->destination + 4;
}
@ -550,7 +550,7 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
uint64_t *p32bytes = (uint64_t *)s->buffer;
for (uint32_t pos = 0; pos < s->length * 4; pos++)
{
*p32bytes++ = m_program->read_qword(s->source);
*p32bytes++ = m_program->read_qword(s->source & SH34_AM);
s->destination = s->destination + 8;
}
}
@ -559,7 +559,7 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
uint64_t *p32bytes = (uint64_t *)s->buffer;
for (uint32_t pos = 0; pos < s->length * 4; pos++)
{
m_program->write_qword(s->destination, *p32bytes);
m_program->write_qword(s->destination & SH34_AM, *p32bytes);
p32bytes++;
s->destination = s->destination + 8;
}
@ -568,100 +568,184 @@ void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s)
}
}
void sh34_base_device::sh4_handle_sar0_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::sar0_r(offs_t offset, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_SAR0);
return m_sar0;
}
void sh34_base_device::sh4_handle_sar1_addr_w(uint32_t data, uint32_t mem_mask)
void sh34_base_device::sar0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_SAR1);
COMBINE_DATA(&m_sar0);
}
void sh34_base_device::sh4_handle_sar2_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::dar0_r(offs_t offset, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_SAR2);
return m_dar0;
}
void sh34_base_device::sh4_handle_sar3_addr_w(uint32_t data, uint32_t mem_mask)
void sh34_base_device::dar0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_SAR3);
COMBINE_DATA(&m_dar0);
}
void sh34_base_device::sh4_handle_dar0_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::dmatcr0_r(offs_t offset, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_DAR0);
return m_dmatcr0;
}
void sh34_base_device::sh4_handle_dar1_addr_w(uint32_t data, uint32_t mem_mask)
void sh34_base_device::dmatcr0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_DAR1);
COMBINE_DATA(&m_dmatcr0);
}
void sh34_base_device::sh4_handle_dar2_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::chcr0_r(offs_t offset, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_DAR2);
return m_chcr0;
}
void sh34_base_device::sh4_handle_dar3_addr_w(uint32_t data, uint32_t mem_mask)
void sh34_base_device::chcr0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_DAR3);
}
void sh34_base_device::sh4_handle_dmatcr0_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_DMATCR0);
}
void sh34_base_device::sh4_handle_dmatcr1_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_DMATCR1);
}
void sh34_base_device::sh4_handle_dmatcr2_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_DMATCR2);
}
void sh34_base_device::sh4_handle_dmatcr3_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_DMATCR3);
}
void sh34_base_device::sh4_handle_chcr0_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_CHCR0);
COMBINE_DATA(&m_chcr0);
sh4_dmac_check(0);
}
void sh34_base_device::sh4_handle_chcr1_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::sar1_r(offs_t offset, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_CHCR1);
return m_sar1;
}
void sh34_base_device::sar1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_sar1);
}
uint32_t sh34_base_device::dar1_r(offs_t offset, uint32_t mem_mask)
{
return m_dar1;
}
void sh34_base_device::dar1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dar1);
}
uint32_t sh34_base_device::dmatcr1_r(offs_t offset, uint32_t mem_mask)
{
return m_dmatcr1;
}
void sh34_base_device::dmatcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dmatcr1);
}
uint32_t sh34_base_device::chcr1_r(offs_t offset, uint32_t mem_mask)
{
return m_chcr1;
}
void sh34_base_device::chcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_chcr1);
sh4_dmac_check(1);
}
void sh34_base_device::sh4_handle_chcr2_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::sar2_r(offs_t offset, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_CHCR2);
return m_sar2;
}
void sh34_base_device::sar2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_sar2);
}
uint32_t sh34_base_device::dar2_r(offs_t offset, uint32_t mem_mask)
{
return m_dar2;
}
void sh34_base_device::dar2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dar2);
}
uint32_t sh34_base_device::dmatcr2_r(offs_t offset, uint32_t mem_mask)
{
return m_dmatcr2;
}
void sh34_base_device::dmatcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dmatcr2);
}
uint32_t sh34_base_device::chcr2_r(offs_t offset, uint32_t mem_mask)
{
return m_chcr2;
}
void sh34_base_device::chcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_chcr2);
sh4_dmac_check(2);
}
void sh34_base_device::sh4_handle_chcr3_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::sar3_r(offs_t offset, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_CHCR3);
return m_sar3;
}
void sh34_base_device::sar3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_sar3);
}
uint32_t sh34_base_device::dar3_r(offs_t offset, uint32_t mem_mask)
{
return m_dar3;
}
void sh34_base_device::dar3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dar3);
}
uint32_t sh34_base_device::dmatcr3_r(offs_t offset, uint32_t mem_mask)
{
return m_dmatcr3;
}
void sh34_base_device::dmatcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_dmatcr3);
}
uint32_t sh34_base_device::chcr3_r(offs_t offset, uint32_t mem_mask)
{
return m_chcr3;
}
void sh34_base_device::chcr3_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_chcr3);
sh4_dmac_check(3);
}
void sh34_base_device::sh4_handle_dmaor_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::dmaor_r(offs_t offset, uint32_t mem_mask)
{
uint32_t old = m_SH4_DMAOR;
COMBINE_DATA(&m_SH4_DMAOR);
return m_dmaor;
}
if ((m_SH4_DMAOR & DMAOR_AE) && (~old & DMAOR_AE))
m_SH4_DMAOR &= ~DMAOR_AE;
if ((m_SH4_DMAOR & DMAOR_NMIF) && (~old & DMAOR_NMIF))
m_SH4_DMAOR &= ~DMAOR_NMIF;
void sh34_base_device::dmaor_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
uint32_t old = m_dmaor;
COMBINE_DATA(&m_dmaor);
if ((m_dmaor & DMAOR_AE) && (~old & DMAOR_AE))
m_dmaor &= ~DMAOR_AE;
if ((m_dmaor & DMAOR_NMIF) && (~old & DMAOR_NMIF))
m_dmaor &= ~DMAOR_NMIF;
sh4_dmac_check(0);
sh4_dmac_check(1);
sh4_dmac_check(2);

35
src/devices/cpu/sh/sh4dmac.h
View File

@ -26,38 +26,3 @@
#define DMAOR_AE 0x0004
#define DMAOR_NMIF 0x0002
#define DMAOR_DME 0x0001
void sh4_handle_sar0_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_sar1_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_sar2_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_sar3_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_dar0_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_dar1_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_dar2_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_dar3_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_dmatcr0_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_dmatcr1_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_dmatcr2_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_dmatcr3_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_chcr0_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_chcr1_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_chcr2_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_chcr3_addr_w(uint32_t data, uint32_t mem_mask);
void sh4_handle_dmaor_addr_w(uint32_t data, uint32_t mem_mask);
uint32_t sh4_handle_sar0_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_sar1_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_sar2_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_sar3_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_dar0_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_dar1_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_dar2_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_dar3_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_dmatcr0_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_dmatcr1_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_dmatcr2_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_dmatcr3_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_chcr0_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_chcr1_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_chcr2_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_chcr3_addr_r(uint32_t mem_mask);
uint32_t sh4_handle_dmaor_addr_r(uint32_t mem_mask);

8
src/devices/cpu/sh/sh4fe.cpp
View File

@ -31,14 +31,6 @@ uint16_t sh4_frontend::read_word(opcode_desc &desc)
return m_sh->m_pr16(desc.physpc & SH34_AM);
}
uint16_t sh4be_frontend::read_word(opcode_desc &desc)
{
if (desc.physpc >= 0xe0000000)
return m_sh->m_pr16(desc.physpc);
return m_sh->m_pr16(desc.physpc & SH34_AM);
}
bool sh4_frontend::describe_group_0(opcode_desc &desc, const opcode_desc *prev, uint16_t opcode)
{

157
src/devices/cpu/sh/sh4regs.h
View File

@ -5,163 +5,6 @@
#pragma once
/* 00000001111111100000000011111100 */
#define PTEH 0x2000 /* FF000000 */
#define PTEL 0x2001 /* FF000004 */
#define TTB 0x2002 /* FF000008 */
#define TEA 0x2003 /* FF00000C */
#define MMUCR 0x2004 /* FF000010 */
#define BASRA 0x2005 /* FF000014 */
#define BASRB 0x2006 /* FF000018 */
#define CCR 0x2007 /* FF00001C */
#define TRA 0x2008 /* FF000020 */
#define EXPEVT 0x2009 /* FF000024 */
#define INTEVT 0x200A /* FF000028 */
#define VERSION 0x200C /* FF000030 */
#define PTEA 0x200D /* FF000034 */
#define QACR0 0x200E /* FF000038 */
#define QACR1 0x200F /* FF00003C */
#define PRR 0x2011 /* FF000044 */
#define BARA 0x2400 /* FF200000 */
#define BAMRA 0x2401 /* FF200004 */
#define BBRA 0x2402 /* FF200008 */
#define BARB 0x2403 /* FF20000C */
#define BAMRB 0x2404 /* FF200010 */
#define BBRB 0x2405 /* FF200014 */
#define BDRB 0x2406 /* FF200018 */
#define BDMRB 0x2407 /* FF20001C */
#define BRCR 0x2408 /* FF200020 */
#define BCR1 0x3000 /* FF800000 */
#define BCR2 0x3001 /* FF800004 */
#define BCR3 0x3014 /* FF800050 */
#define BCR4 0x17C /* FE0A00F0 */
#define WCR1 0x3002 /* FF800008 */
#define WCR2 0x3003 /* FF80000C */
#define WCR3 0x3004 /* FF800010 */
#define MCR 0x3005 /* FF800014 */
#define PCR 0x3006 /* FF800018 */
#define RTCSR 0x3007 /* FF80001C */
#define RTCNT 0x3008 /* FF800020 */
#define RTCOR 0x3009 /* FF800024 */
#define RFCR 0x300A /* FF800028 */
#define PCTRA 0x300B /* FF80002C */
#define PDTRA 0x300C /* FF800030 */
#define PCTRB 0x3010 /* FF800040 */
#define PDTRB 0x3011 /* FF800044 */
#define GPIOIC 0x3012 /* FF800048 */
#define SDMR2 0x3200 /* FF900000 */
#define SDMR3 0x3280 /* FF940000 */
#define SH4_SAR0_ADDR 0x3400 /* FFA00000 */
#define SH4_DAR0_ADDR 0x3401 /* FFA00004 */
#define SH4_DMATCR0_ADDR 0x3402 /* FFA00008 */
#define SH4_CHCR0_ADDR 0x3403 /* FFA0000C */
#define SH4_SAR1_ADDR 0x3404 /* FFA00010 */
#define SH4_DAR1_ADDR 0x3405 /* FFA00014 */
#define SH4_DMATCR1_ADDR 0x3406 /* FFA00018 */
#define SH4_CHCR1_ADDR 0x3407 /* FFA0001C */
#define SH4_SAR2_ADDR 0x3408 /* FFA00020 */
#define SH4_DAR2_ADDR 0x3409 /* FFA00024 */
#define SH4_DMATCR2_ADDR 0x340A /* FFA00028 */
#define SH4_CHCR2_ADDR 0x340B /* FFA0002C */
#define SH4_SAR3_ADDR 0x340C /* FFA00030 */
#define SH4_DAR3_ADDR 0x340D /* FFA00034 */
#define SH4_DMATCR3_ADDR 0x340E /* FFA00038 */
#define SH4_CHCR3_ADDR 0x340F /* FFA0003C */
#define SH4_DMAOR_ADDR 0x3410 /* FFA00040 */
#define SAR4 0x3414 /* FFA00050 */
#define DAR4 0x3415 /* FFA00054 */
#define DMATCR4 0x3416 /* FFA00058 */
#define CHCR4 0x3417 /* FFA0005C */
#define SAR5 0x3418 /* FFA00060 */
#define DAR5 0x3419 /* FFA00064 */
#define DMATCR5 0x341A /* FFA00068 */
#define CHCR5 0x341B /* FFA0006C */
#define SAR6 0x341C /* FFA00070 */
#define DAR6 0x341D /* FFA00074 */
#define DMATCR6 0x341E /* FFA00078 */
#define CHCR6 0x341F /* FFA0007C */
#define SAR7 0x3420 /* FFA00080 */
#define DAR7 0x3421 /* FFA00084 */
#define DMATCR7 0x3422 /* FFA00088 */
#define CHCR7 0x3423 /* FFA0008C */
#define FRQCR 0x3800 /* FFC00000 */
#define STBCR 0x3801 /* FFC00004 */
#define WTCNT 0x3802 /* FFC00008 */
#define WTCSR 0x3803 /* FFC0000C */
#define STBCR2 0x3804 /* FFC00010 */
#define R64CNT 0x3900 /* FFC80000 */
#define RSECCNT 0x3901 /* FFC80004 */
#define RMINCNT 0x3902 /* FFC80008 */
#define RHRCNT 0x3903 /* FFC8000C */
#define RWKCNT 0x3904 /* FFC80010 */
#define RDAYCNT 0x3905 /* FFC80014 */
#define RMONCNT 0x3906 /* FFC80018 */
#define RYRCNT 0x3907 /* FFC8001C */
#define RSECAR 0x3908 /* FFC80020 */
#define RMINAR 0x3909 /* FFC80024 */
#define RHRAR 0x390A /* FFC80028 */
#define RWKAR 0x390B /* FFC8002C */
#define RDAYAR 0x390C /* FFC80030 */
#define RMONAR 0x390D /* FFC80034 */
#define RCR1 0x390E /* FFC80038 */
#define RCR2 0x390F /* FFC8003C */
#define RCR3 0x3914 /* FFC80050 */
#define RYRAR 0x3915 /* FFC80054 */
#define ICR 0x3A00 /* FFD00000 */
#define IPRA 0x3A01 /* FFD00004 */
#define IPRB 0x3A02 /* FFD00008 */
#define IPRC 0x3A03 /* FFD0000C */
#define IPRD 0x3A04 /* FFD00010 */
#define INTPRI00 0x100 /* FE080000 */
#define INTREQ00 0x108 /* FE080020 */
#define INTMSK00 0x110 /* FE080040 */
#define INTMSKCLR00 0x118 /* FE080060 */
#define CLKSTP00 0x140 /* FE0A0000 */
#define CLKSTPCLR00 0x142 /* FE0A0008 */
#define TSTR2 0x201 /* FE100004 */
#define TCOR3 0x202 /* FE100008 */
#define TCNT3 0x203 /* FE10000C */
#define TCR3 0x204 /* FE100010 */
#define TCOR4 0x205 /* FE100014 */
#define TCNT4 0x206 /* FE100018 */
#define TCR4 0x207 /* FE10001C */
#define SH4_TOCR_ADDR 0x3B00 /* FFD80000 */
#define SH4_TSTR_ADDR 0x3B01 /* FFD80004 */
#define SH4_TCOR0_ADDR 0x3B02 /* FFD80008 */
#define SH4_TCNT0_ADDR 0x3B03 /* FFD8000C */
#define SH4_TCR0_ADDR 0x3B04 /* FFD80010 */
#define SH4_TCOR1_ADDR 0x3B05 /* FFD80014 */
#define SH4_TCNT1_ADDR 0x3B06 /* FFD80018 */
#define SH4_TCR1_ADDR 0x3B07 /* FFD8001C */
#define SH4_TCOR2_ADDR 0x3B08 /* FFD80020 */
#define SH4_TCNT2_ADDR 0x3B09 /* FFD80024 */
#define SH4_TCR2_ADDR 0x3B0A /* FFD80028 */
#define SH4_TCPR2_ADDR 0x3B0B /* FFD8002C */
#define SCSMR1 0x3C00 /* FFE00000 */
#define SCBRR1 0x3C01 /* FFE00004 */
#define SCSCR1 0x3C02 /* FFE00008 */
#define SCTDR1 0x3C03 /* FFE0000C */
#define SCSSR1 0x3C04 /* FFE00010 */
#define SCRDR1 0x3C05 /* FFE00014 */
#define SCSCMR1 0x3C06 /* FFE00018 */
#define SCSPTR1 0x3C07 /* FFE0001C */
#define SCSMR2 0x3D00 /* FFE80000 */
#define SCBRR2 0x3D01 /* FFE80004 */
#define SCSCR2 0x3D02 /* FFE80008 */
#define SCFTDR2 0x3D03 /* FFE8000C */
#define SCFSR2 0x3D04 /* FFE80010 */
#define SCFRDR2 0x3D05 /* FFE80014 */
#define SCFCR2 0x3D06 /* FFE80018 */
#define SCFDR2 0x3D07 /* FFE8001C */
#define SCSPTR2 0x3D08 /* FFE80020 */
#define SCLSR2 0x3D09 /* FFE80024 */
#define SDIR 0x3E00 /* FFF00000 */
#define SDDR 0x3E02 /* FFF00008 */
#define SDINT 0x3E05 /* FFF00014 */
#define SIZEREGS 15878
#define MMUCR_LRUI 0xfc000000
#define MMUCR_URB 0x00fc0000
#define MMUCR_URC 0x0000fc00

288
src/devices/cpu/sh/sh4tmu.cpp
View File

@ -37,18 +37,18 @@ void sh34_base_device::sh4_timer_recompute(int which)
switch (which)
{
case 0:
tcr = m_SH4_TCR0;
tcnt = m_SH4_TCNT0;
tcr = m_tcr0;
tcnt = m_tcnt0;
break;
case 1:
tcr = m_SH4_TCR1;
tcnt = m_SH4_TCNT1;
tcr = m_tcr1;
tcnt = m_tcnt1;
break;
case 2:
tcr = m_SH4_TCR2;
tcnt = m_SH4_TCNT2;
tcr = m_tcr2;
tcnt = m_tcnt2;
break;
}
@ -64,15 +64,15 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
switch (which)
{
case 0:
m_SH4_TCNT0 = m_SH4_TCOR0;
m_tcnt0 = m_tcor0;
break;
case 1:
m_SH4_TCNT1 = m_SH4_TCOR1;
m_tcnt1 = m_tcor1;
break;
case 2:
m_SH4_TCNT2 = m_SH4_TCOR2;
m_tcnt2 = m_tcor2;
break;
}
@ -82,15 +82,15 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
switch (which)
{
case 0:
m_SH4_TCR0 |= 0x100;
m_tcr0 |= 0x100;
break;
case 1:
m_SH4_TCR1 |= 0x100;
m_tcr1 |= 0x100;
break;
case 2:
m_SH4_TCR2 |= 0x100;
m_tcr2 |= 0x100;
break;
}
@ -98,7 +98,7 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
switch (which)
{
case 0:
if (m_SH4_TCR0 & 0x20)
if (m_tcr0 & 0x20)
{
sh4_exception_request(SH4_INTC_TUNI0);
// logerror("SH4_INTC_TUNI0 requested\n");
@ -106,7 +106,7 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
break;
case 1:
if (m_SH4_TCR1 & 0x20)
if (m_tcr1 & 0x20)
{
sh4_exception_request(SH4_INTC_TUNI1);
// logerror("SH4_INTC_TUNI1 requested\n");
@ -114,7 +114,7 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
break;
case 2:
if (m_SH4_TCR2 & 0x20)
if (m_tcr2 & 0x20)
{
sh4_exception_request(SH4_INTC_TUNI2);
// logerror("SH4_INTC_TUNI2 requested\n");
@ -124,88 +124,32 @@ TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback )
}
}
uint32_t sh34_base_device::sh4_handle_tcnt0_addr_r(uint32_t mem_mask)
void sh34_base_device::tocr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
{
if (m_SH4_TSTR & 1)
return compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]);
else
return m_SH4_TCNT0;
COMBINE_DATA(&m_tocr);
}
uint32_t sh34_base_device::sh4_handle_tcnt1_addr_r(uint32_t mem_mask)
uint8_t sh34_base_device::tocr_r(offs_t offset, uint8_t mem_mask)
{
if (m_SH4_TSTR & 2)
return compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]);
else
return m_SH4_TCNT1;
return m_tocr;
}
uint32_t sh34_base_device::sh4_handle_tcnt2_addr_r(uint32_t mem_mask)
uint8_t sh34_base_device::tstr_r(offs_t offset, uint8_t mem_mask)
{
if (m_SH4_TSTR & 4)
return compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]);
else
return m_SH4_TCNT2;
return m_tstr;
}
uint32_t sh34_base_device::sh4_handle_tcor0_addr_r(uint32_t mem_mask)
void sh34_base_device::tstr_w(offs_t offset, uint8_t data, uint8_t mem_mask)
{
return m_SH4_TCOR0;
}
uint32_t sh34_base_device::sh4_handle_tcor1_addr_r(uint32_t mem_mask)
{
return m_SH4_TCOR1;
}
uint32_t sh34_base_device::sh4_handle_tcor2_addr_r(uint32_t mem_mask)
{
return m_SH4_TCOR2;
}
uint32_t sh34_base_device::sh4_handle_tcr0_addr_r(uint32_t mem_mask)
{
return m_SH4_TCR0;
}
uint32_t sh34_base_device::sh4_handle_tcr1_addr_r(uint32_t mem_mask)
{
return m_SH4_TCR1;
}
uint32_t sh34_base_device::sh4_handle_tcr2_addr_r(uint32_t mem_mask)
{
return m_SH4_TCR2;
}
uint32_t sh34_base_device::sh4_handle_tstr_addr_r(uint32_t mem_mask)
{
return m_SH4_TSTR;
}
uint32_t sh34_base_device::sh4_handle_tocr_addr_r(uint32_t mem_mask)
{
return m_SH4_TOCR;
}
uint32_t sh34_base_device::sh4_handle_tcpr2_addr_r(uint32_t mem_mask)
{
return m_SH4_TCPR2;
}
void sh34_base_device::sh4_handle_tstr_addr_w(uint32_t data, uint32_t mem_mask)
{
uint32_t chg = m_SH4_TSTR;
COMBINE_DATA(&m_SH4_TSTR);
chg ^= m_SH4_TSTR;
uint32_t chg = m_tstr;
COMBINE_DATA(&m_tstr);
chg ^= m_tstr;
if (chg & 1)
{
if ((m_SH4_TSTR & 1) == 0)
if ((m_tstr & 1) == 0)
{
m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]);
m_tcnt0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_tcr0 & 7]);
m_timer[0]->adjust(attotime::never);
}
else
@ -214,9 +158,9 @@ void sh34_base_device::sh4_handle_tstr_addr_w(uint32_t data, uint32_t mem_mask)
if (chg & 2)
{
if ((m_SH4_TSTR & 2) == 0)
if ((m_tstr & 2) == 0)
{
m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]);
m_tcnt1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_tcr1 & 7]);
m_timer[1]->adjust(attotime::never);
}
else
@ -225,9 +169,9 @@ void sh34_base_device::sh4_handle_tstr_addr_w(uint32_t data, uint32_t mem_mask)
if (chg & 4)
{
if ((m_SH4_TSTR & 4) == 0)
if ((m_tstr & 4) == 0)
{
m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]);
m_tcnt2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_tcr2 & 7]);
m_timer[2]->adjust(attotime::never);
}
else
@ -235,87 +179,141 @@ void sh34_base_device::sh4_handle_tstr_addr_w(uint32_t data, uint32_t mem_mask)
}
}
void sh34_base_device::sh4_handle_tcr0_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::tcor0_r(offs_t offset, uint32_t mem_mask)
{
uint32_t old2 = m_SH4_TCR0;
COMBINE_DATA(&m_SH4_TCR0);
if (m_SH4_TSTR & 1)
return m_tcor0;
}
void sh34_base_device::tcor0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_tcor0);
}
uint32_t sh34_base_device::tcnt0_r(offs_t offset, uint32_t mem_mask)
{
if (m_tstr & 1)
return compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_tcr0 & 7]);
else
return m_tcnt0;
}
void sh34_base_device::tcnt0_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_tcnt0);
if (m_tstr & 1)
sh4_timer_recompute(0);
}
uint16_t sh34_base_device::tcr0_r(offs_t offset, uint16_t mem_mask)
{
return m_tcr0;
}
void sh34_base_device::tcr0_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
uint32_t old2 = m_tcr0;
COMBINE_DATA(&m_tcr0);
if (m_tstr & 1)
{
m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[old2 & 7]);
m_tcnt0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[old2 & 7]);
sh4_timer_recompute(0);
}
if (!(m_SH4_TCR0 & 0x20) || !(m_SH4_TCR0 & 0x100))
if (!(m_tcr0 & 0x20) || !(m_tcr0 & 0x100))
sh4_exception_unrequest(SH4_INTC_TUNI0);
}
void sh34_base_device::sh4_handle_tcr1_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::tcor1_r(offs_t offset, uint32_t mem_mask)
{
uint32_t old2 = m_SH4_TCR1;
COMBINE_DATA(&m_SH4_TCR1);
if (m_SH4_TSTR & 2)
return m_tcor1;
}
void sh34_base_device::tcor1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_tcor1);
}
uint32_t sh34_base_device::tcnt1_r(offs_t offset, uint32_t mem_mask)
{
if (m_tstr & 2)
return compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_tcr1 & 7]);
else
return m_tcnt1;
}
void sh34_base_device::tcnt1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_tcnt1);
if (m_tstr & 2)
sh4_timer_recompute(1);
}
uint16_t sh34_base_device::tcr1_r(offs_t offset, uint16_t mem_mask)
{
return m_tcr1;
}
void sh34_base_device::tcr1_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
uint32_t old2 = m_tcr1;
COMBINE_DATA(&m_tcr1);
if (m_tstr & 2)
{
m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[old2 & 7]);
m_tcnt1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[old2 & 7]);
sh4_timer_recompute(1);
}
if (!(m_SH4_TCR1 & 0x20) || !(m_SH4_TCR1 & 0x100))
if (!(m_tcr1 & 0x20) || !(m_tcr1 & 0x100))
sh4_exception_unrequest(SH4_INTC_TUNI1);
}
void sh34_base_device::sh4_handle_tcr2_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::tcor2_r(offs_t offset, uint32_t mem_mask)
{
uint32_t old2 = m_SH4_TCR2;
COMBINE_DATA(&m_SH4_TCR2);
if (m_SH4_TSTR & 4)
return m_tcor2;
}
void sh34_base_device::tcor2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_tcor2);
}
uint32_t sh34_base_device::tcnt2_r(offs_t offset, uint32_t mem_mask)
{
if (m_tstr & 4)
return compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_tcr2 & 7]);
else
return m_tcnt2;
}
void sh34_base_device::tcnt2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_tcnt2);
if (m_tstr & 4)
sh4_timer_recompute(2);
}
uint16_t sh34_base_device::tcr2_r(offs_t offset, uint16_t mem_mask)
{
return m_tcr2;
}
void sh34_base_device::tcr2_w(offs_t offset, uint16_t data, uint16_t mem_mask)
{
uint32_t old2 = m_tcr2;
COMBINE_DATA(&m_tcr2);
if (m_tstr & 4)
{
m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[old2 & 7]);
m_tcnt2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[old2 & 7]);
sh4_timer_recompute(2);
}
if (!(m_SH4_TCR2 & 0x20) || !(m_SH4_TCR2 & 0x100))
if (!(m_tcr2 & 0x20) || !(m_tcr2 & 0x100))
sh4_exception_unrequest(SH4_INTC_TUNI2);
}
void sh34_base_device::sh4_handle_tcor0_addr_w(uint32_t data, uint32_t mem_mask)
uint32_t sh34_base_device::tcpr2_r(offs_t offset, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_TCOR0);
return m_tcpr2;
}
void sh34_base_device::sh4_handle_tcor1_addr_w(uint32_t data, uint32_t mem_mask)
void sh34_base_device::tcpr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_TCOR1);
}
void sh34_base_device::sh4_handle_tcor2_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_TCOR2);
}
void sh34_base_device::sh4_handle_tcnt0_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_TCNT0);
if (m_SH4_TSTR & 1)
sh4_timer_recompute(0);
}
void sh34_base_device::sh4_handle_tcnt1_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_TCNT1);
if (m_SH4_TSTR & 2)
sh4_timer_recompute(1);
}
void sh34_base_device::sh4_handle_tcnt2_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_TCNT2);
if (m_SH4_TSTR & 4)
sh4_timer_recompute(2);
}
void sh34_base_device::sh4_handle_tocr_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_TOCR);
}
void sh34_base_device::sh4_handle_tcpr2_addr_w(uint32_t data, uint32_t mem_mask)
{
COMBINE_DATA(&m_SH4_TCPR2);
COMBINE_DATA(&m_tcpr2);
}

4
src/mame/aristocrat/aristmk6.cpp
View File

@ -167,7 +167,7 @@ private:
u8 irl3pend0 = 0, irl3en0 = 0;
u8 irl3pend1 = 0, irl3en1 = 0;
required_device<sh4_device> m_maincpu;
required_device<sh7750_device> m_maincpu;
required_device<ns16550_device> m_uart0;
required_device<ns16550_device> m_uart1;
required_device<eeprom_serial_93cxx_device> m_eeprom0;
@ -438,7 +438,7 @@ static constexpr XTAL ARISTMK6_CPU_CLOCK = 200_MHz_XTAL;
void aristmk6_state::aristmk6(machine_config &config)
{
/* basic machine hardware */
SH4LE(config, m_maincpu, ARISTMK6_CPU_CLOCK);
SH7750(config, m_maincpu, ARISTMK6_CPU_CLOCK);
m_maincpu->set_md(0, 1);
m_maincpu->set_md(1, 0);
m_maincpu->set_md(2, 1);

4
src/mame/capcom/alien.cpp
View File

@ -148,7 +148,7 @@ private:
void masmario2_map(address_map &map) ATTR_COLD;
// devices
required_device<sh4_device> m_maincpu;
required_device<sh7750s_device> m_maincpu;
required_shared_ptr<u64> m_workram;
required_device<screen_device> m_screen;
required_device<mb86292_device> m_gpu;
@ -388,7 +388,7 @@ void alien_state::machine_reset()
void alien_state::alien(machine_config &config)
{
/* basic machine hardware */
SH4LE(config, m_maincpu, MASTER_CLOCK); /* 200MHz */
SH7750S(config, m_maincpu, MASTER_CLOCK); /* 200MHz */
m_maincpu->set_addrmap(AS_PROGRAM, &alien_state::alien_map);
m_maincpu->set_periodic_int(FUNC(alien_state::sio_irq_w), attotime::from_hz(60));
// m_maincpu->set_force_no_drc(true);

6
src/mame/cave/cv1k.cpp
View File

@ -234,7 +234,7 @@ protected:
virtual void machine_reset() override ATTR_COLD;
private:
required_device<sh34_base_device> m_maincpu;
required_device<sh7709s_device> m_maincpu;
required_device<ep1c12_device> m_blitter;
required_device<samsung_k9f1g08u0m_device> m_nand;
required_device<rtc9701_device> m_eeprom;
@ -466,7 +466,7 @@ void cv1k_state::machine_reset()
void cv1k_state::cv1k(machine_config &config)
{
/* basic machine hardware */
SH3BE(config, m_maincpu, 12.8_MHz_XTAL*8); // 102.4MHz
SH7709S(config, m_maincpu, 12.8_MHz_XTAL*8, ENDIANNESS_BIG); // 102.4MHz
m_maincpu->set_md(0, 0); // none of this is verified
m_maincpu->set_md(1, 0); // (the sh3 is different to the sh4 anyway, should be changed)
m_maincpu->set_md(2, 0);
@ -506,7 +506,7 @@ void cv1k_state::cv1k_d(machine_config &config)
cv1k(config);
/* basic machine hardware */
SH3BE(config.replace(), m_maincpu, 12.8_MHz_XTAL*8); // 102.4MHz
SH7709S(config.replace(), m_maincpu, 12.8_MHz_XTAL*8, ENDIANNESS_BIG); // 102.4MHz
m_maincpu->set_md(0, 0); // none of this is verified
m_maincpu->set_md(1, 0); // (the sh3 is different to the sh4 anyway, should be changed)
m_maincpu->set_md(2, 0);

8
src/mame/gaelco/atvtrack.cpp
View File

@ -143,8 +143,8 @@ protected:
int m_nandcommand[4]{}, m_nandoffset[4]{}, m_nandaddressstep = 0, m_nandaddress[4]{};
u32 m_area1_data[4]{};
required_device<sh4_device> m_maincpu;
required_device<sh4_device> m_subcpu;
required_device<sh7750s_device> m_maincpu;
required_device<sh7750s_device> m_subcpu;
u16 gpu_irq_pending = 0;
u16 gpu_irq_mask = 0;
@ -576,7 +576,7 @@ INPUT_PORTS_END
void atvtrack_state::atvtrack(machine_config &config)
{
/* basic machine hardware */
SH4LE(config, m_maincpu, ATV_CPU_CLOCK);
SH7750S(config, m_maincpu, ATV_CPU_CLOCK);
m_maincpu->set_md(0, 1);
m_maincpu->set_md(1, 1);
m_maincpu->set_md(2, 0);
@ -591,7 +591,7 @@ void atvtrack_state::atvtrack(machine_config &config)
m_maincpu->set_addrmap(AS_IO, &atvtrack_state::atvtrack_main_port);
m_maincpu->set_force_no_drc(true);
SH4LE(config, m_subcpu, ATV_CPU_CLOCK);
SH7750S(config, m_subcpu, ATV_CPU_CLOCK);
m_subcpu->set_md(0, 1);
m_subcpu->set_md(1, 1);
m_subcpu->set_md(2, 0);

4
src/mame/irem/m119.cpp
View File

@ -53,7 +53,7 @@ private:
void program_map(address_map &map) ATTR_COLD;
required_device<sh3_device> m_maincpu;
required_device<sh7708s_device> m_maincpu;
};
uint32_t m119_state::screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect)
@ -99,7 +99,7 @@ INPUT_PORTS_END
void m119_state::m119(machine_config &config)
{
// basic machine hardware
SH3LE(config, m_maincpu, 60'000'000); // HD6417708S, according to the datasheet operation frequency is 60 MHz.
SH7708S(config, m_maincpu, 60'000'000); // HD6417708S, according to the datasheet operation frequency is 60 MHz.
m_maincpu->set_addrmap(AS_PROGRAM, &m119_state::program_map);
// m_maincpu->set_vblank_int("screen", FUNC(m119_state::irq2_line_hold));

4
src/mame/konami/cougar.cpp
View File

@ -51,7 +51,7 @@ public:
void cougar(machine_config &config);
private:
required_device<cpu_device> m_maincpu;
required_device<sh7751r_device> m_maincpu;
void program_map(address_map &map) ATTR_COLD;
};
@ -67,7 +67,7 @@ INPUT_PORTS_END
void cougar_state::cougar(machine_config &config)
{
SH4LE(config, m_maincpu, 20_MHz_XTAL);
SH7751R(config, m_maincpu, 20_MHz_XTAL);
m_maincpu->set_addrmap(AS_PROGRAM, &cougar_state::program_map);
m_maincpu->set_force_no_drc(true);

5
src/mame/konami/konamigs.cpp
View File

@ -76,7 +76,7 @@ public:
void init_gsan();
protected:
required_device<sh34_base_device> m_maincpu;
required_device<sh7709_device> m_maincpu;
required_device<ymz280b_device> m_ymz;
required_device<ata_interface_device> m_ata;
required_ioport m_rtc_r;
@ -776,7 +776,6 @@ void gsan_state::main_map_common(address_map &map)
map(0x18000000, 0x18000001).rw("ymz", FUNC(ymz280b_device::read), FUNC(ymz280b_device::write));
map(0x1f000000, 0x1f000fff).ram(); // cache RAM-mode (SH3 internal), actually should be 7Fxxxxxx, but current SH3 core doesn't like 7Fxxxxxx
map(0xa0000000, 0xa000ffff).rom().region("maincpu", 0); // uncached mirror, otherwise no disassembly can bee seen in debugger (bug?)
}
void gsan_state::main_map(address_map &map)
{
@ -1039,7 +1038,7 @@ void gsan_state::gsan(machine_config &config)
{
// basic machine hardware
// SH7709 is earlier version of SH7709S (cv1k), not exact same, have minor differences
SH3BE(config, m_maincpu, 32_MHz_XTAL * 2);
SH7709(config, m_maincpu, 32_MHz_XTAL * 2, ENDIANNESS_BIG);
m_maincpu->set_md(0, 0);
m_maincpu->set_md(1, 0);
m_maincpu->set_md(2, 0);

2
src/mame/sega/dc.h
View File

@ -76,7 +76,7 @@ public:
void external_irq(int state);
required_device<sh4_base_device> m_maincpu;
required_device<sh7091_device> m_maincpu;
required_device<cpu_device> m_soundcpu;
required_device<powervr2_device> m_powervr2;
required_device<maple_dc_device> m_maple;

6
src/mame/sega/dccons.cpp
View File

@ -183,10 +183,6 @@ void dc_cons_state::dc_map(address_map &map)
// map(0x14000000, 0x17ffffff) G2 Ext Device #3
map(0x8c000000, 0x8cffffff).ram().share("dc_ram"); // another RAM mirror
map(0xa0000000, 0xa01fffff).rom().region("maincpu", 0);
map(0xf4000000, 0xf4003fff).noprw(); // SH-4 operand cache address array
}
@ -381,7 +377,7 @@ void dc_cons_state::gdrom_config(device_t *device)
void dc_cons_state::dc_base(machine_config &config)
{
/* basic machine hardware */
SH4LE(config, m_maincpu, CPU_CLOCK);
SH7091(config, m_maincpu, CPU_CLOCK);
m_maincpu->set_md(0, 1);
m_maincpu->set_md(1, 0);
m_maincpu->set_md(2, 1);

4
src/mame/sega/hikaru.cpp
View File

@ -512,7 +512,7 @@ void hikaru_state::hikaru_map_slave(address_map &map)
void hikaru_state::hikaru(machine_config &config)
{
/* basic machine hardware */
SH4LE(config, m_maincpu, CPU_CLOCK);
SH4(config, m_maincpu, CPU_CLOCK);
// m_maincpu->set_md(0, 1);
// m_maincpu->set_md(1, 0);
// m_maincpu->set_md(2, 1);
@ -528,7 +528,7 @@ void hikaru_state::hikaru(machine_config &config)
m_maincpu->set_force_no_drc(true);
// m_maincpu->set_vblank_int("screen", FUNC(hikaru_state::vblank));
SH4LE(config, m_slave, CPU_CLOCK);
SH4(config, m_slave, CPU_CLOCK);
m_slave->set_addrmap(AS_PROGRAM, &hikaru_state::hikaru_map_slave);
m_slave->set_force_no_drc(true);

2
src/mame/sega/maple-dc.h
View File

@ -66,7 +66,7 @@ private:
maple_device *devices[4];
required_device<sh4_device> cpu;
required_device<sh7091_device> cpu;
emu_timer *timer;
uint32_t mdstar, mden, mdst, msys;

2
src/mame/sega/naomi.cpp
View File

@ -2413,7 +2413,7 @@ void naomi_state::external_reset(int state)
void dc_state::naomi_aw_base(machine_config &config)
{
/* basic machine hardware */
SH4LE(config, m_maincpu, CPU_CLOCK);
SH7091(config, m_maincpu, CPU_CLOCK);
m_maincpu->set_md(0, 1);
m_maincpu->set_md(1, 0);
m_maincpu->set_md(2, 1);

2
src/mame/sega/naomigd.cpp
View File

@ -1066,7 +1066,7 @@ void naomi_gdrom_board::board_advance(uint32_t size)
void naomi_gdrom_board::device_add_mconfig(machine_config &config)
{
SH4LE(config, m_maincpu, CPU_CLOCK);
SH7091(config, m_maincpu, CPU_CLOCK);
m_maincpu->set_md(0, 1);
m_maincpu->set_md(1, 0);
m_maincpu->set_md(2, 1);

2
src/mame/sega/naomigd.h
View File

@ -140,7 +140,7 @@ private:
enum { FILENAME_LENGTH=24 };
int work_mode; // set it different from 0 to enable the cpus and full dimm board emulation
required_device<sh4_device> m_maincpu;
required_device<sh7091_device> m_maincpu;
required_device<pic16c622_device> m_securitycpu;
required_device<i2cmem_device> m_i2c0;
required_device<i2cmem_device> m_i2c1;

1
src/mame/sega/powervr2.cpp
View File

@ -17,7 +17,6 @@
#include "powervr2.h"
#include "dc.h"
#include "cpu/sh/sh4.h"
#include "video/rgbutil.h"
#include "rendutil.h"

2
src/mame/sega/segashiobd.cpp
View File

@ -79,7 +79,7 @@ void sega_837_14438_device::sh4_map(address_map &map)
void sega_837_14438_device::device_add_mconfig(machine_config &config)
{
SH4LE(config, m_maincpu, CPU_CLOCK);
SH4(config, m_maincpu, CPU_CLOCK);
m_maincpu->set_md(0, 1);
m_maincpu->set_md(1, 0);
m_maincpu->set_md(2, 1);

2
src/mame/sega/segasp.cpp
View File

@ -250,7 +250,7 @@ uint64_t segasp_state::sp_io_r(offs_t offset, uint64_t mem_mask)
void segasp_state::segasp_map(address_map &map)
{
/* Area 0 */
map(0x00000000, 0x001fffff).mirror(0xa2000000).rom().region("maincpu", 0); // BIOS
map(0x00000000, 0x001fffff).mirror(0x02000000).rom().region("maincpu", 0); // BIOS
map(0x005f6800, 0x005f69ff).mirror(0x02000000).rw(FUNC(segasp_state::dc_sysctrl_r), FUNC(segasp_state::dc_sysctrl_w));
map(0x005f6c00, 0x005f6cff).mirror(0x02000000).m(m_maple, FUNC(maple_dc_device::amap));

4
src/mame/sega/winclub.cpp
View File

@ -69,7 +69,7 @@ uint32_t winclub_state::screen_update(screen_device &screen, bitmap_rgb32 &bitma
void winclub_state::prg_map(address_map &map)
{
map(0x00000000, 0x007fffff).rom().mirror(0xe0000000).region("pcmcia", 0);
map(0x00000000, 0x007fffff).rom().region("pcmcia", 0);
}
static INPUT_PORTS_START( winclub ) // no dips on PCB
@ -88,7 +88,7 @@ INPUT_PORTS_END
void winclub_state::winclub(machine_config &config)
{
// basic machine hardware
sh4_device &maincpu(SH4LE(config, "maincpu", 14'318'000)); // TODO: SH-4 based custom, unknown type and clock
sh4_device &maincpu(SH4(config, "maincpu", 14'318'000)); // TODO: SH-4 based custom, unknown type and clock
maincpu.set_addrmap(AS_PROGRAM, &winclub_state::prg_map);
// maincpu.set_vblank_int("screen", FUNC(winclub_state::irq2_line_hold));

2
src/mame/sega/y2.cpp
View File

@ -61,7 +61,7 @@ INPUT_PORTS_END
void system_board_y2_state::system_board_y2(machine_config &config)
{
/*
SH4LE(config, m_maincpu, 266666666);
SH4(config, m_maincpu, 266666666);
m_maincpu->set_md(0, 1);
m_maincpu->set_md(1, 0);
m_maincpu->set_md(2, 1);

5
src/mame/skeleton/sh4robot.cpp
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@ -50,7 +50,7 @@ private:
void io_map(address_map &map) ATTR_COLD;
void mem_map(address_map &map) ATTR_COLD;
required_device<sh4_device> m_maincpu;
required_device<sh7750_device> m_maincpu;
};
@ -60,7 +60,6 @@ void sh4robot_state::mem_map(address_map &map)
map(0x00000000, 0x00000fff).rom();
map(0x08000000, 0x08ffffff).ram(); // SDRAM 1
map(0x0c000000, 0x0cffffff).ram(); // SDRAM 2
map(0xa0000000, 0xa0000fff).rom().region("maincpu", 0);
}
void sh4robot_state::io_map(address_map &map)
@ -74,7 +73,7 @@ INPUT_PORTS_END
void sh4robot_state::sh4robot(machine_config &config)
{
/* basic machine hardware */
SH4LE(config, m_maincpu, 200000000); // SH7750
SH7750(config, m_maincpu, 200000000);
m_maincpu->set_md(0, 1);
m_maincpu->set_md(1, 0);
m_maincpu->set_md(2, 1);

12
src/mame/yamaha/ympsr2000.cpp
View File

@ -27,7 +27,7 @@ public:
void psr2000(machine_config &config);
private:
required_device<sh3be_device> m_maincpu;
required_device<sh7709_device> m_maincpu;
required_device<sed1330_device> m_lcdc; // In reality a sed1335
void map(address_map &map) ATTR_COLD;
@ -42,7 +42,7 @@ void psr2000_state::machine_start()
void psr2000_state::psr2000(machine_config &config)
{
SH3BE(config, m_maincpu, 10_MHz_XTAL*4);
SH7709(config, m_maincpu, 10_MHz_XTAL*4, ENDIANNESS_BIG);
m_maincpu->set_addrmap(AS_PROGRAM, &psr2000_state::map);
auto &palette = PALETTE(config, "palette", palette_device::MONOCHROME_INVERTED);
@ -64,10 +64,10 @@ void psr2000_state::psr2000(machine_config &config)
void psr2000_state::map(address_map &map)
{
map(0x00000000, 0x007fffff).rom().region("maincpu", 0).mirror(0xe0000000);
map(0x08000000, 0x087fffff).rom().region("style", 0).mirror(0xe0000000);
map(0x0c000000, 0x0c7fffff).ram().mirror(0xe0000000);
map(0x10000000, 0x100fffff).rom().region("data", 0).mirror(0xe0000000);
map(0x00000000, 0x007fffff).rom().region("maincpu", 0);
map(0x08000000, 0x087fffff).rom().region("style", 0);
map(0x0c000000, 0x0c7fffff).ram();
map(0x10000000, 0x100fffff).rom().region("data", 0);
map(0x14000000, 0x1400000f); // 8bitcs -> lcdccs, fdccs
map(0x14400000, 0x14400000).rw(m_lcdc, FUNC(sed1330_device::status_r), FUNC(sed1330_device::data_w));
map(0x14400002, 0x14400002).rw(m_lcdc, FUNC(sed1330_device::data_r), FUNC(sed1330_device::command_w));