mirror of
https://github.com/holub/mame
synced 2025-05-28 16:43:04 +03:00
added 32x DRAM clear, needed by 32x tempo, pitfall, primal rage
This commit is contained in:
davidhay
parent
45a29c2c22
commit
b29e06704b
@ -105,8 +105,8 @@ static int _32x_240mode;
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static int sh2_master_vint_enable, sh2_slave_vint_enable;
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static int sh2_master_hint_enable, sh2_slave_hint_enable;
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static int sh2_master_cmdint_enable, sh2_slave_cmdint_enable;
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static int sh2_master_pwmint_enable, sh2_slave_pwnint_enable;
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static int sh2_master_pwmint_enable, sh2_slave_pwmint_enable;
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static int sh2_hint_in_vbl;
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#define SH2_VRES_IRQ_LEVEL 14
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#define SH2_VINT_IRQ_LEVEL 12
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@ -2528,6 +2528,81 @@ ADDRESS_MAP_END
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/****************************************** 32X related ******************************************/
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static UINT16 _32x_autofill_length;
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static UINT16 _32x_autofill_address;
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static UINT16 _32x_autofill_data;
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static READ16_HANDLER( _32x_68k_a15184_r )
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{
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return _32x_autofill_length;
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}
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static WRITE16_HANDLER( _32x_68k_a15184_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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_32x_autofill_length = data & 0xff;
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}
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if (ACCESSING_BITS_8_15)
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{
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}
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}
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static READ16_HANDLER( _32x_68k_a15186_r )
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{
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return _32x_autofill_address;
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}
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static WRITE16_HANDLER( _32x_68k_a15186_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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_32x_autofill_address = (_32x_autofill_address & 0xff00) | (data & 0x00ff);
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}
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if (ACCESSING_BITS_8_15)
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{
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_32x_autofill_address = (_32x_autofill_address & 0x00ff) | (data & 0xff00);
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}
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}
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static READ16_HANDLER( _32x_68k_a15188_r )
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{
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return _32x_autofill_data;
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}
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static WRITE16_HANDLER( _32x_68k_a15188_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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_32x_autofill_data = (_32x_autofill_data & 0xff00) | (data & 0x00ff);
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}
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if (ACCESSING_BITS_8_15)
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{
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_32x_autofill_data = (_32x_autofill_data & 0x00ff) | (data & 0xff00);
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}
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// do the fill - shouldn't be instant..
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{
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int i;
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UINT16 upper = _32x_autofill_address & 0xff00;
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UINT8 lower = _32x_autofill_address & 0x00ff;
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for (i=0; i<_32x_autofill_length+1;i++)
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{
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UINT16 address = upper | lower;
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_32x_access_dram[address] = _32x_autofill_data;
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lower++;
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}
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}
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}
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static READ16_HANDLER( _32x_68k_palette_r )
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{
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@ -2650,14 +2725,14 @@ static READ32_HANDLER( _32x_sh2_dram_r )
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{
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UINT32 retvalue = 0x00000000;
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if (ACCESSING_BITS_16_31) // 4108
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if (ACCESSING_BITS_16_31)
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{
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UINT16 ret = 0x0000;
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ret = _32x_68k_dram_r(machine,offset*2,(mem_mask>>16)&0xffff);
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retvalue |= ret << 16;
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}
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if (ACCESSING_BITS_0_15) // 4108
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if (ACCESSING_BITS_0_15)
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{
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UINT16 ret = 0x0000;
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ret = _32x_68k_dram_r(machine,offset*2+1,(mem_mask>>0)&0xffff);
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@ -2724,7 +2799,7 @@ static READ32_HANDLER( sh2_4108_410a_r )
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if (ACCESSING_BITS_16_31) // 4108
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{
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UINT16 ret = 0x0000;
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printf("sh2 read access 4108\n");
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ret = _32x_68k_a15188_r(machine, offset*2, mem_mask>>16); // autofill data
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retvalue |= (ret << 16);
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}
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if (ACCESSING_BITS_0_15) // 410a
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@ -2742,7 +2817,7 @@ static WRITE32_HANDLER( sh2_4108_410a_w )
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{
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if (ACCESSING_BITS_16_31) // 4108
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{
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printf("sh2 write access 4108\n");
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_32x_68k_a15188_w(machine,offset*2,(data>>16)&0xffff,(mem_mask>>16)&0xffff); // autofill data
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}
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if (ACCESSING_BITS_0_15) // 410a
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{
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@ -2750,6 +2825,19 @@ static WRITE32_HANDLER( sh2_4108_410a_w )
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}
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}
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static WRITE32_HANDLER( sh2_4104_4106_w )
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{
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if (ACCESSING_BITS_16_31) // 4104
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{
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_32x_68k_a15184_w(machine,offset*2,(data>>16)&0xffff,(mem_mask>>16)&0xffff); // autofill length
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}
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if (ACCESSING_BITS_0_15) // 4106
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{
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_32x_68k_a15186_w(machine,offset*2+1,(data>>0)&0xffff,(mem_mask>>0)&0xffff); // autofill address
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}
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}
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static READ16_HANDLER( _32x_68k_bitmapmode_r )
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@ -2833,10 +2921,15 @@ static WRITE32_HANDLER( sh2_4100_4102_w )
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}
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static ADDRESS_MAP_START( sh2_main_map, ADDRESS_SPACE_PROGRAM, 32 )
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AM_RANGE(0x00000000, 0x00003fff) AM_ROM
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AM_RANGE(0x00004100, 0x00004103) AM_READWRITE( sh2_4100_4102_r, sh2_4100_4102_w )
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AM_RANGE(0x00004104, 0x00004107) AM_WRITE( sh2_4104_4106_w )
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AM_RANGE(0x00004108, 0x0000410b) AM_READWRITE( sh2_4108_410a_r, sh2_4108_410a_w )
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AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE(_32x_sh2_palette_r, _32x_sh2_palette_w)
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@ -2846,12 +2939,14 @@ static ADDRESS_MAP_START( sh2_main_map, ADDRESS_SPACE_PROGRAM, 32 )
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AM_RANGE(0x06000000, 0x0603ffff) AM_RAM AM_SHARE(10)
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AM_RANGE(0x02000000, 0x023fffff) AM_ROM AM_REGION("gamecart_sh2", 0)
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AM_RANGE(0xc0000000, 0xc00003ff) AM_RAM
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AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( sh2_slave_map, ADDRESS_SPACE_PROGRAM, 32 )
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AM_RANGE(0x00000000, 0x00003fff) AM_ROM
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AM_RANGE(0x00004100, 0x00004103) AM_READWRITE( sh2_4100_4102_r, sh2_4100_4102_w )
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AM_RANGE(0x00004104, 0x00004107) AM_WRITE( sh2_4104_4106_w )
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AM_RANGE(0x00004108, 0x0000410b) AM_READWRITE( sh2_4108_410a_r, sh2_4108_410a_w )
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AM_RANGE(0x00004200, 0x000043ff) AM_READWRITE(_32x_sh2_palette_r, _32x_sh2_palette_w)
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@ -2861,7 +2956,7 @@ static ADDRESS_MAP_START( sh2_slave_map, ADDRESS_SPACE_PROGRAM, 32 )
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AM_RANGE(0x06000000, 0x0603ffff) AM_RAM AM_SHARE(10)
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AM_RANGE(0x02000000, 0x023fffff) AM_ROM AM_REGION("gamecart_sh2", 0)
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AM_RANGE(0xc0000000, 0xc00003ff) AM_RAM
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AM_RANGE(0xc0000000, 0xc0000fff) AM_RAM
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ADDRESS_MAP_END
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static ADDRESS_MAP_START( segacd_map, ADDRESS_SPACE_PROGRAM, 16 )
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@ -5939,9 +6034,7 @@ void megatech_set_megadrive_z80_as_megadrive_z80(running_machine *machine)
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// these are tests for 'special case' hardware to make sure I don't break anything while rearranging things
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//
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static UINT16 _32x_autofill_length;
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static UINT16 _32x_autofill_address;
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static UINT16 _32x_autofill_data;
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static UINT16 _32x_a15104;
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@ -6294,21 +6387,21 @@ UINT16 comms_port[8];
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static READ32_HANDLER( sh2_commsport_r )
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{
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timer_call_after_resynch(NULL, 0, NULL);
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// timer_call_after_resynch(NULL, 0, NULL);
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return (comms_port[offset*2] << 16) | (comms_port[offset*2+1]);
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}
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static READ16_HANDLER( _32x_68k_comms_r )
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{
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timer_call_after_resynch(NULL, 0, NULL);
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// timer_call_after_resynch(NULL, 0, NULL);
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return comms_port[offset];
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}
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static WRITE16_HANDLER( _32x_68k_comms_w )
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{
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COMBINE_DATA(&comms_port[offset]);
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timer_call_after_resynch(NULL, 0, NULL);
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// timer_call_after_resynch(NULL, 0, NULL);
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}
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@ -6330,7 +6423,7 @@ static WRITE32_HANDLER( sh2_commsport_w )
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//static int sh2_master_vint_enable, sh2_slave_vint_enable;
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//static int sh2_master_hint_enable, sh2_slave_hint_enable;
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//static int sh2_master_cmdint_enable, sh2_slave_cmdint_enable;
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//static int sh2_master_pwmint_enable, sh2_slave_pwnint_enable;
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//static int sh2_master_pwmint_enable, sh2_slave_pwmint_enable;
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static WRITE16_HANDLER( _sh2_master_irq_control_w )
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@ -6344,6 +6437,7 @@ static WRITE16_HANDLER( _sh2_master_irq_control_w )
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if (ACCESSING_BITS_0_7)
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{
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sh2_hint_in_vbl = data & 0x80;
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sh2_master_vint_enable = data & 0x8;
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sh2_master_hint_enable = data & 0x4;
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sh2_master_cmdint_enable = data & 0x2;
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@ -6366,13 +6460,14 @@ static WRITE16_HANDLER( _sh2_slave_irq_control_w )
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if (ACCESSING_BITS_0_7)
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{
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sh2_hint_in_vbl = data & 0x80;
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sh2_slave_vint_enable = data & 0x8;
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sh2_slave_hint_enable = data & 0x4;
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sh2_slave_cmdint_enable = data & 0x2;
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sh2_slave_pwnint_enable = data & 0x1;
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sh2_slave_pwmint_enable = data & 0x1;
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if (sh2_slave_hint_enable) printf("sh2_slave_hint_enable enable!\n");
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if (sh2_slave_pwnint_enable) printf("sh2_slave_pwm_enable enable!\n");
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if (sh2_slave_pwmint_enable) printf("sh2_slave_pwm_enable enable!\n");
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}
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}
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@ -6415,6 +6510,13 @@ static READ16_HANDLER( _32x_4000_master_r )
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{
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UINT16 retvalue = 0x0200;
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retvalue |= _32x_access_auth << 15;
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retvalue |= sh2_hint_in_vbl;;
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retvalue |= sh2_master_vint_enable;
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retvalue |= sh2_master_hint_enable;
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retvalue |= sh2_master_cmdint_enable;
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retvalue |= sh2_master_pwmint_enable;
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return retvalue;
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}
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@ -6422,6 +6524,12 @@ static READ16_HANDLER( _32x_4000_slave_r )
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{
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UINT16 retvalue = 0x0200;
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retvalue |= _32x_access_auth << 15;
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retvalue |= sh2_hint_in_vbl;;
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retvalue |= sh2_slave_vint_enable;
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retvalue |= sh2_slave_hint_enable;
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retvalue |= sh2_slave_cmdint_enable;
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retvalue |= sh2_slave_pwmint_enable;
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return retvalue;
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}
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@ -6486,68 +6594,6 @@ static READ32_HANDLER( sh2_4000_slave_r )
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static READ16_HANDLER( _32x_68k_a15184_r )
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{
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return _32x_autofill_length;
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}
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static WRITE16_HANDLER( _32x_68k_a15184_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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_32x_autofill_length = data & 0xff;
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printf("32x set autofill length to %02x\n",_32x_autofill_length);
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}
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if (ACCESSING_BITS_8_15)
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{
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}
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}
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static READ16_HANDLER( _32x_68k_a15186_r )
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{
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return _32x_autofill_address;
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}
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static WRITE16_HANDLER( _32x_68k_a15186_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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_32x_autofill_address = (_32x_autofill_address & 0xff00) | (data & 0x00ff);
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}
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if (ACCESSING_BITS_8_15)
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{
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_32x_autofill_address = (_32x_autofill_address & 0x00ff) | (data & 0xff00);
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}
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printf("32x set autofill address to %04x\n",_32x_autofill_address);
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}
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static READ16_HANDLER( _32x_68k_a15188_r )
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{
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return _32x_autofill_data;
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}
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static WRITE16_HANDLER( _32x_68k_a15188_w )
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{
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if (ACCESSING_BITS_0_7)
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{
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_32x_autofill_data = (_32x_autofill_data & 0xff00) | (data & 0x00ff);
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}
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if (ACCESSING_BITS_8_15)
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{
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_32x_autofill_data = (_32x_autofill_data & 0x00ff) | (data & 0xff00);
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}
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printf("32x set autofill data to %04x (performing fill)\n",_32x_autofill_data);
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}
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static READ16_HANDLER( _32x_68k_a15104_r )
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{
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@ -6641,7 +6687,7 @@ static int a15102_reg;
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static READ16_HANDLER( _32x_68k_a15102_r )
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{
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//printf("_32x_68k_a15102_r\n");
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return 0x0000;// a15102_reg;
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return 0x0000;//a15102_reg;
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}
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static WRITE16_HANDLER( _32x_68k_a15102_w )
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@ -6727,7 +6773,7 @@ DRIVER_INIT( _32x )
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sh2_master_vint_enable = sh2_slave_vint_enable = 0;
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sh2_master_hint_enable = sh2_slave_hint_enable = 0;
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sh2_master_cmdint_enable = sh2_slave_cmdint_enable = 0;
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sh2_master_pwmint_enable = sh2_slave_pwnint_enable = 0;
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sh2_master_pwmint_enable = sh2_slave_pwmint_enable = 0;
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// start in a reset state
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sh2_are_running = 0;
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@ -6743,6 +6789,10 @@ DRIVER_INIT( _32x )
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_32x_displaymode = 0;
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_32x_240mode = 0;
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// checking if these help brutal, they don't.
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// cpunum_set_info_int(2, CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
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// cpunum_set_info_int(3, CPUINFO_INT_SH2_DRC_OPTIONS, SH2DRC_STRICT_VERIFY|SH2DRC_STRICT_PCREL);
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DRIVER_INIT_CALL(megadriv);
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}
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@ -6765,13 +6815,14 @@ ROM_START( 32x_bios )
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// ROM_LOAD( "32x_koli.bin", 0x000000, 0x300000, CRC(20ca53ef) SHA1(191ae0b525ecf32664086d8d748e0b35f776ddfe) ) // works but needs very tight cpu sync or game just stutters
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// ROM_LOAD( "32x_head.bin", 0x000000, 0x300000, CRC(ef5553ff) SHA1(4e872fbb44ecb2bd730abd8cc8f32f96b10582c0) ) // doesn't boot
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// ROM_LOAD( "32x_pit.bin", 0x000000, 0x300000, CRC(f9126f15) SHA1(ee864d1677c6d976d0846eb5f8d8edb839acfb76) ) // ok, needs vram fill on intro screens tho?
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// ROM_LOAD( "32x_spid.bin", 0x000000, 0x300000, CRC(29dce257) SHA1(7cc2ea1e10f110338ad880bd3e7ff3bce72e7e9e) ) // needs cmdint status reads, overwrite image support wrong?
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// ROM_LOAD( "32x_spid.bin", 0x000000, 0x300000, CRC(29dce257) SHA1(7cc2ea1e10f110338ad880bd3e7ff3bce72e7e9e) ) // needs cmdint status reads, overwrite image support wrong? priority handling wrong??
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// ROM_LOAD( "32x_carn.bin", 0x000000, 0x300000, CRC(7c7be6a2) SHA1(9a563ed821b483148339561ebd2b876efa58847b) ) // ?? doesn't boot
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// ROM_LOAD( "32x_raw.bin", 0x000000, 0x400000, CRC(8eb7cd2c) SHA1(94b974f2f69f0c10bc18b349fa4ff95ca56fa47b) ) // needs cmdint status reads
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// ROM_LOAD( "32x_darx.bin", 0x000000, 0x200000, CRC(22d7c906) SHA1(108b4ffed8643abdefa921cfb58389b119b47f3d) ) // ?? probably abuses the hardware, euro only ;D
|
||||
// ROM_LOAD( "32x_prim.bin", 0x000000, 0x400000, CRC(e78a4d28) SHA1(5084dcca51d76173c383ab7d04cbc661673545f7) ) // needs screen clears
|
||||
// ROM_LOAD( "32x_prim.bin", 0x000000, 0x400000, CRC(e78a4d28) SHA1(5084dcca51d76173c383ab7d04cbc661673545f7) ) // needs tight sync or fails after sega logo - works with tight sync, but VERY slow
|
||||
// ROM_LOAD( "32x_brut.bin", 0x000000, 0x300000, CRC(7a72c939) SHA1(40aa2c787f37772cdbd7280b8be06b15421fabae) ) // locks up left in attract, doesn't scroll, no idea...
|
||||
// ROM_LOAD( "32x_temp.bin", 0x000000, 0x300000, CRC(14e5c575) SHA1(6673ba83570b4f2c1b4a22415a56594c3cc6c6a9) ) // needs ram fills and DREQ? (no main character)
|
||||
// ROM_LOAD( "32x_vr.bin", 0x000000, 0x300000, CRC(1) SHA1(1) ) // doesn't work
|
||||
|
||||
ROM_REGION32_BE( 0x400000, "gamecart_sh2", 0 ) /* Copy for the SH2 */
|
||||
ROM_COPY( "gamecart", 0x0, 0x0, 0x400000)
|
||||
|
||||
Loading…
Reference in New Issue
Block a user