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https://github.com/holub/mame
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buggychl.cpp: Soundlatch modernization, corrected clocks and added sound semaphores (nw)
This commit is contained in:
Lord-Nightmare
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ec7bafc62f
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b32c62dc29
@ -75,6 +75,16 @@ dcxx = /SPOSI (S36)
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2008-07
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Dip locations and factory settings verified from dip listing
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Clock information:
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Xtal = 48mhz
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QA output = "24M" = 24mhz
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QB output = "1/2CLK" = 12mhz
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QC output = "CLK" = 6mhz
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"1/2phi" = 24M / 3 = 8mhz
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The z80B main cpu is clocked by (depending on a jumper) either "1/2CLK"/2 OR "1/2PHI"/2, so either 6mhz or 4mhz.
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Schematics show the jumper set to the 6mhz setting.
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***************************************************************************/
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#include "emu.h"
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@ -94,33 +104,14 @@ WRITE8_MEMBER(buggychl_state::bankswitch_w)
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membank("bank1")->set_entry(data & 0x07); // shall we check if data&7 < # banks?
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}
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TIMER_CALLBACK_MEMBER(buggychl_state::nmi_callback)
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{
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if (m_sound_nmi_enable)
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m_audiocpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
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else
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m_pending_nmi = 1;
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}
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WRITE8_MEMBER(buggychl_state::sound_command_w)
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{
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m_soundlatch->write(space, 0, data);
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machine().scheduler().synchronize(timer_expired_delegate(FUNC(buggychl_state::nmi_callback),this), data);
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}
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WRITE8_MEMBER(buggychl_state::nmi_disable_w)
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{
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m_sound_nmi_enable = 0;
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m_soundnmi->in_w<1>(0);
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}
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WRITE8_MEMBER(buggychl_state::nmi_enable_w)
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{
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m_sound_nmi_enable = 1;
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if (m_pending_nmi)
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{
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m_audiocpu->set_input_line(INPUT_LINE_NMI, PULSE_LINE);
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m_pending_nmi = 0;
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}
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m_soundnmi->in_w<1>(1);
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}
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WRITE8_MEMBER(buggychl_state::sound_enable_w)
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@ -137,6 +128,24 @@ READ8_MEMBER(buggychl_state::mcu_status_r)
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((CLEAR_LINE != m_bmcu->mcu_semaphore_r()) ? 0x02 : 0x00);
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}
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// the schematics show that the two sound semaphore latch bits are actually flipped backwards when read by the sound cpu
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// vs when read by the main cpu.
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// Given the other schematic errors, is this even correct?
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// a cpu write to soundlatch sets ic12.2 so /Q is low, so cpu bit 1 and sound bit 0 read as clear
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// a sound write to soundlatch2 clears ic12.1 so /Q is high, so cpu bit 0 and sound bit 1 read as set
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// a cpu read of soundlatch2 sets ic12.1 so /Q is low, so cpu bit 0 and sound bit 1 read as clear
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// a sound read of soundlatch clears ic12.2 so /Q is high, so cpu bit 1 and sound bit 0 read as set
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// ic12.1 is set and ic12.2 is cleared by /SRESET
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READ8_MEMBER(buggychl_state::sound_status_main_r)
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{
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return (m_soundlatch2->pending_r() ? 1 : 0) | (m_soundlatch->pending_r() ? 0 : 2);
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}
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READ8_MEMBER(buggychl_state::sound_status_sound_r)
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{
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return (m_soundlatch2->pending_r() ? 2 : 0) | (m_soundlatch->pending_r() ? 0 : 1);
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}
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static ADDRESS_MAP_START( buggychl_map, AS_PROGRAM, 8, buggychl_state )
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AM_RANGE(0x0000, 0x3fff) AM_ROM /* A22-04 (23) */
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@ -161,7 +170,9 @@ static ADDRESS_MAP_START( buggychl_map, AS_PROGRAM, 8, buggychl_state )
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AM_RANGE(0xd609, 0xd609) AM_READ_PORT("IN1") /* coin + accelerator */
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// AM_RANGE(0xd60a, 0xd60a) // other inputs, not used?
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// AM_RANGE(0xd60b, 0xd60b) // other inputs, not used?
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AM_RANGE(0xd610, 0xd610) AM_WRITE(sound_command_w)
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AM_RANGE(0xd610, 0xd610) AM_DEVREAD("soundlatch2", generic_latch_8_device, read) AM_DEVWRITE("soundlatch", generic_latch_8_device, write)
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AM_RANGE(0xd611, 0xd611) AM_READ(sound_status_main_r)
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// AM_RANGE(0xd613, 0xd613) AM_WRITE(sound_reset_w)
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AM_RANGE(0xd618, 0xd618) AM_WRITENOP /* accelerator clear */
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AM_RANGE(0xd700, 0xd7ff) AM_DEVWRITE("palette", palette_device, write) AM_SHARE("palette")
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AM_RANGE(0xd840, 0xd85f) AM_WRITEONLY AM_SHARE("scrollv")
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@ -178,11 +189,10 @@ static ADDRESS_MAP_START( sound_map, AS_PROGRAM, 8, buggychl_state )
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AM_RANGE(0x4810, 0x481d) AM_DEVWRITE("msm", msm5232_device, write)
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AM_RANGE(0x4820, 0x4820) AM_RAM /* VOL/BAL for the 7630 on the MSM5232 output */
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AM_RANGE(0x4830, 0x4830) AM_RAM /* TRBL/BASS for the 7630 on the MSM5232 output */
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AM_RANGE(0x5000, 0x5000) AM_DEVREAD("soundlatch", generic_latch_8_device, read)
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// AM_RANGE(0x5001, 0x5001) AM_READNOP /* is command pending? */
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AM_RANGE(0x5001, 0x5001) AM_WRITE(nmi_enable_w)
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AM_RANGE(0x5000, 0x5000) AM_DEVREAD("soundlatch", generic_latch_8_device, read) AM_DEVWRITE("soundlatch2", generic_latch_8_device, write)
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AM_RANGE(0x5001, 0x5001) AM_READ(sound_status_sound_r) AM_WRITE(nmi_enable_w)
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AM_RANGE(0x5002, 0x5002) AM_WRITE(nmi_disable_w)
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AM_RANGE(0x5003, 0x5003) AM_WRITE(sound_enable_w)
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AM_RANGE(0x5003, 0x5003) AM_WRITE(sound_enable_w) // this actually controls the irq generation for the sound cpu as well as a few other things
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AM_RANGE(0xe000, 0xefff) AM_ROM /* space for diagnostics ROM */
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ADDRESS_MAP_END
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@ -345,8 +355,6 @@ void buggychl_state::machine_start()
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membank("bank1")->configure_entries(0, 6, &ROM[0x10000], 0x2000);
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save_item(NAME(m_sound_nmi_enable));
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save_item(NAME(m_pending_nmi));
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save_item(NAME(m_sprite_lookup));
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save_item(NAME(m_sl_bank));
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save_item(NAME(m_bg_on));
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@ -357,8 +365,6 @@ void buggychl_state::machine_start()
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void buggychl_state::machine_reset()
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{
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m_sound_nmi_enable = 0;
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m_pending_nmi = 0;
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m_sl_bank = 0;
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m_bg_on = 0;
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m_sky_on = 0;
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@ -369,19 +375,22 @@ void buggychl_state::machine_reset()
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static MACHINE_CONFIG_START( buggychl )
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/* basic machine hardware */
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MCFG_CPU_ADD("maincpu", Z80, 4000000) /* 4 MHz??? */
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MCFG_CPU_ADD("maincpu", Z80, XTAL_48MHz/8) /* 6 MHz according to schematics, though it can be jumpered for 4MHz as well */
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MCFG_CPU_PROGRAM_MAP(buggychl_map)
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MCFG_CPU_VBLANK_INT_DRIVER("screen", buggychl_state, irq0_line_hold)
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MCFG_CPU_ADD("audiocpu", Z80, 4000000) /* 4 MHz??? */
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MCFG_CPU_ADD("audiocpu", Z80, XTAL_8MHz/2) /* 4 MHz according to schematics */
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MCFG_CPU_PROGRAM_MAP(sound_map)
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MCFG_CPU_PERIODIC_INT_DRIVER(buggychl_state, irq0_line_hold, 60*60) /* irq is timed, tied to the cpu clock and not to vblank */
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/* nmi is caused by the main cpu */
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/* audiocpu nmi is caused by (main->sound semaphore)&&(sound_nmi_enabled), identical to bubble bobble. */
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// schematics show a secondary sound z80 cpu as well, running at the same speed as the audiocpu; unclear if actually populated, or if it only existed on a certain hardware release (cocktail deluxe version?)
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MCFG_DEVICE_ADD("bmcu", TAITO68705_MCU,8000000/2) /* 4 MHz */
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MCFG_WATCHDOG_ADD("watchdog")
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MCFG_WATCHDOG_VBLANK_INIT("screen", 128); // typical Taito 74ls392
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/* video hardware */
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MCFG_SCREEN_ADD("screen", RASTER)
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@ -402,6 +411,12 @@ static MACHINE_CONFIG_START( buggychl )
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MCFG_SPEAKER_STANDARD_MONO("mono")
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MCFG_GENERIC_LATCH_8_ADD("soundlatch")
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MCFG_GENERIC_LATCH_DATA_PENDING_CB(DEVWRITELINE("soundnmi", input_merger_device, in_w<0>))
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MCFG_INPUT_MERGER_ALL_HIGH("soundnmi")
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MCFG_INPUT_MERGER_OUTPUT_HANDLER(INPUTLINE("audiocpu", INPUT_LINE_NMI))
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MCFG_GENERIC_LATCH_8_ADD("soundlatch2")
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MCFG_SOUND_ADD("ay1", AY8910, 8000000/4)
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MCFG_AY8910_PORT_A_WRITE_CB(WRITE8(buggychl_state, port_a_0_w))
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@ -5,6 +5,7 @@
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*/
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#include "machine/taito68705interface.h"
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#include "machine/input_merger.h"
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#include "machine/gen_latch.h"
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#include "sound/msm5232.h"
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#include "screen.h"
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@ -25,8 +26,10 @@ public:
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m_msm(*this, "msm"),
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m_gfxdecode(*this, "gfxdecode"),
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m_screen(*this, "screen"),
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m_palette(*this, "palette") ,
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m_soundlatch(*this, "soundlatch") { }
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m_palette(*this, "palette"),
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m_soundnmi(*this, "soundnmi"),
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m_soundlatch(*this, "soundlatch"),
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m_soundlatch2(*this, "soundlatch2") { }
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/* memory pointers */
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required_shared_ptr<uint8_t> m_charram;
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@ -46,10 +49,6 @@ public:
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int m_bg_scrollx;
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uint8_t m_sprite_lookup[0x2000];
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/* sound-related */
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int m_sound_nmi_enable;
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int m_pending_nmi;
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/* devices */
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required_device<cpu_device> m_audiocpu;
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required_device<cpu_device> m_maincpu;
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@ -58,14 +57,17 @@ public:
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required_device<gfxdecode_device> m_gfxdecode;
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required_device<screen_device> m_screen;
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required_device<palette_device> m_palette;
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required_device<input_merger_device> m_soundnmi;
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required_device<generic_latch_8_device> m_soundlatch;
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required_device<generic_latch_8_device> m_soundlatch2;
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DECLARE_WRITE8_MEMBER(bankswitch_w);
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DECLARE_WRITE8_MEMBER(sound_command_w);
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DECLARE_WRITE8_MEMBER(nmi_disable_w);
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DECLARE_WRITE8_MEMBER(nmi_enable_w);
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DECLARE_WRITE8_MEMBER(sound_enable_w);
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DECLARE_READ8_MEMBER(mcu_status_r);
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DECLARE_READ8_MEMBER(sound_status_main_r);
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DECLARE_READ8_MEMBER(sound_status_sound_r);
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DECLARE_WRITE8_MEMBER(buggychl_chargen_w);
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DECLARE_WRITE8_MEMBER(buggychl_sprite_lookup_bank_w);
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DECLARE_WRITE8_MEMBER(buggychl_sprite_lookup_w);
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