Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-16 05:24:54 +03:00
Code Issues Actions 1 Packages Projects Releases Wiki Activity

nec.cpp: Add support for EXT reg,imm4 and INS reg,imm4 (#9793)

Browse Source
This commit is contained in:
wilbertpol 2022-05-21 14:36:09 +01:00 committed by GitHub
parent da91682bf5
commit b33946d980
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
1 changed files with 45 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

45
src/devices/cpu/nec/necinstr.hxx
View File

@ -45,6 +45,51 @@ OP( 0x0f, i_pre_nec ) { uint32_t ModRM, tmp, tmp2;
case 0x2a : ModRM = fetch(); tmp = GetRMByte(ModRM); tmp2 = (Breg(AL) & 0xf)<<4; Breg(AL) = (Breg(AL) & 0xf0) | (tmp&0xf); tmp = tmp2 | (tmp>>4); PutbackRMByte(ModRM,tmp); CLKM(17,17,13,32,32,19); break;
case 0x31 : ModRM = fetch(); ModRM=0; logerror("%06x: Unimplemented bitfield INS\n",PC()); break;
case 0x33 : ModRM = fetch(); ModRM=0; logerror("%06x: Unimplemented bitfield EXT\n",PC()); break;
case 0x39 : // INS reg,imm4
ModRM = fetch();
tmp = GetRMByte(ModRM) & 0x0f;
tmp2 = (fetch() & 0x0f) + 1;
PutMemW(DS1, Wreg(IY), (GetMemW(DS1, Wreg(IY)) & ~(((1 << tmp2) - 1) << tmp)) | ((Wreg(AW) & ((1 << tmp2) - 1)) << tmp));
if (tmp + tmp2 > 15) {
Wreg(IY) += 2;
PutMemW(DS1, Wreg(IY), (GetMemW(DS1, Wreg(IY)) & ~((1 << (tmp2 - (16 - tmp))) - 1)) | ((Wreg(AW) >> (16 - tmp)) & ((1 << (tmp2 - (16 - tmp))) - 1)));
}
PutRMByte(ModRM, (tmp + tmp2) & 0x0f);
// When and how many extra cycles are taken is not documented:
// V20: 75-103 cycles
// V30: 75-103 cycles, odd addresses
// V30: 67-87 cycles, even addresses
// V33: 39-77 cycles, odd addresses
// V33: 37-69 cycles, even addresses
if (Wreg(IY) & 1) {
CLKS(103, 103, 77);
} else {
CLKS(103, 87, 69);
}
break;
case 0x3b : // EXT reg,imm4
ModRM = fetch();
tmp = GetRMByte(ModRM) & 0x0f;
tmp2 = (fetch() & 0x0f) + 1;
Wreg(AW) = GetMemW(DS0, Wreg(IX)) >> tmp;
if (tmp + tmp2 > 15) {
Wreg(IX) += 2;
Wreg(AW) |= GetMemW(DS0, Wreg(IX)) << (16 - tmp);
}
Wreg(AW) &= ((1 << tmp2) - 1);
PutRMByte(ModRM, (tmp + tmp2) & 0x0f);
// When and how many extra cycles are taken is not documented:
// V20: 25-52 cycles
// V30: 25-52 cycles, odd addresses
// V30: 21-44 cycles, even addresses
// V33: 33-63 cycles, odd addresses
// V33: 29-61 cycles, even addresses
if (Wreg(IX) & 1) {
CLKS(52, 52, 63);
} else {
CLKS(52, 44, 62);
}
break;
case 0xe0 : BRKXA(true); CLK(12); break;
case 0xf0 : BRKXA(false); CLK(12); break;
case 0xff : BRKEM; CLK(50); break;