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Cleanups and version bump to 0.124u3.

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This commit is contained in:
Aaron Giles 2008-04-17 05:26:05 +00:00
parent 2028ecc2f7
commit b35c15fef5
25 changed files with 112 additions and 112 deletions
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2
src/mame/drivers/aerofgt.c
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@ -373,7 +373,7 @@ static ADDRESS_MAP_START( aerfboo2_map, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x0fe006, 0x0fe007) AM_WRITE(aerofgt_bg2scrolly_w)
AM_RANGE(0x0fe008, 0x0fe00b) AM_WRITE(turbofrc_gfxbank_w)
AM_RANGE(0x0fe010, 0x0fe011) AM_WRITENOP
// AM_RANGE(0x0fe012, 0x0fe013) AM_WRITE(aerfboot_soundlatch_w)
// AM_RANGE(0x0fe012, 0x0fe013) AM_WRITE(aerfboot_soundlatch_w)
AM_RANGE(0x0fe400, 0x0fe401) AM_WRITENOP
AM_RANGE(0x0fe402, 0x0fe403) AM_WRITENOP
AM_RANGE(0x0ff000, 0x0fffff) AM_RAM AM_BASE(&aerofgt_rasterram) /* used only for the scroll registers */

6
src/mame/drivers/taito_l.c
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@ -952,7 +952,7 @@ static ADDRESS_MAP_START( puzznici_readmem, ADDRESS_SPACE_PROGRAM, 8 )
COMMON_SINGLE_READ
AM_RANGE(0xa800, 0xa800) AM_READ(SMH_NOP) // Watchdog
AM_RANGE(0xb000, 0xb7ff) AM_READ(SMH_RAM) // Wrong, used to overcome protection
// AM_RANGE(0xb800, 0xb800) AM_READ(mcu_data_r)
// AM_RANGE(0xb800, 0xb800) AM_READ(mcu_data_r)
AM_RANGE(0xb801, 0xb801) AM_READ(mcu_control_r)
ADDRESS_MAP_END
@ -960,8 +960,8 @@ static ADDRESS_MAP_START( puzznici_writemem, ADDRESS_SPACE_PROGRAM, 8 )
COMMON_BANKS_WRITE
COMMON_SINGLE_WRITE
AM_RANGE(0xb000, 0xb7ff) AM_WRITE(SMH_RAM) // Wrong, used to overcome protection
// AM_RANGE(0xb800, 0xb800) AM_WRITE(mcu_data_w)
// AM_RANGE(0xb801, 0xb801) AM_WRITE(mcu_control_w)
// AM_RANGE(0xb800, 0xb800) AM_WRITE(mcu_data_w)
// AM_RANGE(0xb801, 0xb801) AM_WRITE(mcu_control_w)
AM_RANGE(0xbc00, 0xbc00) AM_WRITE(SMH_NOP) // Control register, function unknown
ADDRESS_MAP_END

42
src/mame/drivers/toaplan2.c
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@ -1432,8 +1432,8 @@ static ADDRESS_MAP_START( dogyuun_68k_mem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x200018, 0x200019) AM_READ_PORT("SYS")
AM_RANGE(0x20001c, 0x20001d) AM_WRITE(toaplan2_v25_coin_word_w)
#if USE_V25
// AM_RANGE(0x21e000, 0x21fbff) AM_READWRITE(shared_ram_r, shared_ram_w) AM_BASE(&toaplan2_shared_ram16) /* $21f000 status port */
// AM_RANGE(0x21fc00, 0x21ffff) AM_READWRITE(V25_sharedram_r, V25_sharedram_w) AM_BASE(&V25_shared_ram) /* 16-bit on 68000 side, 8-bit on V25+ side */
// AM_RANGE(0x21e000, 0x21fbff) AM_READWRITE(shared_ram_r, shared_ram_w) AM_BASE(&toaplan2_shared_ram16) /* $21f000 status port */
// AM_RANGE(0x21fc00, 0x21ffff) AM_READWRITE(V25_sharedram_r, V25_sharedram_w) AM_BASE(&V25_shared_ram) /* 16-bit on 68000 side, 8-bit on V25+ side */
AM_RANGE(0x210000, 0x21efff) AM_RAM AM_READWRITE( batsugun_share2_r, batsugun_share2_w )
AM_RANGE(0x21f000, 0x21ffff) AM_RAM AM_READWRITE( batsugun_share_r, batsugun_share_w )
#else
@ -1591,8 +1591,8 @@ static ADDRESS_MAP_START( fixeight_68k_mem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x200010, 0x200011) AM_READ_PORT("SYS")
AM_RANGE(0x20001c, 0x20001d) AM_WRITE(toaplan2_coin_word_w) /* Coin count/lock */
#if USE_V25
// AM_RANGE(0x28e000, 0x28fbff) AM_READWRITE(shared_ram_r, shared_ram_w) AM_BASE(&toaplan2_shared_ram16) /* $28f000 status port */
// AM_RANGE(0x28fc00, 0x28ffff) AM_READWRITE(V25_sharedram_r, V25_sharedram_w) AM_BASE(&V25_shared_ram) /* 16-bit on 68000 side, 8-bit on V25+ side */
// AM_RANGE(0x28e000, 0x28fbff) AM_READWRITE(shared_ram_r, shared_ram_w) AM_BASE(&toaplan2_shared_ram16) /* $28f000 status port */
// AM_RANGE(0x28fc00, 0x28ffff) AM_READWRITE(V25_sharedram_r, V25_sharedram_w) AM_BASE(&V25_shared_ram) /* 16-bit on 68000 side, 8-bit on V25+ side */
AM_RANGE(0x280000, 0x28efff) AM_RAM AM_READWRITE( batsugun_share2_r, batsugun_share2_w )
AM_RANGE(0x28f000, 0x28ffff) AM_RAM AM_READWRITE( batsugun_share_r, batsugun_share_w )
AM_RANGE(0x700000, 0x700001) AM_WRITE(fixeight_subcpu_ctrl) // guess!!!
@ -1653,8 +1653,8 @@ static ADDRESS_MAP_START( vfive_68k_mem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x200018, 0x200019) AM_READ_PORT("SYS")
AM_RANGE(0x20001c, 0x20001d) AM_WRITE(toaplan2_v25_coin_word_w) /* Coin count/lock */
#if USE_V25
// AM_RANGE(0x21e000, 0x21fbff) AM_READWRITE(shared_ram_r, shared_ram_w) AM_BASE(&toaplan2_shared_ram16) /* $21f000 status port */
// AM_RANGE(0x21fc00, 0x21ffff) AM_READWRITE(V25_sharedram_r, V25_sharedram_w) AM_BASE(&V25_shared_ram) /* 16-bit on 68000 side, 8-bit on V25+ side */
// AM_RANGE(0x21e000, 0x21fbff) AM_READWRITE(shared_ram_r, shared_ram_w) AM_BASE(&toaplan2_shared_ram16) /* $21f000 status port */
// AM_RANGE(0x21fc00, 0x21ffff) AM_READWRITE(V25_sharedram_r, V25_sharedram_w) AM_BASE(&V25_shared_ram) /* 16-bit on 68000 side, 8-bit on V25+ side */
AM_RANGE(0x210000, 0x21efff) AM_RAM AM_READWRITE( batsugun_share2_r, batsugun_share2_w )
AM_RANGE(0x21f000, 0x21ffff) AM_RAM AM_READWRITE( batsugun_share_r, batsugun_share_w )
#else
@ -1687,11 +1687,11 @@ static READ16_HANDLER( batsugun_share_r )
static WRITE16_HANDLER( batsugun_share_w )
{
/*
if (ACCESSING_BITS_8_15)
{
batsugun_share[offset] = data >> 8;
}
*/
if (ACCESSING_BITS_8_15)
{
batsugun_share[offset] = data >> 8;
}
*/
if (ACCESSING_BITS_0_7)
{
batsugun_share[offset] = data;
@ -1707,11 +1707,11 @@ static READ16_HANDLER( batsugun_share2_r )
static WRITE16_HANDLER( batsugun_share2_w )
{
/*
if (ACCESSING_BITS_8_15)
{
batsugun_share2[offset] = data >> 8;
}
*/
if (ACCESSING_BITS_8_15)
{
batsugun_share2[offset] = data >> 8;
}
*/
if (ACCESSING_BITS_0_7)
{
@ -1728,8 +1728,8 @@ static ADDRESS_MAP_START( batsugun_68k_mem, ADDRESS_SPACE_PROGRAM, 16 )
AM_RANGE(0x200018, 0x200019) AM_READ_PORT("SYS")
AM_RANGE(0x20001c, 0x20001d) AM_WRITE(toaplan2_v25_coin_word_w) /* Coin count/lock + v25 reset/hold control lines? */
#if USE_V25
// AM_RANGE(0x21e000, 0x21fbff) AM_READWRITE(shared_ram_r, shared_ram_w) AM_BASE(&toaplan2_shared_ram16) /* $21f000 status port */
// AM_RANGE(0x21fc00, 0x21ffff) AM_READWRITE(V25_sharedram_r, V25_sharedram_w) AM_BASE(&V25_shared_ram) /* 16-bit on 68000 side, 8-bit on V25+ side */
// AM_RANGE(0x21e000, 0x21fbff) AM_READWRITE(shared_ram_r, shared_ram_w) AM_BASE(&toaplan2_shared_ram16) /* $21f000 status port */
// AM_RANGE(0x21fc00, 0x21ffff) AM_READWRITE(V25_sharedram_r, V25_sharedram_w) AM_BASE(&V25_shared_ram) /* 16-bit on 68000 side, 8-bit on V25+ side */
AM_RANGE(0x210000, 0x21efff) AM_RAM AM_READWRITE( batsugun_share2_r, batsugun_share2_w )
AM_RANGE(0x21f000, 0x21ffff) AM_RAM AM_READWRITE( batsugun_share_r, batsugun_share_w )
#else
@ -2022,13 +2022,13 @@ static ADDRESS_MAP_START( V25_mem, ADDRESS_SPACE_PROGRAM, 8 )
AM_RANGE(0x04000, 0x04000) AM_READWRITE(YM2151_status_port_0_r, YM2151_register_port_0_w)
AM_RANGE(0x04001, 0x04001) AM_WRITE(YM2151_data_port_0_w)
AM_RANGE(0x04002, 0x04002) AM_READWRITE(OKIM6295_status_0_r, OKIM6295_data_0_w)
// AM_RANGE(0x04004, 0x04004) AM_WRITE(oki_bankswitch_w)
// AM_RANGE(0x04004, 0x04004) AM_WRITE(oki_bankswitch_w)
AM_RANGE(0x04008, 0x04008) AM_READ_PORT("IN1")
AM_RANGE(0x0400a, 0x0400a) AM_READ_PORT("IN2")
AM_RANGE(0x0400c, 0x0400c) AM_READ_PORT("SYS")
AM_RANGE(0x0400e, 0x0400e) AM_WRITE(toaplan2_coin_w)
AM_RANGE(0x0fe00, 0x0ffff) AM_RAM /* Internal 512 bytes of RAM */
// AM_RANGE(0x80000, 0x87fff) AM_RAM AM_BASE(&V25_sharedram) /* External shared RAM (ROM for KBASH) */
// AM_RANGE(0x80000, 0x87fff) AM_RAM AM_BASE(&V25_sharedram) /* External shared RAM (ROM for KBASH) */
ADDRESS_MAP_END
@ -3905,7 +3905,7 @@ MACHINE_RESET(batsugun)
void batsugun_ym2151_irqhandler(int linestate)
{
logerror("batsugun_ym2151_irqhandler %02x\n",linestate);
// update_irq_lines(Machine, linestate ? assert : clear);
// update_irq_lines(Machine, linestate ? assert : clear);
}
const struct YM2151interface batsugun_ym2151_interface =

10
src/mame/machine/seicop.c
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@ -1423,7 +1423,7 @@ READ16_HANDLER( cupsoc_mcu_r )
// return cop_mcu_ram[offset];
/* returning 0xffff for some inputs for now, breaks coinage but
allows cupsoc to boot */
allows cupsoc to boot */
case (0x300/2): return input_port_1_word_r(machine,0,0);
case (0x304/2): return input_port_2_word_r(machine,0,0);
case (0x308/2): return input_port_4_word_r(machine,0,0);
@ -1483,10 +1483,10 @@ WRITE16_HANDLER( cupsoc_mcu_w )
program_write_word(src+0x4,(y+y_rel));
program_write_word(src+0x8,(x+x_rel));
/*logerror("%08x %08x %08x %08x %08x\n",cop_register[0],
program_read_word(cop_reg[0]+0x4),
program_read_word(cop_reg[0]+0x8),
program_read_word(cop_reg[0]+0x10),
program_read_word(cop_reg[0]+0x14));*/
program_read_word(cop_reg[0]+0x4),
program_read_word(cop_reg[0]+0x8),
program_read_word(cop_reg[0]+0x10),
program_read_word(cop_reg[0]+0x14));*/
break;
}
/*???*/

30
src/mame/video/cps1.c
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@ -140,7 +140,7 @@ OUTPUT PORTS
TODO:
the scroll2/scroll3 disable bits are supported by the emulation,
while the scroll1 weird effect is not (it doesn't seem to make a
while the scroll1 weird effect is not (it doesn't seem to make a
difference on any game).
@ -1343,13 +1343,13 @@ if (cps1_game_config->priority[0] && offset == cps1_game_config->priority[0]/2 &
}
/*
The main CPU writes the palette to gfxram, and the CPS-B custom copies it
to the real palette RAM, which is separated from gfxram.
This is done ONLY after the palette base register is written to. It is not
known what the exact timing should be, how long it should take and when it
should happen. We are assuming that the copy happens immediately, since it
fixes glitches in the ghouls intro, but it might happen at next vblank.
*/
The main CPU writes the palette to gfxram, and the CPS-B custom copies it
to the real palette RAM, which is separated from gfxram.
This is done ONLY after the palette base register is written to. It is not
known what the exact timing should be, how long it should take and when it
should happen. We are assuming that the copy happens immediately, since it
fixes glitches in the ghouls intro, but it might happen at next vblank.
*/
if (offset == CPS1_PALETTE_BASE/2)
cps1_build_palette(machine, cps1_base(CPS1_PALETTE_BASE,cps1_palette_align));
}
@ -1614,7 +1614,7 @@ static int gfxrom_bank_mapper(running_machine *machine, int type, int code)
}
#ifdef MAME_DEBUG
// popmessage("tile %02x/%04x out of range", type,code>>shift);
// popmessage("tile %02x/%04x out of range", type,code>>shift);
#endif
return -1;
@ -1656,8 +1656,8 @@ static TILE_GET_INFO( get_tile0_info )
code = gfxrom_bank_mapper(machine, GFXTYPE_SCROLL1, code);
/* allows us to reproduce a problem seen with a ffight board where USA and Japanese
roms have been mixed to be reproduced (ffightua) -- it looks like each column
should alternate between the left and right side of the 16x16 tiles */
roms have been mixed to be reproduced (ffightua) -- it looks like each column
should alternate between the left and right side of the 16x16 tiles */
gfxset = (tile_index & 0x20) >> 5;
SET_TILE_INFO(
@ -1813,10 +1813,10 @@ static void cps1_build_palette(running_machine *machine, const UINT16* const pal
int ctrl = cps1_port(cps1_game_config->palette_control);
/*
The palette is copied only for pages that are enabled in the ctrl
register. Note that if the first palette pages are skipped, all
the following pages are scaled down.
*/
The palette is copied only for pages that are enabled in the ctrl
register. Note that if the first palette pages are skipped, all
the following pages are scaled down.
*/
for (page = 0; page < 6; ++page)
{
if (BIT(ctrl,page))

2
src/version.c
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@ -9,4 +9,4 @@
***************************************************************************/
const char build_version[] = "0.124u2 ("__DATE__")";
const char build_version[] = "0.124u3 ("__DATE__")";