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sparclite: update notes
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@ -16,6 +16,9 @@
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// - Test: SPARCv8 ops are untested
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// - Extended-precision FPU support
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// - Coprocessor support
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// - Finish SPARClite peripherals
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// - SPARClite m_wssr[0] should be 0x7ff40 at reset (32 wait cycles for CS0),
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// but that is problematic for Saitek Renaissance + Sparc module
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//
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//================================================================
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@ -661,9 +664,6 @@ void mb86930_device::device_reset()
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std::fill_n(&m_wssr[0], 3, 0);
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m_last_masked_addr = 0ULL;
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std::fill_n(&m_same_page_waits[0], 6, 0);
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std::fill_n(&m_other_page_waits[0], 6, 0);
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m_arsr[0] = (9 << 23);
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m_amr[0] = (0x1f << 1);
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@ -879,23 +879,18 @@ void mb86930_device::update_wait_states()
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const bool single = bool(BIT(m_wssr[i >> 1], shift + 1));
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//const bool override = bool(BIT(m_wssr[i >> 1], shift + 0));
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if (!BIT(m_ssctrl, 3) || enable == single)
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{
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m_other_page_waits[i] = 0;
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m_same_page_waits[i] = 0;
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}
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else if (single && !enable)
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{
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m_other_page_waits[i] = 1;
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m_same_page_waits[i] = 1;
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}
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else if (!single && enable)
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if (BIT(m_ssctrl, 3) && !single && enable)
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{
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const uint8_t count1 = ((m_wssr[i >> 1] >> (shift + 8)) & 0x1f) + 1;
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const uint8_t count2 = ((m_wssr[i >> 1] >> (shift + 3)) & 0x1f) + 1;
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m_other_page_waits[i] = count1;
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m_same_page_waits[i] = BIT(m_ssctrl, 5) ? count2 : count1;
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}
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else
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{
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m_other_page_waits[i] = 0;
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m_same_page_waits[i] = 0;
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}
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}
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}
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@ -4544,7 +4539,7 @@ void sparcv8_device::execute_div(uint32_t op)
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result = uint32_t(temp_64bit);
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temp_v = ((temp_64bit & 0xffffffff00000000) == 0) ? false : true;
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temp_v = ((temp_64bit & 0xffffffff00000000ULL) == 0) ? false : true;
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}
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else if (SDIV || SDIVCC)
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{
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@ -4553,7 +4548,7 @@ void sparcv8_device::execute_div(uint32_t op)
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result = uint32_t(temp_64bit);
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uint64_t shifted = uint64_t(temp_64bit) >> 31;
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temp_v = (shifted == 0 || shifted == 0x1ffffffff) ? false : true;
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temp_v = (shifted == 0 || shifted == 0x1ffffffffULL) ? false : true;
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}
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if (temp_v)
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