From b534f19fa8331d1f4bd250035a7f4b96a1a2f53d Mon Sep 17 00:00:00 2001 From: "therealmogminer@gmail.com" Date: Sun, 21 Aug 2016 13:39:58 +0200 Subject: [PATCH] -cmi2x: Hooked up serial callbacks, alphanumeric keyboard now works [Ryan Holtz] --- src/mame/drivers/cmi.cpp | 402 +++++++++++++++++++-------------------- 1 file changed, 196 insertions(+), 206 deletions(-) diff --git a/src/mame/drivers/cmi.cpp b/src/mame/drivers/cmi.cpp index 3f323d19845..b116f2a25c6 100644 --- a/src/mame/drivers/cmi.cpp +++ b/src/mame/drivers/cmi.cpp @@ -103,12 +103,15 @@ #include "cpu/m6800/m6800.h" #include "cpu/m68000/m68000.h" -#include "machine/msm5832.h" +#include "machine/clock.h" #include "machine/6821pia.h" #include "machine/6840ptm.h" #include "machine/6850acia.h" +#include "machine/mos6551.h" #include "machine/i8214.h" #include "machine/wd_fdc.h" +#include "machine/msm5832.h" +#include "machine/input_merger.h" #include "video/dl1416.h" #define Q209_CPU_CLOCK 4000000 // ? @@ -363,6 +366,10 @@ public: , m_q133_pia_0(*this, "q133_pia_1") , m_q133_pia_1(*this, "q133_pia_2") , m_q133_ptm(*this, "q133_ptm") + , m_q133_acia_0(*this, "q133_acia_0") + , m_q133_acia_1(*this, "q133_acia_1") + , m_q133_acia_2(*this, "q133_acia_2") + , m_q133_acia_3(*this, "q133_acia_3") , m_q133_region(*this, "q133") , m_q219_pia(*this, "q219_pia") , m_q219_ptm(*this, "q219_ptm") @@ -419,9 +426,16 @@ public: DECLARE_DRIVER_INIT( cmi2x ); + DECLARE_WRITE8_MEMBER( acia_control_w ); + DECLARE_WRITE8_MEMBER( acia_data_w ); + DECLARE_READ8_MEMBER( acia_status_r ); + DECLARE_READ8_MEMBER( acia_data_r ); + // CPU card - DECLARE_READ8_MEMBER( q133_acia_r ); - DECLARE_WRITE8_MEMBER( q133_acia_w ); + DECLARE_WRITE_LINE_MEMBER( q133_acia_irq0 ); + DECLARE_WRITE_LINE_MEMBER( q133_acia_irq1 ); + DECLARE_WRITE_LINE_MEMBER( q133_acia_irq2 ); + DECLARE_WRITE_LINE_MEMBER( q133_acia_irq3 ); DECLARE_WRITE8_MEMBER( i8214_cpu1_w ); DECLARE_WRITE8_MEMBER( i8214_cpu2_w ); DECLARE_WRITE_LINE_MEMBER( i8214_1_int_w ); @@ -480,10 +494,10 @@ public: DECLARE_WRITE8_MEMBER( master_tune_w ); // Alphanumeric keyboard - DECLARE_WRITE_LINE_MEMBER( ank_data_w ); DECLARE_READ8_MEMBER( ank_col_r ); - DECLARE_WRITE_LINE_MEMBER( ank_cts_w ); DECLARE_READ_LINE_MEMBER( ank_rts_r ); + DECLARE_WRITE_LINE_MEMBER( ank_irqa_w ); + DECLARE_WRITE_LINE_MEMBER( ank_irqb_w ); // ??? DECLARE_READ8_MEMBER( cmi07_r ); @@ -500,22 +514,11 @@ public: DECLARE_WRITE16_MEMBER( cmi_iix_update_dp2 ); DECLARE_WRITE16_MEMBER( cmi_iix_update_dp3 ); - DECLARE_READ_LINE_MEMBER( mkbd_kbd_rx ); - DECLARE_WRITE_LINE_MEMBER( mkbd_kbd_tx ); -#if 0 - DECLARE_READ_LINE_MEMBER( q133_rx ); - DECLARE_WRITE_LINE_MEMBER( q133_tx ); - DECLARE_WRITE_LINE_MEMBER( mkbd_cmi_w ); -#endif - DECLARE_READ_LINE_MEMBER( mkbd_cmi_rx ); - DECLARE_WRITE_LINE_MEMBER( mkbd_cmi_tx ); DECLARE_WRITE_LINE_MEMBER( msm5832_irq ); - DECLARE_WRITE_LINE_MEMBER( mkbd_acia1_int ); - DECLARE_WRITE_LINE_MEMBER( mkbd_acia2_int ); -#if 0 - DECLARE_WRITE_LINE_MEMBER( q133_acia_int ); -#endif + DECLARE_WRITE_LINE_MEMBER( mkbd_kbd_acia_int ); + DECLARE_WRITE_LINE_MEMBER( mkbd_cmi_acia_int ); DECLARE_WRITE_LINE_MEMBER( cmi07_irq ); + DECLARE_WRITE_LINE_MEMBER( mkbd_acia_clock ); protected: @@ -533,6 +536,10 @@ protected: required_device m_q133_pia_0; required_device m_q133_pia_1; required_device m_q133_ptm; + required_device m_q133_acia_0; + required_device m_q133_acia_1; + required_device m_q133_acia_2; + required_device m_q133_acia_3; required_memory_region m_q133_region; required_device m_q219_pia; @@ -592,11 +599,7 @@ protected: address_space *m_cpu2space; UINT8 *m_q133_rom; - UINT8 m_q133_acia_rx_data; -// UINT8 m_q133_acia_tx_data; - UINT8 m_q133_acia_status; - UINT8 m_q133_acia_cmd; - UINT8 m_q133_acia_ctrl; + UINT8 m_q133_acia_irq; private: @@ -661,11 +664,15 @@ private: /* Musical keyboard */ UINT8 m_msm5832_addr; - int m_mkbd_acia1_irq; - int m_mkbd_acia2_irq; + int m_mkbd_kbd_acia_irq; + int m_mkbd_cmi_acia_irq; int m_mkbd_tx_start; int m_mkbd_tx_bits; int m_mkbd_tx_reg; + + // Alphanumeric keyboard + int m_ank_irqa; + int m_ank_irqb; }; /************************************** @@ -856,7 +863,6 @@ READ8_MEMBER( cmi_state::rom_r ) WRITE8_MEMBER( cmi_state::map_ram_w ) { - //printf("map_ram_w: %04x = %02x\n", offset, data); if ((offset & 1) == 0) { m_map_ram_latch = data; @@ -890,14 +896,12 @@ READ8_MEMBER( cmi_state::map_r ) { int cpunum = (&space.device() == m_maincpu1) ? 0 : 1; UINT8 data = (m_cpu_active_space[1] << 2) | (m_cpu_active_space[0] << 1) | cpunum; - //printf("map_r %04x = %02x (%d)\n", offset, data, cpunum); return data; } WRITE8_MEMBER( cmi_state::map_w ) { int cpunum = (&space.device() == m_maincpu1) ? 0 : 1; - //printf("map_w %04x = %02x (%d)\n", offset, data, cpunum); m_map_switch_timer->adjust(attotime::from_ticks(data & 0xf, M6809_CLOCK), cpunum); } @@ -949,13 +953,13 @@ WRITE8_MEMBER( cmi_state::cpufunc_w ) int cpunum = data & 1; int idx = data & 6; int bit = (data & 8) >> 3; - //printf("cpufunc_w %04x = %02x cpunum:%d idx:%d bit:%d\n", offset, data, cpunum, idx, bit); switch (idx) { case 0: set_interrupt(cpunum, IRQ_IPI2_LEVEL, bit ? ASSERT_LINE : CLEAR_LINE); break; case 2: // TODO: Hardware trace + printf("TODO: Hardware trace %02x\n", data); break; case 4: m_cpu_map_switch[cpunum] = bit; break; @@ -976,7 +980,6 @@ READ8_MEMBER( cmi_state::parity_r ) WRITE8_MEMBER( cmi_state::mapsel_w ) { - //printf("mapsel_w %04x = %02x\n", offset, data); data ^= 0x1f; m_map_sel[offset] = data; @@ -1020,6 +1023,34 @@ static ADDRESS_MAP_START( maincpu2_map, AS_PROGRAM, 8, cmi_state ) AM_RANGE(0xfffe, 0xffff) AM_READ(vector_r) ADDRESS_MAP_END + +READ8_MEMBER( cmi_state::acia_status_r ) +{ + UINT8 ret = m_acia_mkbd_cmi->status_r(space, offset); + //printf("cmi acia_status_r: %02x\n", ret); + return ret; +} + +READ8_MEMBER( cmi_state::acia_data_r ) +{ + UINT8 ret = m_acia_mkbd_cmi->data_r(space, offset); + //printf("cmi acia_data_r: %02x\n", ret); + machine().debug_break(); + return ret; +} + +WRITE8_MEMBER( cmi_state::acia_data_w ) +{ + m_acia_mkbd_cmi->data_w(space, offset, data, mem_mask); + //printf("cmi acia_data_w: %02x\n", data); +} + +WRITE8_MEMBER( cmi_state::acia_control_w ) +{ + m_acia_mkbd_cmi->control_w(space, offset, data, mem_mask); + //printf("cmi acia_control_w: %02x\n", data); +} + static ADDRESS_MAP_START( muskeys_map, AS_PROGRAM, 8, cmi_state) ADDRESS_MAP_UNMAP_HIGH AM_RANGE(0x0000, 0x007f) AM_RAM @@ -1027,8 +1058,10 @@ static ADDRESS_MAP_START( muskeys_map, AS_PROGRAM, 8, cmi_state) AM_RANGE(0x0090, 0x0093) AM_DEVREADWRITE("cmi10_pia_u20", pia6821_device, read, write) AM_RANGE(0x00a0, 0x00a0) AM_DEVREADWRITE("acia_mkbd_kbd", acia6850_device, status_r, control_w) AM_RANGE(0x00a1, 0x00a1) AM_DEVREADWRITE("acia_mkbd_kbd", acia6850_device, data_r, data_w) - AM_RANGE(0x00b0, 0x00b0) AM_DEVREADWRITE("acia_mkbd_cmi", acia6850_device, status_r, control_w) - AM_RANGE(0x00b1, 0x00b1) AM_DEVREADWRITE("acia_mkbd_cmi", acia6850_device, data_r, data_w) + //AM_RANGE(0x00b0, 0x00b0) AM_DEVREADWRITE("acia_mkbd_cmi", acia6850_device, status_r, control_w) + //AM_RANGE(0x00b1, 0x00b1) AM_DEVREADWRITE("acia_mkbd_cmi", acia6850_device, data_r, data_w) + AM_RANGE(0x00b0, 0x00b0) AM_READWRITE(acia_status_r, acia_control_w) + AM_RANGE(0x00b1, 0x00b1) AM_READWRITE(acia_data_r, acia_data_w) AM_RANGE(0x4000, 0x47ff) AM_RAM AM_RANGE(0xb000, 0xb400) AM_ROM AM_RANGE(0xf000, 0xffff) AM_ROM @@ -1393,52 +1426,28 @@ READ8_MEMBER( cmi_state::cmi07_r ) return 0xff; } -READ8_MEMBER( cmi_state::q133_acia_r ) +WRITE_LINE_MEMBER( cmi_state::q133_acia_irq0 ) { - int acia = (offset >> 2) & 3; - - if (acia != 0) - return 0; - - switch (offset & 3) - { - case 0: - /* Clear RDRF */ - m_q133_acia_status &= ~0x08; - set_interrupt(CPU_1, IRQ_ACINT_LEVEL, CLEAR_LINE); - return m_q133_acia_rx_data; - case 1: - m_q133_acia_status &= ~0x80; - return m_q133_acia_status | 0x10; - case 2: return m_q133_acia_cmd; - case 3: return m_q133_acia_ctrl; - } - - return 0; - -// return m_133_acia->read(0); + m_q133_acia_irq = (m_q133_acia_irq & ~1) | state; + set_interrupt(CPU_1, IRQ_ACINT_LEVEL, m_q133_acia_irq ? ASSERT_LINE : CLEAR_LINE); } -WRITE8_MEMBER( cmi_state::q133_acia_w ) +WRITE_LINE_MEMBER( cmi_state::q133_acia_irq1 ) { - int acia = (offset >> 2) & 3; - - if (acia != 0) - return; - - switch (offset & 3) - { - case 0: break;//printf("%c\n", data); break; // TODO - case 1: break; // Reset - case 2: m_q133_acia_cmd = data; break; - case 3: m_q133_acia_ctrl = data; break; - } - -// m_q133_acia->write(offset & 3, data); + m_q133_acia_irq = (m_q133_acia_irq & ~2) | (state << 1); + set_interrupt(CPU_1, IRQ_ACINT_LEVEL, m_q133_acia_irq ? ASSERT_LINE : CLEAR_LINE); } -WRITE_LINE_MEMBER( cmi_state::ank_data_w ) +WRITE_LINE_MEMBER( cmi_state::q133_acia_irq2 ) { + m_q133_acia_irq = (m_q133_acia_irq & ~4) | (state << 2); + set_interrupt(CPU_1, IRQ_ACINT_LEVEL, m_q133_acia_irq ? ASSERT_LINE : CLEAR_LINE); +} + +WRITE_LINE_MEMBER( cmi_state::q133_acia_irq3 ) +{ + m_q133_acia_irq = (m_q133_acia_irq & ~8) | (state << 3); + set_interrupt(CPU_1, IRQ_ACINT_LEVEL, m_q133_acia_irq ? ASSERT_LINE : CLEAR_LINE); } READ8_MEMBER( cmi_state::ank_col_r ) @@ -1495,7 +1504,6 @@ void cmi_state::dma_fdc_rom() /* TODO: This should be stuck in a deferred write */ int cnt = std::min(m_fdc_dma_cnt.w.l ^ 0xffff, 2048); - //printf("cnt is %d\n", cnt); memcpy(&m_q256_ram[i][(p_info & 0x7f) * PAGE_SIZE], m_qfc9_region_ptr, cnt); m_fdc_status |= FDC_STATUS_DRIVER_LOAD; @@ -1509,7 +1517,6 @@ void cmi_state::write_fdc_ctrl(UINT8 data) int drive = data & 1; int side = BIT(data, 5) ? 1 : 0; - //printf("write_fdc_ctrl: drive:%d side:%d dd:%d data:%02x\n", drive, side, BIT(data, 7) ? 1 : 0, data); if (drive) { m_floppy_1->ss_w(side); @@ -1527,21 +1534,20 @@ void cmi_state::write_fdc_ctrl(UINT8 data) WRITE8_MEMBER( cmi_state::fdc_w ) { - //printf("fdc_w: %04x = %02x\n", offset, data); fflush(stdout); if (offset == 0) { switch (m_fdc_addr) { - case 0x0: /*printf("write_fdc_ctrl: %02x\n", data);*/ write_fdc_ctrl(data); break; - case 0x2: /*printf("fdc_dma_addr : %02x\n", data);*/ m_fdc_dma_addr.b.l = data; break; - case 0x4: /*printf("fdc_dma_addr hi: %02x\n", data);*/ m_fdc_dma_addr.b.h = data; break; - case 0x6: /*printf("fdc_dma_cnt lo: %02x\n", data);*/ m_fdc_dma_cnt.b.l = data; break; - case 0x8: /*printf("fdc_dma_cnt hi: %02x\n", data);*/ m_fdc_dma_cnt.b.h = data; break; - case 0xa: /*printf("dma_fdc_rom\n");*/ dma_fdc_rom(); break; - case 0xc: /*printf("cmd_w: %02x\n", data);*/ m_wd1791->cmd_w(data ^ 0xff); break; - case 0xd: /*printf("track_w: %02x\n", data);*/ m_wd1791->track_w(data ^ 0xff); break; - case 0xe: /*printf("sector_w: %02x\n", data);*/ m_wd1791->sector_w(data ^ 0xff); break; - case 0xf: /*printf("data_w: %02x\n", data);*/ m_wd1791->data_w(data ^ 0xff); break; + case 0x0: write_fdc_ctrl(data); break; + case 0x2: m_fdc_dma_addr.b.l = data; break; + case 0x4: m_fdc_dma_addr.b.h = data; break; + case 0x6: m_fdc_dma_cnt.b.l = data; break; + case 0x8: m_fdc_dma_cnt.b.h = data; break; + case 0xa: dma_fdc_rom(); break; + case 0xc: m_wd1791->cmd_w(data ^ 0xff); break; + case 0xd: m_wd1791->track_w(data ^ 0xff); break; + case 0xe: m_wd1791->sector_w(data ^ 0xff); break; + case 0xf: m_wd1791->data_w(data ^ 0xff); break; default: printf("fdc_w: Invalid access (%x with %x)", m_fdc_addr, data); } } @@ -1555,10 +1561,10 @@ READ8_MEMBER( cmi_state::fdc_r ) { switch (m_fdc_addr) { - case 0xc: { UINT8 ret = m_wd1791->status_r(); /*printf("status_r: %02x\n", ret);*/ return ret ^ 0xff; } - case 0xd: { UINT8 ret = m_wd1791->track_r(); /*printf("track_r: %02x\n", ret);*/ return ret ^ 0xff; } - case 0xe: { UINT8 ret = m_wd1791->sector_r(); /*printf("sector_r: %02x\n", ret);*/ return ret ^ 0xff; } - case 0xf: { UINT8 ret = m_wd1791->data_r(); /*printf("data_r: %02x\n", ret);*/ return ret ^ 0xff; } + case 0xc: { return m_wd1791->status_r() ^ 0xff; } + case 0xd: { return m_wd1791->track_r() ^ 0xff; } + case 0xe: { return m_wd1791->sector_r() ^ 0xff; } + case 0xf: { return m_wd1791->data_r() ^ 0xff; } default: return 0; } } @@ -1575,13 +1581,10 @@ void cmi_state::fdc_dma_transfer() /* Transfer from disk to RAM */ if (!BIT(m_fdc_ctrl, 4)) { - //printf("fdc_dma_transfer: Transfer from disk to RAM\n"); /* Determine the initial page */ int cpu_page = (m_fdc_dma_addr.w.l & ~PAGE_MASK) / PAGE_SIZE; int phys_page = 0; - //printf("fdc_dma_transfer: m_fdc_dma_addr (RAM addr): %04x\n", m_fdc_dma_addr.w.l); - // printf("FDC DMA: Disk to [%x] (%x bytes)\n", m_fdc_dma_addr.w.l, m_fdc_dma_cnt.w.l ^ 0xffff); int i; @@ -1595,14 +1598,11 @@ void cmi_state::fdc_dma_transfer() //phys_page &= 0x7f; - //printf("fdc_dma_transfer: fdc_dma_cnt is %04x, drq is %d\n", m_fdc_dma_cnt.w.l, m_fdc_drq); - for (; m_fdc_dma_cnt.w.l < 0xffff && m_fdc_drq; m_fdc_dma_cnt.w.l++) { /* Read a byte at a time */ UINT8 data = m_wd1791->data_r() ^ 0xff; - //printf("fdc_dma_transfer, data %02x\n", data); if (m_cmi07_ctrl & 0x30) if (BIT(m_cmi07_ctrl, 6) && !BIT(m_cmi07_ctrl, 7)) { @@ -1630,25 +1630,16 @@ void cmi_state::fdc_dma_transfer() } } } - - /* HACK */ - while (m_fdc_drq) - { - //printf("fdc_dma_transfer: fdc_drq is still set; emptying wd1791 until it is lowered\n"); - m_wd1791->data_r(); - } } // Transfer from RAM to disk else { - //printf("fdc_dma_transfer: Transfer from RAM to disk\n"); /* TODO: Check me and combine common code with the above */ /* Determine the initial page */ int cpu_page = (m_fdc_dma_addr.w.l & ~PAGE_MASK) / PAGE_SIZE; int phys_page = 0; - //printf("fdc_dma_transfer: m_fdc_dma_addr (RAM addr): %04x\n", m_fdc_dma_addr.w.l); int i; for (i = 0; i < NUM_Q256_CARDS; ++i) { @@ -1660,8 +1651,6 @@ void cmi_state::fdc_dma_transfer() phys_page &= 0x7f; - //printf("fdc_dma_transfer: fdc_dma_cnt is %04x, drq is %d\n", m_fdc_dma_cnt.w.l, m_fdc_drq); - for (; m_fdc_dma_cnt.w.l < 0xffff && m_fdc_drq; m_fdc_dma_cnt.w.l++) { /* Write a byte at a time */ @@ -1671,7 +1660,6 @@ void cmi_state::fdc_dma_transfer() if (phys_page & 0x80) data = m_q256_ram[i][((phys_page & 0x7f) * PAGE_SIZE) + (m_fdc_dma_addr.w.l & PAGE_MASK)]; - //printf("fdc_dma_transfer: writing data %02x to controller\n", data); m_wd1791->data_w(data ^ 0xff); /* TODO: Is updating these correct? */ @@ -1720,7 +1708,6 @@ WRITE_LINE_MEMBER( cmi_state::wd1791_irq ) WRITE_LINE_MEMBER( cmi_state::wd1791_drq ) { m_fdc_drq = state; - //printf("m_fdc_drq: %d\n", state); if (state) fdc_dma_transfer(); } @@ -2124,10 +2111,24 @@ WRITE8_MEMBER( cmi_state::shared_ram_w ) m_shared_ram[offset] = data; } - -WRITE_LINE_MEMBER( cmi_state::ank_cts_w ) +WRITE_LINE_MEMBER( cmi_state::ank_irqa_w ) { -// printf("ANK CTS: %x\n", state); + m_ank_irqa = state; + + if (m_ank_irqa) + m_alphakeyscpu->set_input_line(M6802_IRQ_LINE, ASSERT_LINE); + else if(!m_ank_irqb) + m_alphakeyscpu->set_input_line(M6802_IRQ_LINE, CLEAR_LINE); +} + +WRITE_LINE_MEMBER( cmi_state::ank_irqb_w ) +{ + m_ank_irqb = state; + + if (m_ank_irqb) + m_alphakeyscpu->set_input_line(M6802_IRQ_LINE, ASSERT_LINE); + else if(!m_ank_irqa) + m_alphakeyscpu->set_input_line(M6802_IRQ_LINE, CLEAR_LINE); } READ_LINE_MEMBER( cmi_state::ank_rts_r ) @@ -2148,7 +2149,6 @@ READ_LINE_MEMBER( cmi01a_device::zx_r ) void cmi_state::install_peripherals(int cpunum) { - //printf("Installing peripherals for CPU %d\n", cpunum + 1); address_space *space = (cpunum == CPU_1 ? m_cpu1space : m_cpu2space); space->install_readwrite_handler(0xe000, 0xe03f, read8_delegate(FUNC(cmi_state::cmi02_r),this), write8_delegate(FUNC(cmi_state::cmi02_w),this)); @@ -2161,7 +2161,11 @@ void cmi_state::install_peripherals(int cpunum) //space->install_readwrite_handler(0xfc5a, 0xfc5b, SMH_NOP, SMH_NOP); // Q077 HDD controller - not installed space->install_readwrite_handler(0xfc5e, 0xfc5e, read8_delegate(FUNC(cmi_state::atomic_r),this), write8_delegate(FUNC(cmi_state::cpufunc_w),this)); space->install_readwrite_handler(0xfc5f, 0xfc5f, read8_delegate(FUNC(cmi_state::map_r),this), write8_delegate(FUNC(cmi_state::map_w),this)); - space->install_readwrite_handler(0xfc80, 0xfc8f, read8_delegate(FUNC(cmi_state::q133_acia_r),this), write8_delegate(FUNC(cmi_state::q133_acia_w),this)); + + space->install_readwrite_handler(0xfc80, 0xfc83, read8_delegate(FUNC(mos6551_device::read),m_q133_acia_0.target()), write8_delegate(FUNC(mos6551_device::write),m_q133_acia_0.target())); + space->install_readwrite_handler(0xfc84, 0xfc87, read8_delegate(FUNC(mos6551_device::read),m_q133_acia_1.target()), write8_delegate(FUNC(mos6551_device::write),m_q133_acia_1.target())); + space->install_readwrite_handler(0xfc88, 0xfc8b, read8_delegate(FUNC(mos6551_device::read),m_q133_acia_2.target()), write8_delegate(FUNC(mos6551_device::write),m_q133_acia_2.target())); + space->install_readwrite_handler(0xfc8c, 0xfc8f, read8_delegate(FUNC(mos6551_device::read),m_q133_acia_3.target()), write8_delegate(FUNC(mos6551_device::write),m_q133_acia_3.target())); space->install_readwrite_handler(0xfc90, 0xfc97, read8_delegate(FUNC(ptm6840_device::read),m_q133_ptm.target()), write8_delegate(FUNC(ptm6840_device::write),m_q133_ptm.target())); space->install_readwrite_handler(0xfcbc, 0xfcbc, read8_delegate(FUNC(cmi_state::cmi07_r),this), write8_delegate(FUNC(cmi_state::cmi07_w),this)); @@ -2529,63 +2533,16 @@ READ8_MEMBER( cmi_state::cmi10_u21_a_r ) //static int kbd_to_cmi; //static int cmi_to_kbd; -READ_LINE_MEMBER( cmi_state::mkbd_kbd_rx ) +WRITE_LINE_MEMBER( cmi_state::mkbd_acia_clock ) { - return m_ank_pia->cb2_output(); -} - -WRITE_LINE_MEMBER( cmi_state::mkbd_kbd_tx ) -{ -} - -#if 0 -READ_LINE_MEMBER( cmi_state::q133_rx ) -{ - return m_kbd_to_cmi; -} - -WRITE_LINE_MEMBER( cmi_state::q133_tx ) -{ - m_cmi_to_kbd = state; -} - -WRITE_LINE_MEMBER( cmi_state::mkbd_cmi_w ) -{ - -} -#endif - -READ_LINE_MEMBER( cmi_state::mkbd_cmi_rx ) -{ - return 1;//cmi_to_kbd; -} - -WRITE_LINE_MEMBER( cmi_state::mkbd_cmi_tx ) -{ -// kbd_to_cmi = state; - - if (m_mkbd_tx_start == 0) - { - if (!state) - { - m_mkbd_tx_start = 1; - m_mkbd_tx_bits = 10; - m_mkbd_tx_reg = 0; - } - } - else if (m_mkbd_tx_start) - { - m_mkbd_tx_reg = m_mkbd_tx_reg | state << (10 - m_mkbd_tx_bits); - - if (--m_mkbd_tx_bits == 0) - { - m_q133_acia_rx_data = m_mkbd_tx_reg & 0xff; - m_q133_acia_status |= 0x88; - set_interrupt(CPU_1, IRQ_ACINT_LEVEL, ASSERT_LINE); -// printf("%x\n",q133_acia_rx_data); - m_mkbd_tx_start = 0; - } - } + m_acia_mkbd_kbd->write_rxc(state); + m_acia_mkbd_kbd->write_txc(state); + m_acia_mkbd_cmi->write_rxc(state); + m_acia_mkbd_cmi->write_txc(state); + m_q133_acia_0->write_rxc(state); + m_q133_acia_1->write_rxc(state); + m_q133_acia_2->write_rxc(state); + m_q133_acia_3->write_rxc(state); } WRITE_LINE_MEMBER( cmi_state::msm5832_irq ) @@ -2595,33 +2552,30 @@ WRITE_LINE_MEMBER( cmi_state::msm5832_irq ) #endif } -WRITE_LINE_MEMBER( cmi_state::mkbd_acia1_int ) +WRITE_LINE_MEMBER( cmi_state::mkbd_kbd_acia_int ) { - m_mkbd_acia1_irq = state; + m_mkbd_kbd_acia_irq = state; - if (m_mkbd_acia1_irq) + if (m_mkbd_kbd_acia_irq) + { m_muskeyscpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE); - else if (!m_mkbd_acia2_irq) + } + else if (!m_mkbd_cmi_acia_irq) + { + m_muskeyscpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE); + } +} + +WRITE_LINE_MEMBER( cmi_state::mkbd_cmi_acia_int ) +{ + m_mkbd_cmi_acia_irq = state; + + if (m_mkbd_cmi_acia_irq) + m_muskeyscpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE); + else if (!m_mkbd_kbd_acia_irq) m_muskeyscpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE); } -WRITE_LINE_MEMBER( cmi_state::mkbd_acia2_int ) -{ - m_mkbd_acia2_irq = state; - - if (m_mkbd_acia2_irq) - m_muskeyscpu->set_input_line(INPUT_LINE_IRQ0, ASSERT_LINE); - else if (!m_mkbd_acia1_irq) - m_muskeyscpu->set_input_line(INPUT_LINE_IRQ0, CLEAR_LINE); -} - -#if 0 -WRITE_LINE_MEMBER( cmi_state::q133_acia_int ) -{ - m_maincpu1->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE); -} -#endif - WRITE_LINE_MEMBER( cmi_state::cmi07_irq ) { m_cmi07cpu->set_input_line(INPUT_LINE_IRQ0, state ? ASSERT_LINE : CLEAR_LINE); @@ -2670,6 +2624,10 @@ void cmi_state::machine_reset() m_cmi10_scnd_timer->adjust(attotime::from_hz(4000000 / 4 / 2048 / 2), 0, attotime::from_hz(4000000 / 4 / 2048 / 2)); m_scnd = 0; + + m_ank_irqa = 0; + m_ank_irqb = 0; + m_q133_acia_irq = 0; } void cmi_state::machine_start() @@ -2747,9 +2705,9 @@ static MACHINE_CONFIG_START( cmi2x, cmi_state ) MCFG_CPU_ADD("muskeys", M6802, 3840000) MCFG_CPU_PROGRAM_MAP(muskeys_map) - MCFG_CPU_ADD("alphakeys", M6802, 4000000) + MCFG_CPU_ADD("alphakeys", M6802, 3840000) MCFG_CPU_PROGRAM_MAP(alphakeys_map) - MCFG_CPU_PERIODIC_INT_DRIVER(cmi_state, irq0_line_hold, 9600) // TODO: ACIA controls this + MCFG_CPU_PERIODIC_INT_DRIVER(cmi_state, irq0_line_hold, 9600) // TODO: PIA controls this MCFG_CPU_ADD("smptemidi", M68000, 10000000) MCFG_CPU_PROGRAM_MAP(midicpu_map) @@ -2811,24 +2769,56 @@ static MACHINE_CONFIG_START( cmi2x, cmi_state ) MCFG_DEVICE_ADD("cmi02_ptm", PTM6840, 0) // ptm_cmi02_config MCFG_PTM6840_INTERNAL_CLOCK(2000000) // TODO + MCFG_DEVICE_ADD("mkbd_acia_clock", CLOCK, 9600*16) + MCFG_CLOCK_SIGNAL_HANDLER(WRITELINE(cmi_state, mkbd_acia_clock)) + + MCFG_DEVICE_ADD("q133_acia_0", MOS6551, XTAL_1_8432MHz) + MCFG_MOS6551_XTAL(XTAL_1_8432MHz) + MCFG_MOS6551_IRQ_HANDLER(WRITELINE(cmi_state, q133_acia_irq0)) + + MCFG_DEVICE_ADD("q133_acia_1", MOS6551, XTAL_1_8432MHz) + MCFG_MOS6551_XTAL(XTAL_1_8432MHz) + MCFG_MOS6551_IRQ_HANDLER(WRITELINE(cmi_state, q133_acia_irq1)) + + MCFG_DEVICE_ADD("q133_acia_2", MOS6551, XTAL_1_8432MHz) + MCFG_MOS6551_XTAL(XTAL_1_8432MHz) + MCFG_MOS6551_IRQ_HANDLER(WRITELINE(cmi_state, q133_acia_irq2)) + + MCFG_DEVICE_ADD("q133_acia_3", MOS6551, XTAL_1_8432MHz) + MCFG_MOS6551_XTAL(XTAL_1_8432MHz) + MCFG_MOS6551_IRQ_HANDLER(WRITELINE(cmi_state, q133_acia_irq3)) + + MCFG_DEVICE_ADD("acia_mkbd_kbd", ACIA6850, XTAL_1_8432MHz / 12) // acia_mkbd_kbd + MCFG_DEVICE_ADD("acia_mkbd_cmi", ACIA6850, XTAL_1_8432MHz / 12) // acia_mkbd_cmi MCFG_DEVICE_ADD("ank_pia", PIA6821, 0) // pia_ank_config - MCFG_PIA_READPA_HANDLER(READ8(cmi_state, ank_col_r)) - MCFG_PIA_READCB1_HANDLER(READLINE(cmi_state, ank_rts_r)) - MCFG_PIA_CA2_HANDLER(WRITELINE(cmi_state, ank_cts_w)) - MCFG_PIA_CB2_HANDLER(WRITELINE(cmi_state, ank_data_w)) - MCFG_DEVICE_ADD("acia_mkbd_cmi", ACIA6850, 1843200 / 12) // acia_mkbd_cmi - MCFG_DEVICE_ADD("acia_mkbd_kbd", ACIA6850, 1843200 / 12) // acia_mkbd_kbd - - MCFG_DEVICE_MODIFY("acia_mkbd_kbd") - MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("acia_mkbd_cmi", acia6850_device, write_rxd)) - MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("acia_mkbd_cmi", acia6850_device, write_cts)) - MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(cmi_state, mkbd_acia1_int)) + MCFG_DEVICE_MODIFY("q133_acia_0") + MCFG_MOS6551_TXD_HANDLER(DEVWRITELINE("acia_mkbd_cmi", acia6850_device, write_rxd)) + MCFG_MOS6551_RTS_HANDLER(DEVWRITELINE("acia_mkbd_cmi", acia6850_device, write_cts)) MCFG_DEVICE_MODIFY("acia_mkbd_cmi") - MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("acia_mkbd_kbd", acia6850_device, write_rxd)) - MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("acia_mkbd_kbd", acia6850_device, write_cts)) - MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(cmi_state, mkbd_acia2_int)) + MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("q133_acia_0", mos6551_device, write_rxd)) + MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("q133_acia_0", mos6551_device, write_cts)) + MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(cmi_state, mkbd_cmi_acia_int)) + + MCFG_DEVICE_MODIFY("acia_mkbd_kbd") + MCFG_ACIA6850_TXD_HANDLER(DEVWRITELINE("ank_pia", pia6821_device, cb2_w)) + MCFG_ACIA6850_RTS_HANDLER(DEVWRITELINE("ank_pia", pia6821_device, ca2_w)) + MCFG_ACIA6850_IRQ_HANDLER(WRITELINE(cmi_state, mkbd_kbd_acia_int)) + + MCFG_INPUT_MERGER_ACTIVE_HIGH("irqs") + MCFG_INPUT_MERGER_OUTPUT_HANDLER(INPUTLINE("alphakeys", M6802_IRQ_LINE)) + + MCFG_DEVICE_MODIFY("ank_pia") + MCFG_PIA_READPA_HANDLER(READ8(cmi_state, ank_col_r)) + MCFG_PIA_READCB1_HANDLER(READLINE(cmi_state, ank_rts_r)) + MCFG_PIA_CA2_HANDLER(DEVWRITELINE("acia_mkbd_kbd", acia6850_device, write_cts)) + MCFG_PIA_CB2_HANDLER(DEVWRITELINE("acia_mkbd_kbd", acia6850_device, write_rxd)) + MCFG_PIA_IRQA_HANDLER(WRITELINE(cmi_state, ank_irqa_w)) + MCFG_PIA_IRQB_HANDLER(WRITELINE(cmi_state, ank_irqb_w)) + + MCFG_DEVICE_ADD("ank_pia_clock", CLOCK, 9600) + MCFG_CLOCK_SIGNAL_HANDLER(DEVWRITELINE("ank_pia", pia6821_device, ca1_w)) MCFG_DEVICE_ADD("cmi07_ptm", PTM6840, 0) // ptm_cmi07_config MCFG_PTM6840_INTERNAL_CLOCK(2000000) // TODO