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This commit is contained in:
Michaël Banaan Ananas 2013-12-02 18:44:34 +00:00
parent 3f4ba92455
commit b5449a48f1
1 changed files with 35 additions and 34 deletions
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69
src/mame/drivers/omegrace.c
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@ -49,7 +49,7 @@
1 - - 0 0 Vec RAM (4k) 1 - - 0 0 Vec RAM (4k)
1 - - 0 1 1 - - 0 1
1 - - 1 0 Vec ROM (2k) E1 1 - - 1 0 Vec ROM (2k) E1
1 - - 1 1 Vec ROM (2k) F1 1 - - 1 1 Vec ROM (2k) F1
I/O Ports I/O Ports
@ -61,7 +61,7 @@
10 I DIP SW C4 (game ship settings) 10 I DIP SW C4 (game ship settings)
6 5 4 3 2 1 6 5 4 3 2 1
1st bonus ship at 1st bonus ship at
| | | | 0 0 40,000 | | | | 0 0 40,000
| | | | 0 1 50,000 | | | | 0 1 50,000
@ -79,22 +79,22 @@
1 1 1 credit = 3 ships / 2 credits = 7 ships 1 1 1 credit = 3 ships / 2 credits = 7 ships
11 I 7 = Test 11 I 7 = Test
6 = P1 Fire 6 = P1 Fire
5 = P1 Thrust 5 = P1 Thrust
4 = Tilt 4 = Tilt
1 = Coin 2 1 = Coin 2
0 = Coin 1 0 = Coin 1
12 I 7 = 1P1CR 12 I 7 = 1P1CR
6 = 1P2CR 6 = 1P2CR
3 = 2P2CR -+ 3 = 2P2CR -+
2 = 2P1CR | 2 = 2P1CR |
1 = P2Fire | 1 = P2Fire |
0 = P2Thr -+ cocktail only 0 = P2Thr -+ cocktail only
13 O 7 = 13 O 7 =
6 = screen reverse 6 = screen reverse
5 = 2 player 2 credit start LED 5 = 2 player 2 credit start LED
4 = 2 player 1 credit start LED 4 = 2 player 1 credit start LED
@ -107,24 +107,24 @@
15 I encoder 1 (d7-d2) 15 I encoder 1 (d7-d2)
The encoder is a 64 position Grey Code encoder, or a The encoder is a 64 position Grey Code encoder, or a
pot and A to D converter. pot and A to D converter.
Unlike the quadrature inputs on Atari and Sega games, Unlike the quadrature inputs on Atari and Sega games,
Omega Race's controller is an absolute angle. Omega Race's controller is an absolute angle.
0x00, 0x04, 0x14, 0x10, 0x18, 0x1c, 0x5c, 0x58, 0x00, 0x04, 0x14, 0x10, 0x18, 0x1c, 0x5c, 0x58,
0x50, 0x54, 0x44, 0x40, 0x48, 0x4c, 0x6c, 0x68, 0x50, 0x54, 0x44, 0x40, 0x48, 0x4c, 0x6c, 0x68,
0x60, 0x64, 0x74, 0x70, 0x78, 0x7c, 0xfc, 0xf8, 0x60, 0x64, 0x74, 0x70, 0x78, 0x7c, 0xfc, 0xf8,
0xf0, 0xf4, 0xe4, 0xe0, 0xe8, 0xec, 0xcc, 0xc8, 0xf0, 0xf4, 0xe4, 0xe0, 0xe8, 0xec, 0xcc, 0xc8,
0xc0, 0xc4, 0xd4, 0xd0, 0xd8, 0xdc, 0x9c, 0x98, 0xc0, 0xc4, 0xd4, 0xd0, 0xd8, 0xdc, 0x9c, 0x98,
0x90, 0x94, 0x84, 0x80, 0x88, 0x8c, 0xac, 0xa8, 0x90, 0x94, 0x84, 0x80, 0x88, 0x8c, 0xac, 0xa8,
0xa0, 0xa4, 0xb4, 0xb0, 0xb8, 0xbc, 0x3c, 0x38, 0xa0, 0xa4, 0xb4, 0xb0, 0xb8, 0xbc, 0x3c, 0x38,
0x30, 0x34, 0x24, 0x20, 0x28, 0x2c, 0x0c, 0x08 0x30, 0x34, 0x24, 0x20, 0x28, 0x2c, 0x0c, 0x08
16 I encoder 2 (d5-d0) 16 I encoder 2 (d5-d0)
The inputs aren't scrambled as they are on the 1 player The inputs aren't scrambled as they are on the 1 player
encoder encoder
17 I DIP SW C6 (coin/cocktail settings) 17 I DIP SW C6 (coin/cocktail settings)
@ -199,8 +199,8 @@
I/O (write-only) I/O (write-only)
0,1 8912 (K3) 0,1 8912 (K3)
2,3 8912 (J3) 2,3 8912 (J3)
I/O (read-only) I/O (read-only)
@ -232,14 +232,15 @@ public:
m_maincpu(*this, "maincpu"), m_maincpu(*this, "maincpu"),
m_audiocpu(*this, "audiocpu") { } m_audiocpu(*this, "audiocpu") { }
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_audiocpu;
DECLARE_READ8_MEMBER(omegrace_vg_go_r); DECLARE_READ8_MEMBER(omegrace_vg_go_r);
DECLARE_READ8_MEMBER(omegrace_spinner1_r); DECLARE_READ8_MEMBER(omegrace_spinner1_r);
DECLARE_WRITE8_MEMBER(omegrace_leds_w); DECLARE_WRITE8_MEMBER(omegrace_leds_w);
DECLARE_WRITE8_MEMBER(omegrace_soundlatch_w); DECLARE_WRITE8_MEMBER(omegrace_soundlatch_w);
DECLARE_DRIVER_INIT(omegrace); DECLARE_DRIVER_INIT(omegrace);
virtual void machine_reset(); virtual void machine_reset();
required_device<cpu_device> m_maincpu;
required_device<cpu_device> m_audiocpu;
}; };
@ -266,7 +267,7 @@ void omegrace_state::machine_reset()
READ8_MEMBER(omegrace_state::omegrace_vg_go_r) READ8_MEMBER(omegrace_state::omegrace_vg_go_r)
{ {
avgdvg_go_w(space,0,0); avgdvg_go_w(space, 0, 0);
return 0; return 0;
} }
@ -493,7 +494,7 @@ static MACHINE_CONFIG_START( omegrace, omegrace_state )
/* main CPU */ /* main CPU */
/* XTAL101 Crystal @ 12mhz */ /* XTAL101 Crystal @ 12mhz */
/* through 74LS161, Pin 13 = divide by 4 */ /* through 74LS161, Pin 13 = divide by 4 */
MCFG_CPU_ADD("maincpu", Z80,12000000/4) MCFG_CPU_ADD("maincpu", Z80, XTAL_12MHz/4)
MCFG_CPU_PROGRAM_MAP(main_map) MCFG_CPU_PROGRAM_MAP(main_map)
MCFG_CPU_IO_MAP(port_map) MCFG_CPU_IO_MAP(port_map)
MCFG_CPU_PERIODIC_INT_DRIVER(omegrace_state, irq0_line_hold, 250) MCFG_CPU_PERIODIC_INT_DRIVER(omegrace_state, irq0_line_hold, 250)
@ -502,7 +503,7 @@ static MACHINE_CONFIG_START( omegrace, omegrace_state )
/* XTAL101 Crystal @ 12mhz */ /* XTAL101 Crystal @ 12mhz */
/* through 74LS161, Pin 12 = divide by 8 */ /* through 74LS161, Pin 12 = divide by 8 */
/* Fed to CPU as 1.5mhz though line J4-D */ /* Fed to CPU as 1.5mhz though line J4-D */
MCFG_CPU_ADD("audiocpu", Z80,12000000/8) MCFG_CPU_ADD("audiocpu", Z80, XTAL_12MHz/8)
MCFG_CPU_PROGRAM_MAP(sound_map) MCFG_CPU_PROGRAM_MAP(sound_map)
MCFG_CPU_IO_MAP(sound_port) MCFG_CPU_IO_MAP(sound_port)
MCFG_CPU_PERIODIC_INT_DRIVER(omegrace_state, nmi_line_pulse, 250) MCFG_CPU_PERIODIC_INT_DRIVER(omegrace_state, nmi_line_pulse, 250)
@ -524,10 +525,10 @@ static MACHINE_CONFIG_START( omegrace, omegrace_state )
/* XTAL101 Crystal @ 12mhz */ /* XTAL101 Crystal @ 12mhz */
/* through 74LS92, Pin 8 = divide by 12 */ /* through 74LS92, Pin 8 = divide by 12 */
MCFG_SOUND_ADD("ay1", AY8912, 12000000/12) MCFG_SOUND_ADD("ay1", AY8912, XTAL_12MHz/12)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
MCFG_SOUND_ADD("ay2", AY8912, 12000000/12) MCFG_SOUND_ADD("ay2", AY8912, XTAL_12MHz/12)
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25) MCFG_SOUND_ROUTE(ALL_OUTPUTS, "mono", 0.25)
MACHINE_CONFIG_END MACHINE_CONFIG_END