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netlist: dead code removal.

Browse Source 
* moved dead code into examples/lostfound.cpp
* This work didn't improve performance but still may serve as examples
for complex truth table implementations.
This commit is contained in:
couriersud 2020-08-17 00:54:32 +02:00
parent e02478a492
commit b55747b276
12 changed files with 350 additions and 275 deletions
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1
src/lib/netlist/analog/nlid_twoterm.h
View File

@ -336,7 +336,6 @@ namespace analog
NETLIB_RESETI()
{
m_cap.setparams(exec().gmin());
clear_mat();
}
/// \brief Set capacitance

141
src/lib/netlist/devices/net_lib.cpp
View File

@ -3,9 +3,7 @@
// ***************************************************************************
//
// netlib.c
//
// Discrete netlist implementation.
// net_lib.cpp
//
// ***************************************************************************
@ -25,6 +23,138 @@ namespace devices
void initialize_factory(factory::list_t &factory)
{
// The following is from a script which automatically creates
// the entries.
// FIXME: the list should be either include or the whole
// initialize factory code should be created programmatically.
#if 0
LIB_ENTRY(2102A)
LIB_ENTRY(2716)
LIB_ENTRY(4538)
LIB_ENTRY(74107)
LIB_ENTRY(74107A)
LIB_ENTRY(74113)
LIB_ENTRY(74113A)
LIB_ENTRY(74121)
LIB_ENTRY(74123)
LIB_ENTRY(74125)
LIB_ENTRY(74126)
LIB_ENTRY(74153)
LIB_ENTRY(74161)
LIB_ENTRY(74161_fixme)
LIB_ENTRY(74163)
LIB_ENTRY(74164)
LIB_ENTRY(74165)
LIB_ENTRY(74166)
LIB_ENTRY(74174)
LIB_ENTRY(74174_GATE)
LIB_ENTRY(74175)
LIB_ENTRY(74175_dip)
LIB_ENTRY(74192)
LIB_ENTRY(74192_dip)
LIB_ENTRY(74193)
LIB_ENTRY(74193_dip)
LIB_ENTRY(74194)
LIB_ENTRY(74194_dip)
LIB_ENTRY(74365)
LIB_ENTRY(74365_dip)
LIB_ENTRY(74377_GATE)
LIB_ENTRY(74393)
LIB_ENTRY(7448)
LIB_ENTRY(7450)
LIB_ENTRY(7473)
LIB_ENTRY(7473A)
LIB_ENTRY(7474)
LIB_ENTRY(7475_GATE)
LIB_ENTRY(7477_GATE)
LIB_ENTRY(7483)
LIB_ENTRY(7485)
LIB_ENTRY(7490)
LIB_ENTRY(7492)
LIB_ENTRY(7493)
LIB_ENTRY(7497)
LIB_ENTRY(74S287)
LIB_ENTRY(82S115)
LIB_ENTRY(82S123)
LIB_ENTRY(82S126)
LIB_ENTRY(82S16)
LIB_ENTRY(9310)
LIB_ENTRY(9314)
LIB_ENTRY(9314_dip)
LIB_ENTRY(9316)
LIB_ENTRY(9322)
LIB_ENTRY(9322_GATE)
LIB_ENTRY(9334)
LIB_ENTRY(9334_dip)
LIB_ENTRY(9602)
LIB_ENTRY(AM2847)
LIB_ENTRY(AM2847_dip)
LIB_ENTRY(analog_input)
LIB_ENTRY(C)
LIB_ENTRY(CCCS)
LIB_ENTRY(CCVS)
LIB_ENTRY(CD4006)
LIB_ENTRY(CD4013)
LIB_ENTRY(CD4017)
LIB_ENTRY(CD4020)
LIB_ENTRY(CD4020_WI)
LIB_ENTRY(CD4022)
LIB_ENTRY(CD4024)
LIB_ENTRY(CD4053_GATE)
LIB_ENTRY(CD4066_GATE)
LIB_ENTRY(CD4316_GATE)
LIB_ENTRY(clock)
LIB_ENTRY(CS)
LIB_ENTRY(D)
LIB_ENTRY(extclock)
LIB_ENTRY(frontier)
LIB_ENTRY(function)
LIB_ENTRY(gnd)
LIB_ENTRY(L)
LIB_ENTRY(log)
LIB_ENTRY(logD)
LIB_ENTRY(logic_input)
LIB_ENTRY(logic_input8)
LIB_ENTRY(logic_input_ttl)
LIB_ENTRY(LVCCS)
LIB_ENTRY(mainclock)
LIB_ENTRY(MC1455P)
LIB_ENTRY(MC1455P_dip)
LIB_ENTRY(MM5837_dip)
LIB_ENTRY(MOSFET)
LIB_ENTRY(nc_pin)
LIB_ENTRY(NE555)
LIB_ENTRY(NE555_dip)
LIB_ENTRY(netlistparams)
LIB_ENTRY(nicDelay)
LIB_ENTRY(nicRSFF)
LIB_ENTRY(opamp)
LIB_ENTRY(POT)
LIB_ENTRY(POT2)
LIB_ENTRY(QBJT_EB)
LIB_ENTRY(QBJT_switch)
LIB_ENTRY(R)
LIB_ENTRY(r2r_dac)
LIB_ENTRY(schmitt_trigger)
LIB_ENTRY(SN74LS629)
LIB_ENTRY(solver)
LIB_ENTRY(switch1)
LIB_ENTRY(switch2)
LIB_ENTRY(sys_compd)
LIB_ENTRY(sys_dsw1)
LIB_ENTRY(sys_dsw2)
LIB_ENTRY(sys_noise_mt_n)
LIB_ENTRY(sys_noise_mt_u)
LIB_ENTRY(TMS4800)
LIB_ENTRY(TMS4800_dip)
LIB_ENTRY(tristate)
LIB_ENTRY(tristate3)
LIB_ENTRY(varclock)
LIB_ENTRY(VCCS)
LIB_ENTRY(VCVS)
LIB_ENTRY(VS)
LIB_ENTRY(Z)
#else
LIB_ENTRY(R)
LIB_ENTRY(POT)
LIB_ENTRY(POT2)
@ -70,9 +200,7 @@ namespace devices
LIB_ENTRY(nicDelay)
LIB_ENTRY(2102A)
LIB_ENTRY(2716)
#if !(NL_USE_TRUTHTABLE_7448)
LIB_ENTRY(7448)
#endif
LIB_ENTRY(MK28000)
LIB_ENTRY(7450)
LIB_ENTRY(7473)
@ -86,9 +214,7 @@ namespace devices
LIB_ENTRY(7492)
LIB_ENTRY(7493)
LIB_ENTRY(7497)
#if (!NL_USE_TRUTHTABLE_74107)
LIB_ENTRY(74107)
#endif
LIB_ENTRY(74107A)
LIB_ENTRY(74113)
LIB_ENTRY(74113A)
@ -163,6 +289,7 @@ namespace devices
LIB_ENTRY(9334_dip)
LIB_ENTRY(AM2847_dip)
LIB_ENTRY(MM5837_dip)
#endif
}
} //namespace devices

75
src/lib/netlist/devices/nld_4066.cpp
View File

@ -26,19 +26,6 @@
#include "netlist/analog/nlid_twoterm.h"
#include "netlist/solver/nld_solver.h"
// This is an experimental approach to implement the analog switch.
// This will make the switch a 3 terminal element which is completely
// being dealt with as part as the linear system.
//
// The intention was to improve convergence when the switch is in a feedback
// loop. One example are two-opamp tridiagonal wave generators.
// Unfortunately the approach did not work out and in addition was performing
// far worse than the net-separating original code.
//
// FIXME: The transfer function needs review
//
#define USE_DYNAMIC_APPROACH (0)
namespace netlist
{
@ -96,69 +83,7 @@ namespace netlist
};
NETLIB_OBJECT(CD4066_GATE_DYNAMIC)
{
NETLIB_CONSTRUCTOR_MODEL(CD4066_GATE_DYNAMIC, "CD4XXX")
, m_R(*this, "R", NETLIB_DELEGATE(analog_input_changed))
, m_DUM1(*this, "_DUM1", NETLIB_DELEGATE(analog_input_changed))
, m_DUM2(*this, "_DUM2", NETLIB_DELEGATE(analog_input_changed))
, m_base_r(*this, "BASER", nlconst::magic(270.0))
, m_last(*this, "m_last", false)
, m_supply(*this)
{
register_subalias("CTL", m_DUM1.P());
connect(m_DUM1.P(), m_DUM2.P());
connect(m_DUM1.N(), m_R.P());
connect(m_DUM2.N(), m_R.N());
}
NETLIB_RESETI()
{
// Start in off condition
// FIXME: is ROFF correct?
}
NETLIB_UPDATE_TERMINALSI()
{
nl_fptype sup = (m_supply.VCC().Q_Analog() - m_supply.GND().Q_Analog());
nl_fptype in = m_DUM1.P().net().Q_Analog() - m_supply.GND().Q_Analog();
nl_fptype rON = m_base_r() * nlconst::magic(5.0) / sup;
nl_fptype R = std::exp(-(in / sup - nlconst::magic(0.55)) * nlconst::magic(25.0)) + rON;
nl_fptype G = plib::reciprocal(R);
// dI/dVin = (VR1-VR2)*(1.0/sup*b) * exp((Vin/sup-a) * b)
const auto dfdz = nlconst::magic(25.0)/(R*sup) * m_R.deltaV();
const auto Ieq = dfdz * in;
const auto zero(nlconst::zero());
m_R.set_mat( G, -G, zero,
-G, G, zero);
//VIN VR1
m_DUM1.set_mat( zero, zero, zero, // IIN
dfdz, zero, Ieq); // IR1
m_DUM2.set_mat( zero, zero, zero, // IIN
-dfdz, zero, -Ieq); // IR2
}
NETLIB_IS_DYNAMIC(true)
private:
NETLIB_HANDLERI(analog_input_changed)
{
m_R.solve_now();
}
analog::nld_twoterm m_R;
analog::nld_twoterm m_DUM1;
analog::nld_twoterm m_DUM2;
param_fp_t m_base_r;
state_var<bool> m_last;
nld_power_pins m_supply;
};
#if !USE_DYNAMIC_APPROACH
NETLIB_DEVICE_IMPL(CD4066_GATE, "CD4066_GATE", "")
#else
NETLIB_DEVICE_IMPL_ALIAS(CD4066_GATE, CD4066_GATE_DYNAMIC, "CD4066_GATE", "")
#endif
} //namespace devices
} // namespace netlist

2
src/lib/netlist/devices/nld_74107.cpp
View File

@ -157,9 +157,7 @@ namespace netlist
}
};
#if (!NL_USE_TRUTHTABLE_74107)
NETLIB_DEVICE_IMPL(74107, "TTL_74107", "+CLK,+J,+K,+CLRQ,@VCC,@GND")
#endif
NETLIB_DEVICE_IMPL(74107A, "TTL_74107A", "+CLK,+J,+K,+CLRQ,@VCC,@GND")
} //namespace devices

2
src/lib/netlist/devices/nld_74107.h
View File

@ -6,10 +6,8 @@
#include "netlist/nl_setup.h"
#if (!NL_USE_TRUTHTABLE_74107)
#define TTL_74107(...) \
NET_REGISTER_DEVEXT(TTL_74107, __VA_ARGS__)
#endif
// usage: TTL_74107A(name, cCLK, cJ, cK, cCLRQ)
#define TTL_74107A(...) \

4
src/lib/netlist/devices/nld_7448.cpp
View File

@ -30,7 +30,6 @@ namespace netlist
{
namespace devices
{
#if !(NL_USE_TRUTHTABLE_7448)
NETLIB_OBJECT(7448)
{
NETLIB_CONSTRUCTOR(7448)
@ -137,8 +136,5 @@ namespace netlist
NETLIB_DEVICE_IMPL(7448, "TTL_7448", "+A,+B,+C,+D,+LTQ,+BIQ,+RBIQ,@VCC,@GND")
#endif
} //namespace devices
} // namespace netlist

5
src/lib/netlist/devices/nld_7448.h
View File

@ -6,14 +6,9 @@
#include "netlist/nl_setup.h"
#if !NL_AUTO_DEVICES
#if !(NL_USE_TRUTHTABLE_7448)
// usage : TTL_7448(name, pA, pB, pC, pD, pLTQ, pBIQ, pRBIQ)
// auto connect: VCC, GND
#define TTL_7448(...) \
NET_REGISTER_DEVEXT(TTL_7448, __VA_ARGS__)
#endif
#endif
#endif /* NLD_7448_H_ */

215
src/lib/netlist/examples/lostfound.cpp Normal file
View File

@ -0,0 +1,215 @@
///
/// \file lostfound.cpp
///
/// This file contains various code removed from the core which may be
/// useful again in the future or serve educational purposes.
///
/// Don't expect this file to compile
/// \brief Use the truthtable implementation of 74107 instead of the coded device
///
/// FIXME: The truthtable implementation of 74107 (JK-Flipflop)
/// is included for educational purposes to demonstrate how
/// to implement state holding devices as truthtables.
/// It will completely nuke performance for pong.
#ifndef NL_USE_TRUTHTABLE_74107
#define NL_USE_TRUTHTABLE_74107 (0)
#endif
#if (NL_USE_TRUTHTABLE_74107)
/*
* +-----+-----+-----+---++---+-----+
* | CLRQ| CLK | J | K || Q | QQ |
* +=====+=====+=====+===++===+=====+
* | 0 | X | X | X || 0 | 1 |
* | 1 | * | 0 | 0 || Q0| Q0Q |
* | 1 | * | 1 | 0 || 1 | 0 |
* | 1 | * | 0 | 1 || 0 | 1 |
* | 1 | * | 1 | 1 || TOGGLE |
* +-----+-----+-----+---++---+-----+
*/
TRUTHTABLE_START(TTL_74107, 6, 4, "+CLK,+J,+K,+CLRQ,@VCC,@GND")
TT_HEAD("CLRQ, CLK, _CO, J, K,_QX | Q, QQ, CO, QX")
TT_LINE(" 0, 0, X, X, X, X | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 0, 1, X, X, X, X | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, X, 0, 0, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 1, X, 0, 0, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, X, 0, 0, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 1, X, 0, 0, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 0, 1, 1, 0, X | 1, 0, 0, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 0, 0, 1, 0, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, 0, 1, 0, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 1, X, 1, 0, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 1, X, 1, 0, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 0, 1, 0, 1, X | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, 0, 0, 1, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, 0, 0, 1, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 1, X, 0, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 1, X, 0, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
// Toggle
TT_LINE(" 1, 0, 0, 1, 1, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, 0, 1, 1, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 1, 0, 1, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 1, 0, 1, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 1, 1, 1, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 1, 1, 1, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 0, 1, 1, 1, 1 | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, 1, 1, 1, 0 | 1, 0, 0, 1 | 25, 16, 1, 1")
TRUTHTABLE_END()
#endif
/// \brief Use the truthtable implementation of 7448 instead of the coded device
///
/// FIXME: Using truthtable is a lot slower than the explicit device
/// in breakout. Performance drops by 20%. This can be fixed by
/// setting param USE_DEACTIVATE for the device.
#ifndef NL_USE_TRUTHTABLE_7448
#define NL_USE_TRUTHTABLE_7448 (0)
#endif
#if (NL_USE_TRUTHTABLE_7448)
TRUTHTABLE_START(TTL_7448, 7, 7, "+A,+B,+C,+D,+LTQ,+BIQ,+RBIQ,@VCC,@GND")
TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
TT_LINE(" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100")
// BI/RBO is input output. In the next case it is used as an input will go low.
TT_LINE(" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // RBI
TT_LINE(" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100") // LT
// This condition has precedence
TT_LINE(" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // BI
TT_FAMILY("74XX")
TRUTHTABLE_END()
// FIXME: We need a more elegant solution than defining twice
TRUTHTABLE_START(TTL_7448_TT, 7, 7, "")
TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
TT_LINE(" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100")
// BI/RBO is input output. In the next case it is used as an input will go low.
TT_LINE(" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // RBI
TT_LINE(" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100") // LT
// This condition has precedence
TT_LINE(" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // BI
TT_FAMILY("74XX")
TRUTHTABLE_END()
#endif
// This is an experimental approach to implement the analog switch.
// This will make the switch a 3 terminal element which is completely
// being dealt with as part as the linear system.
//
// The intention was to improve convergence when the switch is in a feedback
// loop. One example are two-opamp tridiagonal wave generators.
// Unfortunately the approach did not work out and in addition was performing
// far worse than the net-separating original code.
//
// FIXME: The transfer function needs review
//
NETLIB_OBJECT(CD4066_GATE_DYNAMIC)
{
NETLIB_CONSTRUCTOR_MODEL(CD4066_GATE_DYNAMIC, "CD4XXX")
, m_R(*this, "R", NETLIB_DELEGATE(analog_input_changed))
, m_DUM1(*this, "_DUM1", NETLIB_DELEGATE(analog_input_changed))
, m_DUM2(*this, "_DUM2", NETLIB_DELEGATE(analog_input_changed))
, m_base_r(*this, "BASER", nlconst::magic(270.0))
, m_last(*this, "m_last", false)
, m_supply(*this)
{
register_subalias("CTL", m_DUM1.P());
connect(m_DUM1.P(), m_DUM2.P());
connect(m_DUM1.N(), m_R.P());
connect(m_DUM2.N(), m_R.N());
}
NETLIB_RESETI()
{
// Start in off condition
// FIXME: is ROFF correct?
}
NETLIB_UPDATE_TERMINALSI()
{
nl_fptype sup = (m_supply.VCC().Q_Analog() - m_supply.GND().Q_Analog());
nl_fptype in = m_DUM1.P().net().Q_Analog() - m_supply.GND().Q_Analog();
nl_fptype rON = m_base_r() * nlconst::magic(5.0) / sup;
nl_fptype R = std::exp(-(in / sup - nlconst::magic(0.55)) * nlconst::magic(25.0)) + rON;
nl_fptype G = plib::reciprocal(R);
// dI/dVin = (VR1-VR2)*(1.0/sup*b) * exp((Vin/sup-a) * b)
const auto dfdz = nlconst::magic(25.0)/(R*sup) * m_R.deltaV();
const auto Ieq = dfdz * in;
const auto zero(nlconst::zero());
m_R.set_mat( G, -G, zero,
-G, G, zero);
//VIN VR1
m_DUM1.set_mat( zero, zero, zero, // IIN
dfdz, zero, Ieq); // IR1
m_DUM2.set_mat( zero, zero, zero, // IIN
-dfdz, zero, -Ieq); // IR2
}
NETLIB_IS_DYNAMIC(true)
private:
NETLIB_HANDLERI(analog_input_changed)
{
m_R.solve_now();
}
analog::nld_twoterm m_R;
analog::nld_twoterm m_DUM1;
analog::nld_twoterm m_DUM2;
param_fp_t m_base_r;
state_var<bool> m_last;
nld_power_pins m_supply;
};
NETLIB_DEVICE_IMPL(CD4066_GATE_DYNAMIC, "CD4066_GATE_DYNAMIC", "")

137
src/lib/netlist/macro/nlm_ttl74xx_lib.cpp
View File

@ -3,20 +3,6 @@
#include "netlist/devices/net_lib.h"
#ifndef NL_USE_TRUTHTABLE_74107
#define NL_USE_TRUTHTABLE_74107 0
#endif
#ifndef NL_USE_TRUTHTABLE_7448
#define NL_USE_TRUTHTABLE_7448 0
#endif
#if 1
//
#elif %&/()
//
#endif
//- Identifier: TTL_7400_DIP
//- Title: 5400/DM5400/DM7400 Quad 2-Input NAND Gates
//- Description: This device contains four independent gates each of which performs the logic NAND function.
@ -826,11 +812,7 @@ NETLIST_END()
//-
static NETLIST_START(TTL_7448_DIP)
#if (NL_USE_TRUTHTABLE_7448)
NET_REGISTER_DEV(TTL_7448_TT, A)
#else
NET_REGISTER_DEV(TTL_7448, A)
#endif
TTL_7448(A)
DIPPINS( /* +--------------+ */
A.B, /* B |1 ++ 16| VCC */ A.VCC,
@ -1490,13 +1472,8 @@ NETLIST_END()
//- +------+-------+---+---++---+----+
//-
static NETLIST_START(TTL_74107_DIP)
#if (NL_USE_TRUTHTABLE_74107)
TTL_74107_TT(A)
TTL_74107_TT(B)
#else
TTL_74107(A)
TTL_74107(B)
#endif
NET_C(A.VCC, B.VCC)
NET_C(A.GND, B.GND)
@ -3201,72 +3178,6 @@ NETLIST_START(ttl74xx_lib)
TT_LINE("1,1,X,X|1,1,1,1,1,1,1,1,1,1|30,30,30,30,30,30,30,30,30,30")
TRUTHTABLE_END()
#if (NL_USE_TRUTHTABLE_7448)
TRUTHTABLE_START(TTL_7448, 7, 7, "+A,+B,+C,+D,+LTQ,+BIQ,+RBIQ,@VCC,@GND")
TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
TT_LINE(" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100")
// BI/RBO is input output. In the next case it is used as an input will go low.
TT_LINE(" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // RBI
TT_LINE(" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100") // LT
// This condition has precedence
TT_LINE(" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // BI
TT_FAMILY("74XX")
TRUTHTABLE_END()
// FIXME: We need a more elegant solution than defining twice
TRUTHTABLE_START(TTL_7448_TT, 7, 7, "")
TT_HEAD(" LTQ,BIQ,RBIQ, A , B , C , D | a, b, c, d, e, f, g")
TT_LINE(" 1, 1, 1, 0, 0, 0, 0 | 1, 1, 1, 1, 1, 1, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 0, 0 | 0, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 0, 0 | 1, 1, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 0, 0 | 1, 1, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 1, 0 | 0, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 1, 0 | 1, 0, 1, 1, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 1, 0 | 0, 0, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 1, 0 | 1, 1, 1, 0, 0, 0, 0|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 0, 1 | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 0, 1 | 1, 1, 1, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 0, 1 | 0, 0, 0, 1, 1, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 0, 1 | 0, 0, 1, 1, 0, 0, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 0, 1, 1 | 0, 1, 0, 0, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 0, 1, 1 | 1, 0, 0, 1, 0, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 0, 1, 1, 1 | 0, 0, 0, 1, 1, 1, 1|100,100,100,100,100,100,100")
TT_LINE(" 1, 1, X, 1, 1, 1, 1 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100")
// BI/RBO is input output. In the next case it is used as an input will go low.
TT_LINE(" 1, 1, 0, 0, 0, 0, 0 | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // RBI
TT_LINE(" 0, 1, X, X, X, X, X | 1, 1, 1, 1, 1, 1, 1|100,100,100,100,100,100,100") // LT
// This condition has precedence
TT_LINE(" X, 0, X, X, X, X, X | 0, 0, 0, 0, 0, 0, 0|100,100,100,100,100,100,100") // BI
TT_FAMILY("74XX")
TRUTHTABLE_END()
#endif
TRUTHTABLE_START(TTL_7437_NAND, 2, 1, "+A,+B")
TT_HEAD("A,B|Q ")
TT_LINE("0,X|1|22")
@ -3293,52 +3204,6 @@ NETLIST_START(ttl74xx_lib)
TT_FAMILY("74XX")
TRUTHTABLE_END()
#if (NL_USE_TRUTHTABLE_74107)
/*
* +-----+-----+-----+---++---+-----+
* | CLRQ| CLK | J | K || Q | QQ |
* +=====+=====+=====+===++===+=====+
* | 0 | X | X | X || 0 | 1 |
* | 1 | * | 0 | 0 || Q0| Q0Q |
* | 1 | * | 1 | 0 || 1 | 0 |
* | 1 | * | 0 | 1 || 0 | 1 |
* | 1 | * | 1 | 1 || TOGGLE |
* +-----+-----+-----+---++---+-----+
*/
TRUTHTABLE_START(TTL_74107_TT, 6, 4, "+CLK,+J,+K,+CLRQ,@VCC,@GND")
TT_HEAD("CLRQ, CLK, _CO, J, K,_QX | Q, QQ, CO, QX")
TT_LINE(" 0, 0, X, X, X, X | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 0, 1, X, X, X, X | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, X, 0, 0, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 1, X, 0, 0, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, X, 0, 0, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 1, X, 0, 0, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 0, 1, 1, 0, X | 1, 0, 0, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 0, 0, 1, 0, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, 0, 1, 0, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 1, X, 1, 0, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 1, X, 1, 0, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 0, 1, 0, 1, X | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, 0, 0, 1, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, 0, 0, 1, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 1, X, 0, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 1, X, 0, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
// Toggle
TT_LINE(" 1, 0, 0, 1, 1, 0 | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, 0, 1, 1, 1 | 1, 0, 0, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 1, 0, 1, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 1, 0, 1, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 1, 1, 1, 1, 0 | 0, 1, 1, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 1, 1, 1, 1, 1 | 1, 0, 1, 1 | 25, 16, 1, 1")
TT_LINE(" 1, 0, 1, 1, 1, 1 | 0, 1, 0, 0 | 16, 25, 1, 1")
TT_LINE(" 1, 0, 1, 1, 1, 0 | 1, 0, 0, 1 | 25, 16, 1, 1")
TRUTHTABLE_END()
#endif
TRUTHTABLE_START(TTL_74155A_GATE, 4, 4, "")
TT_HEAD("B,A,G,C|0,1,2,3")

21
src/lib/netlist/macro/nlm_ttl74xx_lib.h
View File

@ -248,21 +248,6 @@
#define TTL_7442_DIP(name) \
NET_REGISTER_DEV(TTL_7442_DIP, name)
#if (NL_USE_TRUTHTABLE_7448)
#define TTL_7448(name, cA0, cA1, cA2, cA3, cLTQ, cBIQ, cRBIQ) \
NET_REGISTER_DEV(TTL_7448, name) \
NET_CONNECT(name, VCC, VCC) \
NET_CONNECT(name, GND, GND) \
NET_CONNECT(name, A, cA0) \
NET_CONNECT(name, B, cA1) \
NET_CONNECT(name, C, cA2) \
NET_CONNECT(name, D, cA3) \
NET_CONNECT(name, LTQ, cLTQ) \
NET_CONNECT(name, BIQ, cBIQ) \
NET_CONNECT(name, RBIQ, cRBIQ)
#endif
#define TTL_7448_DIP(name) \
NET_REGISTER_DEV(TTL_7448_DIP, name)
@ -315,12 +300,6 @@
#define TTL_7497_DIP(name) \
NET_REGISTER_DEV(TTL_7497_DIP, name)
#if (NL_USE_TRUTHTABLE_74107)
// usage: TTL_74107(name, cCLK, cJ, cK, cCLRQ)
#define TTL_74107(...) \
NET_REGISTER_DEVEXT(TTL_74107_TT, __VA_ARGS__)
#endif
#define TTL_74107_DIP(name) \
NET_REGISTER_DEV(TTL_74107_DIP, name)

1
src/lib/netlist/nl_base.cpp
View File

@ -209,7 +209,6 @@ namespace netlist
ENTRY(NL_USE_MEMPOOL)
ENTRY(NL_USE_QUEUE_STATS)
ENTRY(NL_USE_COPY_INSTEAD_OF_REFERENCE)
ENTRY(NL_USE_TRUTHTABLE_7448)
ENTRY(NL_AUTO_DEVICES)
ENTRY(NL_USE_FLOAT128)
ENTRY(NL_USE_FLOAT_MATRIX)

21
src/lib/netlist/nl_config.h
View File

@ -111,27 +111,6 @@
#define NL_USE_BACKWARD_EULER (1)
#endif
/// \brief Use the truthtable implementation of 7448 instead of the coded device
///
/// FIXME: Using truthtable is a lot slower than the explicit device
/// in breakout. Performance drops by 20%. This can be fixed by
/// setting param USE_DEACTIVATE for the device.
#ifndef NL_USE_TRUTHTABLE_7448
#define NL_USE_TRUTHTABLE_7448 (0)
#endif
/// \brief Use the truthtable implementation of 74107 instead of the coded device
///
/// FIXME: The truthtable implementation of 74107 (JK-Flipflop)
/// is included for educational purposes to demonstrate how
/// to implement state holding devices as truthtables.
/// It will completely nuke performance for pong.
#ifndef NL_USE_TRUTHTABLE_74107
#define NL_USE_TRUTHTABLE_74107 (0)
#endif
/// \brief Use the __float128 type for matrix calculations.
///
/// Defaults to \ref PUSE_FLOAT128