mirror of
https://github.com/holub/mame
synced 2025-04-22 16:31:49 +03:00
sh: remove prefixes
This commit is contained in:
Olivier Galibert
parent
7221abfbd4
commit
b5832f7352
@ -11,10 +11,10 @@
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#include "sh7014.h"
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DEFINE_DEVICE_TYPE(SH2_SH7014, sh2_sh7014_device, "sh2_sh7014", "Hitachi SH-2 (SH7014)")
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DEFINE_DEVICE_TYPE(SH7014, sh7014_device, "sh7014", "Hitachi SH-2 (SH7014)")
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sh2_sh7014_device::sh2_sh7014_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: sh2_device(mconfig, SH2_SH7014, tag, owner, clock, CPU_TYPE_SH2, address_map_constructor(FUNC(sh2_sh7014_device::sh7014_map), this), 32, 0xffffffff)
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sh7014_device::sh7014_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: sh2_device(mconfig, SH7014, tag, owner, clock, CPU_TYPE_SH2, address_map_constructor(FUNC(sh7014_device::sh7014_map), this), 32, 0xffffffff)
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, m_sci(*this, "sci%u", 0u)
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, m_bsc(*this, "bsc")
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, m_dmac(*this, "dmac")
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@ -25,14 +25,14 @@ sh2_sh7014_device::sh2_sh7014_device(const machine_config &mconfig, const char *
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{
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}
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void sh2_sh7014_device::device_start()
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void sh7014_device::device_start()
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{
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sh2_device::device_start();
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save_item(NAME(m_ccr));
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}
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void sh2_sh7014_device::device_reset()
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void sh7014_device::device_reset()
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{
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sh2_device::device_reset();
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@ -40,7 +40,7 @@ void sh2_sh7014_device::device_reset()
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m_ccr = 0;
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}
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void sh2_sh7014_device::device_add_mconfig(machine_config &config)
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void sh7014_device::device_add_mconfig(machine_config &config)
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{
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SH7014_SCI(config, m_sci[0], DERIVED_CLOCK(1, 1), m_intc,
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0, // id
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@ -61,17 +61,17 @@ void sh2_sh7014_device::device_add_mconfig(machine_config &config)
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SH7014_BSC(config, m_bsc);
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SH7014_DMAC(config, m_dmac, DERIVED_CLOCK(1, 1), *this, m_intc);
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m_dmac->set_notify_dma_source_callback(FUNC(sh2_sh7014_device::notify_dma_source));
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m_dmac->set_notify_dma_source_callback(FUNC(sh7014_device::notify_dma_source));
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SH7014_INTC(config, m_intc);
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m_intc->set_irq_callback(FUNC(sh2_sh7014_device::set_irq));
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m_intc->set_irq_callback(FUNC(sh7014_device::set_irq));
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SH7014_MTU(config, m_mtu, DERIVED_CLOCK(1, 1), m_intc);
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SH7014_PORT(config, m_port);
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}
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void sh2_sh7014_device::sh7014_map(address_map &map)
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void sh7014_device::sh7014_map(address_map &map)
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{
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// SCI - Serial Communication Interface
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map(0xffff81a0, 0xffff81af).m(m_sci[0], FUNC(sh7014_sci_device::map));
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@ -125,32 +125,32 @@ void sh2_sh7014_device::sh7014_map(address_map &map)
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map(0xffff86b0, 0xffff86df).m(m_dmac, FUNC(sh7014_dmac_device::map));
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// CAC - Cache Memory
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map(0xffff8740, 0xffff8741).rw(FUNC(sh2_sh7014_device::ccr_r), FUNC(sh2_sh7014_device::ccr_w));
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map(0xffff8740, 0xffff8741).rw(FUNC(sh7014_device::ccr_r), FUNC(sh7014_device::ccr_w));
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// Cache space
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map(0xfffff000, 0xffffffff).ram();
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}
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void sh2_sh7014_device::sh2_exception_internal(const char *message, int irqline, int vector)
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void sh7014_device::sh2_exception_internal(const char *message, int irqline, int vector)
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{
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// IRQ was taken so clear it in the interrupt controller and pass it down
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m_intc->set_interrupt(vector, CLEAR_LINE);
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sh2_device::sh2_exception_internal(message, irqline, vector);
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}
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void sh2_sh7014_device::execute_set_input(int irqline, int state)
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void sh7014_device::execute_set_input(int irqline, int state)
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{
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/*
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Flow for SH7014 IRQs:
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sh2_sh7014_device::execute_set_input (for externally triggered IRQs)
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sh7014_device::execute_set_input (for externally triggered IRQs)
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-> sh7014_intc_device::set_input
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-> sh2_sh7014_device::set_irq
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-> sh7014_device::set_irq
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-> sh2_device::execute_set_input (if not internal peripheral IRQ) OR DMA interception OR set sh2_device's internal IRQ flags
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*/
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m_intc->set_input(irqline, state);
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}
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void sh2_sh7014_device::set_irq(int vector, int level, bool is_internal)
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void sh7014_device::set_irq(int vector, int level, bool is_internal)
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{
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if (!is_internal) {
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sh2_device::execute_set_input(vector, ASSERT_LINE);
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@ -169,7 +169,7 @@ void sh2_sh7014_device::set_irq(int vector, int level, bool is_internal)
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m_test_irq = 1;
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}
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void sh2_sh7014_device::notify_dma_source(uint32_t source)
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void sh7014_device::notify_dma_source(uint32_t source)
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{
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if (source == sh7014_dmac_channel_device::RS_SCI_TXI0)
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m_sci[0]->set_dma_source_tx(true);
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@ -184,13 +184,13 @@ void sh2_sh7014_device::notify_dma_source(uint32_t source)
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///////
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// CAC
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uint16_t sh2_sh7014_device::ccr_r()
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uint16_t sh7014_device::ccr_r()
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{
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// bits 15-5 are undefined
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return m_ccr & 0x1f;
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}
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void sh2_sh7014_device::ccr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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void sh7014_device::ccr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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{
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// bit 0 - CECS0 CS0 Space Cache Enable
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// bit 1 - CECS1 CS1 Space Cache Enable
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@ -19,10 +19,10 @@
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#include "sh7014_port.h"
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#include "sh7014_sci.h"
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class sh2_sh7014_device : public sh2_device
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class sh7014_device : public sh2_device
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{
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public:
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sh2_sh7014_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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sh7014_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
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template<int Sci> auto sci_tx_w() {
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return m_sci[Sci].lookup()->write_sci_tx();
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@ -78,6 +78,6 @@ private:
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uint16_t m_ccr;
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};
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DECLARE_DEVICE_TYPE(SH2_SH7014, sh2_sh7014_device)
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DECLARE_DEVICE_TYPE(SH7014, sh7014_device)
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#endif // MAME_CPU_SH_SH7014_H
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@ -4,40 +4,40 @@
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#include "emu.h"
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#include "sh7032.h"
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DEFINE_DEVICE_TYPE(SH1_SH7032, sh1_sh7032_device, "sh1_sh7032", "Hitachi SH-1 (SH7032)")
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DEFINE_DEVICE_TYPE(SH7032, sh7032_device, "sh7032", "Hitachi SH-1 (SH7032)")
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sh1_sh7032_device::sh1_sh7032_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: sh2_device(mconfig, SH1_SH7032, tag, owner, clock, CPU_TYPE_SH1, address_map_constructor(FUNC(sh1_sh7032_device::sh7032_map), this), 28, 0xc7ffffff)
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sh7032_device::sh7032_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: sh2_device(mconfig, SH7032, tag, owner, clock, CPU_TYPE_SH1, address_map_constructor(FUNC(sh7032_device::sh7032_map), this), 28, 0xc7ffffff)
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{
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}
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void sh1_sh7032_device::device_start()
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void sh7032_device::device_start()
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{
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sh2_device::device_start();
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save_item(NAME(m_sh7032_regs));
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}
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void sh1_sh7032_device::device_reset()
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void sh7032_device::device_reset()
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{
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sh2_device::device_reset();
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std::fill(std::begin(m_sh7032_regs), std::end(m_sh7032_regs), 0);
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}
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void sh1_sh7032_device::sh7032_map(address_map &map)
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void sh7032_device::sh7032_map(address_map &map)
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{
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// fall-back
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map(0x05fffe00, 0x05ffffff).rw(FUNC(sh1_sh7032_device::sh7032_r), FUNC(sh1_sh7032_device::sh7032_w)); // SH-7032H internal i/o
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map(0x05fffe00, 0x05ffffff).rw(FUNC(sh7032_device::sh7032_r), FUNC(sh7032_device::sh7032_w)); // SH-7032H internal i/o
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}
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uint16_t sh1_sh7032_device::sh7032_r(offs_t offset)
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uint16_t sh7032_device::sh7032_r(offs_t offset)
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{
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return m_sh7032_regs[offset];
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}
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void sh1_sh7032_device::sh7032_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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void sh7032_device::sh7032_w(offs_t offset, uint16_t data, uint16_t mem_mask)
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{
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COMBINE_DATA(&m_sh7032_regs[offset]);
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}
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@ -1,6 +1,8 @@
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// license:BSD-3-Clause
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// copyright-holders:Angelo Salese
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// SH7032, sh1 variant
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#ifndef MAME_CPU_SH_SH7032_H
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#define MAME_CPU_SH_SH7032_H
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@ -8,10 +10,10 @@
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#include "sh2.h"
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class sh1_sh7032_device : public sh2_device
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class sh7032_device : public sh2_device
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{
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public:
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sh1_sh7032_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock);
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sh7032_device(const machine_config &mconfig, const char *_tag, device_t *_owner, uint32_t _clock);
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protected:
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virtual void device_start() override;
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@ -26,6 +28,6 @@ private:
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uint16_t m_sh7032_regs[0x200];
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};
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DECLARE_DEVICE_TYPE(SH1_SH7032, sh1_sh7032_device)
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DECLARE_DEVICE_TYPE(SH7032, sh7032_device)
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#endif // MAME_CPU_SH_SH7032_H
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@ -28,11 +28,11 @@ static constexpr int div_tab[4] = { 3, 5, 7, 0 };
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static constexpr int wdtclk_tab[8] = { 1, 6, 7, 8, 9, 10, 12, 13 };
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DEFINE_DEVICE_TYPE(SH2_SH7604, sh2_sh7604_device, "sh2_7604", "Hitachi SH-2 (SH7604)")
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DEFINE_DEVICE_TYPE(SH7604, sh7604_device, "sh2_7604", "Hitachi SH-2 (SH7604)")
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sh2_sh7604_device::sh2_sh7604_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: sh2_device(mconfig, SH2_SH7604, tag, owner, clock, CPU_TYPE_SH2, address_map_constructor(FUNC(sh2_sh7604_device::sh7604_map), this), 32, 0xc7ffffff)
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sh7604_device::sh7604_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock)
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: sh2_device(mconfig, SH7604, tag, owner, clock, CPU_TYPE_SH2, address_map_constructor(FUNC(sh7604_device::sh7604_map), this), 32, 0xc7ffffff)
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, m_test_irq(0), m_internal_irq_vector(0)
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, m_smr(0), m_brr(0), m_scr(0), m_tdr(0), m_ssr(0)
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, m_tier(0), m_ftcsr(0), m_frc_tcr(0), m_tocr(0), m_frc(0), m_ocra(0), m_ocrb(0), m_frc_icr(0)
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@ -71,19 +71,19 @@ sh2_sh7604_device::sh2_sh7604_device(const machine_config &mconfig, const char *
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m_dmac[i].drcr = m_dmac[i].sar = m_dmac[i].dar = m_dmac[i].tcr = m_dmac[i].chcr = 0;
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}
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void sh2_sh7604_device::device_start()
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void sh7604_device::device_start()
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{
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sh2_device::device_start();
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m_timer = timer_alloc(FUNC(sh2_sh7604_device::sh2_timer_callback), this);
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m_timer = timer_alloc(FUNC(sh7604_device::sh2_timer_callback), this);
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m_timer->adjust(attotime::never);
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m_wdtimer = timer_alloc(FUNC(sh2_sh7604_device::sh2_wdtimer_callback), this);
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m_wdtimer = timer_alloc(FUNC(sh7604_device::sh2_wdtimer_callback), this);
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m_wdtimer->adjust(attotime::never);
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m_dma_current_active_timer[0] = timer_alloc(FUNC(sh2_sh7604_device::sh2_dma_current_active_callback), this);
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m_dma_current_active_timer[0] = timer_alloc(FUNC(sh7604_device::sh2_dma_current_active_callback), this);
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m_dma_current_active_timer[0]->adjust(attotime::never);
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m_dma_current_active_timer[1] = timer_alloc(FUNC(sh2_sh7604_device::sh2_dma_current_active_callback), this);
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m_dma_current_active_timer[1] = timer_alloc(FUNC(sh7604_device::sh2_dma_current_active_callback), this);
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m_dma_current_active_timer[1]->adjust(attotime::never);
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/* resolve callbacks */
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@ -171,7 +171,7 @@ void sh2_sh7604_device::device_start()
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save_item(NAME(m_rtcnt));
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}
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void sh2_sh7604_device::device_reset()
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void sh7604_device::device_reset()
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{
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sh2_device::device_reset();
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@ -199,97 +199,97 @@ void sh2_sh7604_device::device_reset()
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m_wtcsr = 0;
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}
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void sh2_sh7604_device::sh7604_map(address_map &map)
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void sh7604_device::sh7604_map(address_map &map)
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{
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map(0x40000000, 0xbfffffff).r(FUNC(sh2_sh7604_device::sh2_internal_a5));
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map(0x40000000, 0xbfffffff).r(FUNC(sh7604_device::sh2_internal_a5));
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// TODO: cps3boot breaks with this enabled. Needs callback
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// map(0xc0000000, 0xc0000fff).ram(); // cache data array
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// map(0xe0000000, 0xe00001ff).mirror(0x1ffffe00).rw(FUNC(sh2_sh7604_device::sh7604_r), FUNC(sh2_sh7604_device::sh7604_w));
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// map(0xe0000000, 0xe00001ff).mirror(0x1ffffe00).rw(FUNC(sh7604_device::sh7604_r), FUNC(sh7604_device::sh7604_w));
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// TODO: internal map takes way too much resources if mirrored with 0x1ffffe00
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// we eventually internalize again via trampoline & sh7604_device
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// Also area 0xffff8000-0xffffbfff is for synchronous DRAM mode,
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// so this isn't actually a full mirror
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// SCI
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map(0xfffffe00, 0xfffffe00).rw(FUNC(sh2_sh7604_device::smr_r), FUNC(sh2_sh7604_device::smr_w));
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map(0xfffffe01, 0xfffffe01).rw(FUNC(sh2_sh7604_device::brr_r), FUNC(sh2_sh7604_device::brr_w));
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map(0xfffffe02, 0xfffffe02).rw(FUNC(sh2_sh7604_device::scr_r), FUNC(sh2_sh7604_device::scr_w));
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map(0xfffffe03, 0xfffffe03).rw(FUNC(sh2_sh7604_device::tdr_r), FUNC(sh2_sh7604_device::tdr_w));
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map(0xfffffe04, 0xfffffe04).rw(FUNC(sh2_sh7604_device::ssr_r), FUNC(sh2_sh7604_device::ssr_w));
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map(0xfffffe05, 0xfffffe05).r(FUNC(sh2_sh7604_device::rdr_r));
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map(0xfffffe00, 0xfffffe00).rw(FUNC(sh7604_device::smr_r), FUNC(sh7604_device::smr_w));
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map(0xfffffe01, 0xfffffe01).rw(FUNC(sh7604_device::brr_r), FUNC(sh7604_device::brr_w));
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map(0xfffffe02, 0xfffffe02).rw(FUNC(sh7604_device::scr_r), FUNC(sh7604_device::scr_w));
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map(0xfffffe03, 0xfffffe03).rw(FUNC(sh7604_device::tdr_r), FUNC(sh7604_device::tdr_w));
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map(0xfffffe04, 0xfffffe04).rw(FUNC(sh7604_device::ssr_r), FUNC(sh7604_device::ssr_w));
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map(0xfffffe05, 0xfffffe05).r(FUNC(sh7604_device::rdr_r));
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// FRC
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map(0xfffffe10, 0xfffffe10).rw(FUNC(sh2_sh7604_device::tier_r), FUNC(sh2_sh7604_device::tier_w));
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map(0xfffffe11, 0xfffffe11).rw(FUNC(sh2_sh7604_device::ftcsr_r), FUNC(sh2_sh7604_device::ftcsr_w));
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map(0xfffffe12, 0xfffffe13).rw(FUNC(sh2_sh7604_device::frc_r), FUNC(sh2_sh7604_device::frc_w));
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map(0xfffffe14, 0xfffffe15).rw(FUNC(sh2_sh7604_device::ocra_b_r), FUNC(sh2_sh7604_device::ocra_b_w));
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map(0xfffffe16, 0xfffffe16).rw(FUNC(sh2_sh7604_device::frc_tcr_r), FUNC(sh2_sh7604_device::frc_tcr_w));
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map(0xfffffe17, 0xfffffe17).rw(FUNC(sh2_sh7604_device::tocr_r), FUNC(sh2_sh7604_device::tocr_w));
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map(0xfffffe18, 0xfffffe19).r(FUNC(sh2_sh7604_device::frc_icr_r));
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map(0xfffffe10, 0xfffffe10).rw(FUNC(sh7604_device::tier_r), FUNC(sh7604_device::tier_w));
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map(0xfffffe11, 0xfffffe11).rw(FUNC(sh7604_device::ftcsr_r), FUNC(sh7604_device::ftcsr_w));
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map(0xfffffe12, 0xfffffe13).rw(FUNC(sh7604_device::frc_r), FUNC(sh7604_device::frc_w));
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map(0xfffffe14, 0xfffffe15).rw(FUNC(sh7604_device::ocra_b_r), FUNC(sh7604_device::ocra_b_w));
|
||||
map(0xfffffe16, 0xfffffe16).rw(FUNC(sh7604_device::frc_tcr_r), FUNC(sh7604_device::frc_tcr_w));
|
||||
map(0xfffffe17, 0xfffffe17).rw(FUNC(sh7604_device::tocr_r), FUNC(sh7604_device::tocr_w));
|
||||
map(0xfffffe18, 0xfffffe19).r(FUNC(sh7604_device::frc_icr_r));
|
||||
|
||||
// INTC
|
||||
map(0xfffffe60, 0xfffffe61).rw(FUNC(sh2_sh7604_device::iprb_r), FUNC(sh2_sh7604_device::iprb_w));
|
||||
map(0xfffffe62, 0xfffffe63).rw(FUNC(sh2_sh7604_device::vcra_r), FUNC(sh2_sh7604_device::vcra_w));
|
||||
map(0xfffffe64, 0xfffffe65).rw(FUNC(sh2_sh7604_device::vcrb_r), FUNC(sh2_sh7604_device::vcrb_w));
|
||||
map(0xfffffe66, 0xfffffe67).rw(FUNC(sh2_sh7604_device::vcrc_r), FUNC(sh2_sh7604_device::vcrc_w));
|
||||
map(0xfffffe68, 0xfffffe69).rw(FUNC(sh2_sh7604_device::vcrd_r), FUNC(sh2_sh7604_device::vcrd_w));
|
||||
map(0xfffffe60, 0xfffffe61).rw(FUNC(sh7604_device::iprb_r), FUNC(sh7604_device::iprb_w));
|
||||
map(0xfffffe62, 0xfffffe63).rw(FUNC(sh7604_device::vcra_r), FUNC(sh7604_device::vcra_w));
|
||||
map(0xfffffe64, 0xfffffe65).rw(FUNC(sh7604_device::vcrb_r), FUNC(sh7604_device::vcrb_w));
|
||||
map(0xfffffe66, 0xfffffe67).rw(FUNC(sh7604_device::vcrc_r), FUNC(sh7604_device::vcrc_w));
|
||||
map(0xfffffe68, 0xfffffe69).rw(FUNC(sh7604_device::vcrd_r), FUNC(sh7604_device::vcrd_w));
|
||||
|
||||
map(0xfffffe71, 0xfffffe71).rw(FUNC(sh2_sh7604_device::drcr_r<0>), FUNC(sh2_sh7604_device::drcr_w<0>));
|
||||
map(0xfffffe72, 0xfffffe72).rw(FUNC(sh2_sh7604_device::drcr_r<1>), FUNC(sh2_sh7604_device::drcr_w<1>));
|
||||
map(0xfffffe71, 0xfffffe71).rw(FUNC(sh7604_device::drcr_r<0>), FUNC(sh7604_device::drcr_w<0>));
|
||||
map(0xfffffe72, 0xfffffe72).rw(FUNC(sh7604_device::drcr_r<1>), FUNC(sh7604_device::drcr_w<1>));
|
||||
|
||||
// WTC
|
||||
map(0xfffffe80, 0xfffffe81).rw(FUNC(sh2_sh7604_device::wtcnt_r), FUNC(sh2_sh7604_device::wtcnt_w));
|
||||
map(0xfffffe82, 0xfffffe83).rw(FUNC(sh2_sh7604_device::rstcsr_r), FUNC(sh2_sh7604_device::rstcsr_w));
|
||||
map(0xfffffe80, 0xfffffe81).rw(FUNC(sh7604_device::wtcnt_r), FUNC(sh7604_device::wtcnt_w));
|
||||
map(0xfffffe82, 0xfffffe83).rw(FUNC(sh7604_device::rstcsr_r), FUNC(sh7604_device::rstcsr_w));
|
||||
|
||||
// standby and cache control
|
||||
map(0xfffffe90, 0xfffffe91).rw(FUNC(sh2_sh7604_device::fmr_sbycr_r), FUNC(sh2_sh7604_device::fmr_sbycr_w));
|
||||
map(0xfffffe92, 0xfffffe92).rw(FUNC(sh2_sh7604_device::ccr_r), FUNC(sh2_sh7604_device::ccr_w));
|
||||
map(0xfffffe90, 0xfffffe91).rw(FUNC(sh7604_device::fmr_sbycr_r), FUNC(sh7604_device::fmr_sbycr_w));
|
||||
map(0xfffffe92, 0xfffffe92).rw(FUNC(sh7604_device::ccr_r), FUNC(sh7604_device::ccr_w));
|
||||
|
||||
// INTC second section
|
||||
map(0xfffffee0, 0xfffffee1).rw(FUNC(sh2_sh7604_device::intc_icr_r), FUNC(sh2_sh7604_device::intc_icr_w));
|
||||
map(0xfffffee2, 0xfffffee3).rw(FUNC(sh2_sh7604_device::ipra_r), FUNC(sh2_sh7604_device::ipra_w));
|
||||
map(0xfffffee4, 0xfffffee5).rw(FUNC(sh2_sh7604_device::vcrwdt_r), FUNC(sh2_sh7604_device::vcrwdt_w));
|
||||
map(0xfffffee0, 0xfffffee1).rw(FUNC(sh7604_device::intc_icr_r), FUNC(sh7604_device::intc_icr_w));
|
||||
map(0xfffffee2, 0xfffffee3).rw(FUNC(sh7604_device::ipra_r), FUNC(sh7604_device::ipra_w));
|
||||
map(0xfffffee4, 0xfffffee5).rw(FUNC(sh7604_device::vcrwdt_r), FUNC(sh7604_device::vcrwdt_w));
|
||||
|
||||
// DIVU
|
||||
map(0xffffff00, 0xffffff03).rw(FUNC(sh2_sh7604_device::dvsr_r), FUNC(sh2_sh7604_device::dvsr_w));
|
||||
map(0xffffff04, 0xffffff07).rw(FUNC(sh2_sh7604_device::dvdnt_r), FUNC(sh2_sh7604_device::dvdnt_w));
|
||||
map(0xffffff08, 0xffffff0b).rw(FUNC(sh2_sh7604_device::dvcr_r), FUNC(sh2_sh7604_device::dvcr_w));
|
||||
map(0xffffff00, 0xffffff03).rw(FUNC(sh7604_device::dvsr_r), FUNC(sh7604_device::dvsr_w));
|
||||
map(0xffffff04, 0xffffff07).rw(FUNC(sh7604_device::dvdnt_r), FUNC(sh7604_device::dvdnt_w));
|
||||
map(0xffffff08, 0xffffff0b).rw(FUNC(sh7604_device::dvcr_r), FUNC(sh7604_device::dvcr_w));
|
||||
// INTC third section
|
||||
map(0xffffff0c, 0xffffff0f).rw(FUNC(sh2_sh7604_device::vcrdiv_r), FUNC(sh2_sh7604_device::vcrdiv_w));
|
||||
map(0xffffff0c, 0xffffff0f).rw(FUNC(sh7604_device::vcrdiv_r), FUNC(sh7604_device::vcrdiv_w));
|
||||
// DIVU continued (64-bit plus mirrors)
|
||||
map(0xffffff10, 0xffffff13).rw(FUNC(sh2_sh7604_device::dvdnth_r), FUNC(sh2_sh7604_device::dvdnth_w));
|
||||
map(0xffffff14, 0xffffff17).rw(FUNC(sh2_sh7604_device::dvdntl_r), FUNC(sh2_sh7604_device::dvdntl_w));
|
||||
map(0xffffff18, 0xffffff1b).r(FUNC(sh2_sh7604_device::dvdnth_r));
|
||||
map(0xffffff1c, 0xffffff1f).r(FUNC(sh2_sh7604_device::dvdntl_r));
|
||||
map(0xffffff10, 0xffffff13).rw(FUNC(sh7604_device::dvdnth_r), FUNC(sh7604_device::dvdnth_w));
|
||||
map(0xffffff14, 0xffffff17).rw(FUNC(sh7604_device::dvdntl_r), FUNC(sh7604_device::dvdntl_w));
|
||||
map(0xffffff18, 0xffffff1b).r(FUNC(sh7604_device::dvdnth_r));
|
||||
map(0xffffff1c, 0xffffff1f).r(FUNC(sh7604_device::dvdntl_r));
|
||||
|
||||
// DMAC
|
||||
map(0xffffff80, 0xffffff83).rw(FUNC(sh2_sh7604_device::sar_r<0>), FUNC(sh2_sh7604_device::sar_w<0>));
|
||||
map(0xffffff84, 0xffffff87).rw(FUNC(sh2_sh7604_device::dar_r<0>), FUNC(sh2_sh7604_device::dar_w<0>));
|
||||
map(0xffffff88, 0xffffff8b).rw(FUNC(sh2_sh7604_device::dmac_tcr_r<0>), FUNC(sh2_sh7604_device::dmac_tcr_w<0>));
|
||||
map(0xffffff8c, 0xffffff8f).rw(FUNC(sh2_sh7604_device::chcr_r<0>), FUNC(sh2_sh7604_device::chcr_w<0>));
|
||||
map(0xffffff80, 0xffffff83).rw(FUNC(sh7604_device::sar_r<0>), FUNC(sh7604_device::sar_w<0>));
|
||||
map(0xffffff84, 0xffffff87).rw(FUNC(sh7604_device::dar_r<0>), FUNC(sh7604_device::dar_w<0>));
|
||||
map(0xffffff88, 0xffffff8b).rw(FUNC(sh7604_device::dmac_tcr_r<0>), FUNC(sh7604_device::dmac_tcr_w<0>));
|
||||
map(0xffffff8c, 0xffffff8f).rw(FUNC(sh7604_device::chcr_r<0>), FUNC(sh7604_device::chcr_w<0>));
|
||||
|
||||
map(0xffffff90, 0xffffff93).rw(FUNC(sh2_sh7604_device::sar_r<1>), FUNC(sh2_sh7604_device::sar_w<1>));
|
||||
map(0xffffff94, 0xffffff97).rw(FUNC(sh2_sh7604_device::dar_r<1>), FUNC(sh2_sh7604_device::dar_w<1>));
|
||||
map(0xffffff98, 0xffffff9b).rw(FUNC(sh2_sh7604_device::dmac_tcr_r<1>), FUNC(sh2_sh7604_device::dmac_tcr_w<1>));
|
||||
map(0xffffff9c, 0xffffff9f).rw(FUNC(sh2_sh7604_device::chcr_r<1>), FUNC(sh2_sh7604_device::chcr_w<1>));
|
||||
map(0xffffff90, 0xffffff93).rw(FUNC(sh7604_device::sar_r<1>), FUNC(sh7604_device::sar_w<1>));
|
||||
map(0xffffff94, 0xffffff97).rw(FUNC(sh7604_device::dar_r<1>), FUNC(sh7604_device::dar_w<1>));
|
||||
map(0xffffff98, 0xffffff9b).rw(FUNC(sh7604_device::dmac_tcr_r<1>), FUNC(sh7604_device::dmac_tcr_w<1>));
|
||||
map(0xffffff9c, 0xffffff9f).rw(FUNC(sh7604_device::chcr_r<1>), FUNC(sh7604_device::chcr_w<1>));
|
||||
|
||||
map(0xffffffa0, 0xffffffa3).rw(FUNC(sh2_sh7604_device::vcrdma_r<0>), FUNC(sh2_sh7604_device::vcrdma_w<0>));
|
||||
map(0xffffffa8, 0xffffffab).rw(FUNC(sh2_sh7604_device::vcrdma_r<1>), FUNC(sh2_sh7604_device::vcrdma_w<1>));
|
||||
map(0xffffffb0, 0xffffffb3).rw(FUNC(sh2_sh7604_device::dmaor_r), FUNC(sh2_sh7604_device::dmaor_w));
|
||||
map(0xffffffa0, 0xffffffa3).rw(FUNC(sh7604_device::vcrdma_r<0>), FUNC(sh7604_device::vcrdma_w<0>));
|
||||
map(0xffffffa8, 0xffffffab).rw(FUNC(sh7604_device::vcrdma_r<1>), FUNC(sh7604_device::vcrdma_w<1>));
|
||||
map(0xffffffb0, 0xffffffb3).rw(FUNC(sh7604_device::dmaor_r), FUNC(sh7604_device::dmaor_w));
|
||||
|
||||
// BSC
|
||||
map(0xffffffe0, 0xffffffe3).rw(FUNC(sh2_sh7604_device::bcr1_r), FUNC(sh2_sh7604_device::bcr1_w));
|
||||
map(0xffffffe4, 0xffffffe7).rw(FUNC(sh2_sh7604_device::bcr2_r), FUNC(sh2_sh7604_device::bcr2_w));
|
||||
map(0xffffffe8, 0xffffffeb).rw(FUNC(sh2_sh7604_device::wcr_r), FUNC(sh2_sh7604_device::wcr_w));
|
||||
map(0xffffffec, 0xffffffef).rw(FUNC(sh2_sh7604_device::mcr_r), FUNC(sh2_sh7604_device::mcr_w));
|
||||
map(0xfffffff0, 0xfffffff3).rw(FUNC(sh2_sh7604_device::rtcsr_r), FUNC(sh2_sh7604_device::rtcsr_w));
|
||||
map(0xfffffff4, 0xfffffff7).rw(FUNC(sh2_sh7604_device::rtcnt_r), FUNC(sh2_sh7604_device::rtcnt_w));
|
||||
map(0xfffffff8, 0xfffffffb).rw(FUNC(sh2_sh7604_device::rtcor_r), FUNC(sh2_sh7604_device::rtcor_w));
|
||||
map(0xffffffe0, 0xffffffe3).rw(FUNC(sh7604_device::bcr1_r), FUNC(sh7604_device::bcr1_w));
|
||||
map(0xffffffe4, 0xffffffe7).rw(FUNC(sh7604_device::bcr2_r), FUNC(sh7604_device::bcr2_w));
|
||||
map(0xffffffe8, 0xffffffeb).rw(FUNC(sh7604_device::wcr_r), FUNC(sh7604_device::wcr_w));
|
||||
map(0xffffffec, 0xffffffef).rw(FUNC(sh7604_device::mcr_r), FUNC(sh7604_device::mcr_w));
|
||||
map(0xfffffff0, 0xfffffff3).rw(FUNC(sh7604_device::rtcsr_r), FUNC(sh7604_device::rtcsr_w));
|
||||
map(0xfffffff4, 0xfffffff7).rw(FUNC(sh7604_device::rtcnt_r), FUNC(sh7604_device::rtcnt_w));
|
||||
map(0xfffffff8, 0xfffffffb).rw(FUNC(sh7604_device::rtcor_r), FUNC(sh7604_device::rtcor_w));
|
||||
}
|
||||
|
||||
|
||||
void sh2_sh7604_device::sh2_exception(const char *message, int irqline)
|
||||
void sh7604_device::sh2_exception(const char *message, int irqline)
|
||||
{
|
||||
int vector;
|
||||
|
||||
@ -330,12 +330,12 @@ void sh2_sh7604_device::sh2_exception(const char *message, int irqline)
|
||||
sh2_exception_internal(message, irqline, vector);
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::sh2_internal_a5()
|
||||
uint32_t sh7604_device::sh2_internal_a5()
|
||||
{
|
||||
return 0xa5a5a5a5;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::sh2_timer_resync()
|
||||
void sh7604_device::sh2_timer_resync()
|
||||
{
|
||||
// TODO: setting 3 is "External clock: count on rising edge"
|
||||
int divider = div_tab[m_frc_tcr & 3];
|
||||
@ -351,7 +351,7 @@ void sh2_sh7604_device::sh2_timer_resync()
|
||||
}
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::sh2_timer_activate()
|
||||
void sh7604_device::sh2_timer_activate()
|
||||
{
|
||||
int max_delta = 0xfffff;
|
||||
|
||||
@ -395,7 +395,7 @@ void sh2_sh7604_device::sh2_timer_activate()
|
||||
}
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(sh2_sh7604_device::sh2_timer_callback)
|
||||
TIMER_CALLBACK_MEMBER(sh7604_device::sh2_timer_callback)
|
||||
{
|
||||
sh2_timer_resync();
|
||||
uint16_t frc = m_frc;
|
||||
@ -418,18 +418,18 @@ TIMER_CALLBACK_MEMBER(sh2_sh7604_device::sh2_timer_callback)
|
||||
sh2_timer_activate();
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::sh2_wtcnt_recalc()
|
||||
void sh7604_device::sh2_wtcnt_recalc()
|
||||
{
|
||||
if (m_wdtimer->expire() != attotime::never)
|
||||
m_wtcnt = 0x100 - (attotime_to_cycles(m_wdtimer->remaining()) >> wdtclk_tab[m_wtcsr & 7]);
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::sh2_wdt_activate()
|
||||
void sh7604_device::sh2_wdt_activate()
|
||||
{
|
||||
m_wdtimer->adjust(cycles_to_attotime((0x100 - m_wtcnt) << wdtclk_tab[m_wtcsr & 7]));
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(sh2_sh7604_device::sh2_wdtimer_callback)
|
||||
TIMER_CALLBACK_MEMBER(sh7604_device::sh2_wdtimer_callback)
|
||||
{
|
||||
m_wtcnt = 0;
|
||||
if (!(m_wtcsr & 0x40)) // timer mode
|
||||
@ -469,7 +469,7 @@ TIMER_CALLBACK_MEMBER(sh2_sh7604_device::sh2_wdtimer_callback)
|
||||
|
||||
|
||||
|
||||
void sh2_sh7604_device::sh2_notify_dma_data_available()
|
||||
void sh7604_device::sh2_notify_dma_data_available()
|
||||
{
|
||||
//printf("call notify\n");
|
||||
|
||||
@ -487,7 +487,7 @@ void sh2_sh7604_device::sh2_notify_dma_data_available()
|
||||
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::sh2_do_dma(int dmach)
|
||||
void sh7604_device::sh2_do_dma(int dmach)
|
||||
{
|
||||
if (m_active_dma_count[dmach] > 0)
|
||||
{
|
||||
@ -708,13 +708,13 @@ void sh2_sh7604_device::sh2_do_dma(int dmach)
|
||||
}
|
||||
}
|
||||
|
||||
TIMER_CALLBACK_MEMBER(sh2_sh7604_device::sh2_dma_current_active_callback)
|
||||
TIMER_CALLBACK_MEMBER(sh7604_device::sh2_dma_current_active_callback)
|
||||
{
|
||||
sh2_do_dma(param & 1);
|
||||
}
|
||||
|
||||
|
||||
void sh2_sh7604_device::sh2_dmac_check(int dmach)
|
||||
void sh7604_device::sh2_dmac_check(int dmach)
|
||||
{
|
||||
if (m_dmac[dmach].chcr & m_dmaor & 1)
|
||||
{
|
||||
@ -792,59 +792,59 @@ void sh2_sh7604_device::sh2_dmac_check(int dmach)
|
||||
*/
|
||||
// TODO: identical to H8 counterpart
|
||||
|
||||
uint8_t sh2_sh7604_device::smr_r()
|
||||
uint8_t sh7604_device::smr_r()
|
||||
{
|
||||
return m_smr;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::smr_w(uint8_t data)
|
||||
void sh7604_device::smr_w(uint8_t data)
|
||||
{
|
||||
m_smr = data;
|
||||
}
|
||||
|
||||
uint8_t sh2_sh7604_device::brr_r()
|
||||
uint8_t sh7604_device::brr_r()
|
||||
{
|
||||
return m_brr;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::brr_w(uint8_t data)
|
||||
void sh7604_device::brr_w(uint8_t data)
|
||||
{
|
||||
m_brr = data;
|
||||
}
|
||||
|
||||
uint8_t sh2_sh7604_device::scr_r()
|
||||
uint8_t sh7604_device::scr_r()
|
||||
{
|
||||
return m_scr;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::scr_w(uint8_t data)
|
||||
void sh7604_device::scr_w(uint8_t data)
|
||||
{
|
||||
m_scr = data;
|
||||
}
|
||||
|
||||
uint8_t sh2_sh7604_device::tdr_r()
|
||||
uint8_t sh7604_device::tdr_r()
|
||||
{
|
||||
return m_tdr;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::tdr_w(uint8_t data)
|
||||
void sh7604_device::tdr_w(uint8_t data)
|
||||
{
|
||||
m_tdr = data;
|
||||
//printf("%c", data & 0xff);
|
||||
}
|
||||
|
||||
uint8_t sh2_sh7604_device::ssr_r()
|
||||
uint8_t sh7604_device::ssr_r()
|
||||
{
|
||||
// 0x84 is needed by EGWord on Saturn to make it to boot for some reason.
|
||||
return m_ssr | 0x84;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::ssr_w(uint8_t data)
|
||||
void sh7604_device::ssr_w(uint8_t data)
|
||||
{
|
||||
m_ssr = data;
|
||||
}
|
||||
|
||||
uint8_t sh2_sh7604_device::rdr_r()
|
||||
uint8_t sh7604_device::rdr_r()
|
||||
{
|
||||
return 0;
|
||||
}
|
||||
@ -853,12 +853,12 @@ uint8_t sh2_sh7604_device::rdr_r()
|
||||
* FRC
|
||||
*/
|
||||
|
||||
uint8_t sh2_sh7604_device::tier_r()
|
||||
uint8_t sh7604_device::tier_r()
|
||||
{
|
||||
return m_tier;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::tier_w(uint8_t data)
|
||||
void sh7604_device::tier_w(uint8_t data)
|
||||
{
|
||||
sh2_timer_resync();
|
||||
m_tier = data;
|
||||
@ -866,7 +866,7 @@ void sh2_sh7604_device::tier_w(uint8_t data)
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint8_t sh2_sh7604_device::ftcsr_r()
|
||||
uint8_t sh7604_device::ftcsr_r()
|
||||
{
|
||||
// TODO: to be tested
|
||||
if (!m_ftcsr_read_cb.isnull())
|
||||
@ -875,7 +875,7 @@ uint8_t sh2_sh7604_device::ftcsr_r()
|
||||
return m_ftcsr;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::ftcsr_w(uint8_t data)
|
||||
void sh7604_device::ftcsr_w(uint8_t data)
|
||||
{
|
||||
uint8_t old = m_ftcsr;
|
||||
|
||||
@ -886,13 +886,13 @@ void sh2_sh7604_device::ftcsr_w(uint8_t data)
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::frc_r()
|
||||
uint16_t sh7604_device::frc_r()
|
||||
{
|
||||
sh2_timer_resync();
|
||||
return m_frc;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::frc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::frc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
sh2_timer_resync();
|
||||
COMBINE_DATA(&m_frc);
|
||||
@ -900,12 +900,12 @@ void sh2_sh7604_device::frc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::ocra_b_r()
|
||||
uint16_t sh7604_device::ocra_b_r()
|
||||
{
|
||||
return (m_tocr & 0x10) ? m_ocrb : m_ocra;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::ocra_b_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::ocra_b_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
sh2_timer_resync();
|
||||
if (m_tocr & 0x10)
|
||||
@ -916,12 +916,12 @@ void sh2_sh7604_device::ocra_b_w(offs_t offset, uint16_t data, uint16_t mem_mask
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint8_t sh2_sh7604_device::frc_tcr_r()
|
||||
uint8_t sh7604_device::frc_tcr_r()
|
||||
{
|
||||
return m_frc_tcr & 0x83;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::frc_tcr_w(uint8_t data)
|
||||
void sh7604_device::frc_tcr_w(uint8_t data)
|
||||
{
|
||||
sh2_timer_resync();
|
||||
m_frc_tcr = data & 0x83;
|
||||
@ -929,12 +929,12 @@ void sh2_sh7604_device::frc_tcr_w(uint8_t data)
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint8_t sh2_sh7604_device::tocr_r()
|
||||
uint8_t sh7604_device::tocr_r()
|
||||
{
|
||||
return (m_tocr & 0x13) | 0xe0;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::tocr_w(uint8_t data)
|
||||
void sh7604_device::tocr_w(uint8_t data)
|
||||
{
|
||||
sh2_timer_resync();
|
||||
// TODO: output levels A/B (bits 1-0)
|
||||
@ -943,7 +943,7 @@ void sh2_sh7604_device::tocr_w(uint8_t data)
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::frc_icr_r()
|
||||
uint16_t sh7604_device::frc_icr_r()
|
||||
{
|
||||
return m_frc_icr;
|
||||
}
|
||||
@ -952,26 +952,26 @@ uint16_t sh2_sh7604_device::frc_icr_r()
|
||||
* INTC
|
||||
*/
|
||||
|
||||
uint16_t sh2_sh7604_device::intc_icr_r()
|
||||
uint16_t sh7604_device::intc_icr_r()
|
||||
{
|
||||
// TODO: flip meaning based off NMI edge select bit (NMIE)
|
||||
uint16_t nmilv = m_nmi_line_state == ASSERT_LINE ? 0 : 0x8000;
|
||||
return nmilv | (m_intc_icr & 0x0101);
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::intc_icr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::intc_icr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_intc_icr);
|
||||
m_nmie = BIT(m_intc_icr, 8);
|
||||
m_vecmd = BIT(m_intc_icr, 0);
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::ipra_r()
|
||||
uint16_t sh7604_device::ipra_r()
|
||||
{
|
||||
return m_ipra & 0xfff0;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::ipra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::ipra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_ipra);
|
||||
m_irq_level.divu = (m_ipra >> 12) & 0xf;
|
||||
@ -980,12 +980,12 @@ void sh2_sh7604_device::ipra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::iprb_r()
|
||||
uint16_t sh7604_device::iprb_r()
|
||||
{
|
||||
return m_iprb & 0xff00;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_iprb);
|
||||
m_irq_level.sci = (m_iprb >> 12) & 0xf;
|
||||
@ -993,36 +993,36 @@ void sh2_sh7604_device::iprb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::vcra_r()
|
||||
uint16_t sh7604_device::vcra_r()
|
||||
{
|
||||
return m_vcra & 0x7f7f;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::vcra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::vcra_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_vcra);
|
||||
// ...
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::vcrb_r()
|
||||
uint16_t sh7604_device::vcrb_r()
|
||||
{
|
||||
return m_vcrb;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::vcrb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::vcrb_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_vcrb);
|
||||
// ...
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::vcrc_r()
|
||||
uint16_t sh7604_device::vcrc_r()
|
||||
{
|
||||
return m_vcrc & 0x7f7f;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::vcrc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::vcrc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_vcrc);
|
||||
m_irq_vector.fic = (m_vcrc >> 8) & 0x7f;
|
||||
@ -1030,36 +1030,36 @@ void sh2_sh7604_device::vcrc_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::vcrd_r()
|
||||
uint16_t sh7604_device::vcrd_r()
|
||||
{
|
||||
return m_vcrd & 0x7f00;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::vcrd_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::vcrd_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_vcrd);
|
||||
m_irq_vector.fov = (m_vcrc >> 8) & 0x7f;
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::vcrwdt_r()
|
||||
uint16_t sh7604_device::vcrwdt_r()
|
||||
{
|
||||
return m_vcrwdt & 0x7f7f;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::vcrwdt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::vcrwdt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_vcrwdt);
|
||||
// ...
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::vcrdiv_r()
|
||||
uint32_t sh7604_device::vcrdiv_r()
|
||||
{
|
||||
return m_vcrdiv & 0x7f;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::vcrdiv_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::vcrdiv_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_vcrdiv);
|
||||
// TODO: unemulated, level is seemingly not documented/settable?
|
||||
@ -1071,12 +1071,12 @@ void sh2_sh7604_device::vcrdiv_w(offs_t offset, uint32_t data, uint32_t mem_mask
|
||||
* DIVU
|
||||
*/
|
||||
|
||||
uint32_t sh2_sh7604_device::dvcr_r()
|
||||
uint32_t sh7604_device::dvcr_r()
|
||||
{
|
||||
return (m_divu_ovfie ? 2 : 0) | (m_divu_ovf ? 1 : 0);
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::dvcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::dvcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
@ -1092,22 +1092,22 @@ void sh2_sh7604_device::dvcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::dvsr_r()
|
||||
uint32_t sh7604_device::dvsr_r()
|
||||
{
|
||||
return m_dvsr;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::dvsr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::dvsr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_dvsr);
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::dvdnt_r()
|
||||
uint32_t sh7604_device::dvdnt_r()
|
||||
{
|
||||
return m_dvdntl;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::dvdnt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::dvdnt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_dvdntl);
|
||||
int32_t a = m_dvdntl;
|
||||
@ -1127,22 +1127,22 @@ void sh2_sh7604_device::dvdnt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
}
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::dvdnth_r()
|
||||
uint32_t sh7604_device::dvdnth_r()
|
||||
{
|
||||
return m_dvdnth;
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::dvdntl_r()
|
||||
uint32_t sh7604_device::dvdntl_r()
|
||||
{
|
||||
return m_dvdntl;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::dvdnth_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::dvdnth_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_dvdnth);
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::dvdntl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::dvdntl_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_dvdntl);
|
||||
int64_t a = m_dvdntl | ((uint64_t)m_dvdnth << 32);
|
||||
@ -1177,18 +1177,18 @@ void sh2_sh7604_device::dvdntl_w(offs_t offset, uint32_t data, uint32_t mem_mask
|
||||
* WTC
|
||||
*/
|
||||
|
||||
uint16_t sh2_sh7604_device::wtcnt_r()
|
||||
uint16_t sh7604_device::wtcnt_r()
|
||||
{
|
||||
sh2_wtcnt_recalc();
|
||||
return ((m_wtcsr | 0x18) << 8) | (m_wtcnt & 0xff);
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::rstcsr_r()
|
||||
uint16_t sh7604_device::rstcsr_r()
|
||||
{
|
||||
return (m_rstcsr & 0xe0) | 0x1f;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::wtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::wtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_wtcw[0]);
|
||||
switch (m_wtcw[0] & 0xff00)
|
||||
@ -1222,7 +1222,7 @@ void sh2_sh7604_device::wtcnt_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
}
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::rstcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::rstcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_wtcw[1]);
|
||||
switch (m_wtcw[1] & 0xff00)
|
||||
@ -1238,12 +1238,12 @@ void sh2_sh7604_device::rstcsr_w(offs_t offset, uint16_t data, uint16_t mem_mask
|
||||
}
|
||||
}
|
||||
|
||||
uint16_t sh2_sh7604_device::fmr_sbycr_r()
|
||||
uint16_t sh7604_device::fmr_sbycr_r()
|
||||
{
|
||||
return m_sbycr;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::fmr_sbycr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
void sh7604_device::fmr_sbycr_w(offs_t offset, uint16_t data, uint16_t mem_mask)
|
||||
{
|
||||
switch (mem_mask)
|
||||
{
|
||||
@ -1263,12 +1263,12 @@ void sh2_sh7604_device::fmr_sbycr_w(offs_t offset, uint16_t data, uint16_t mem_m
|
||||
}
|
||||
}
|
||||
|
||||
uint8_t sh2_sh7604_device::ccr_r()
|
||||
uint8_t sh7604_device::ccr_r()
|
||||
{
|
||||
return m_ccr & ~0x30;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::ccr_w(uint8_t data)
|
||||
void sh7604_device::ccr_w(uint8_t data)
|
||||
{
|
||||
/*
|
||||
xx-- ---- Way 0/1
|
||||
@ -1281,79 +1281,79 @@ void sh2_sh7604_device::ccr_w(uint8_t data)
|
||||
m_ccr = data;
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::bcr1_r()
|
||||
uint32_t sh7604_device::bcr1_r()
|
||||
{
|
||||
return (m_bcr1 & ~0xe008) | (m_is_slave ? 0x8000 : 0);
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::bcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::bcr1_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_bcr1);
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::bcr2_r()
|
||||
uint32_t sh7604_device::bcr2_r()
|
||||
{
|
||||
return m_bcr2;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::bcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::bcr2_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_bcr2);
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::wcr_r()
|
||||
uint32_t sh7604_device::wcr_r()
|
||||
{
|
||||
return m_wcr;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::wcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::wcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_wcr);
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::mcr_r()
|
||||
uint32_t sh7604_device::mcr_r()
|
||||
{
|
||||
return m_mcr & ~0x103;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::mcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::mcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_mcr);
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::rtcsr_r()
|
||||
uint32_t sh7604_device::rtcsr_r()
|
||||
{
|
||||
return m_rtcsr & 0xf8;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::rtcsr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::rtcsr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_rtcsr);
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::rtcnt_r()
|
||||
uint32_t sh7604_device::rtcnt_r()
|
||||
{
|
||||
return m_rtcnt & 0xff;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::rtcnt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::rtcnt_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_rtcnt);
|
||||
m_rtcnt &= 0xff;
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::rtcor_r()
|
||||
uint32_t sh7604_device::rtcor_r()
|
||||
{
|
||||
return m_rtcor & 0xff;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::rtcor_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::rtcor_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_rtcor);
|
||||
m_rtcor &= 0xff;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::set_frt_input(int state)
|
||||
void sh7604_device::set_frt_input(int state)
|
||||
{
|
||||
if (m_frt_input == state)
|
||||
return;
|
||||
@ -1378,7 +1378,7 @@ void sh2_sh7604_device::set_frt_input(int state)
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::sh2_recalc_irq()
|
||||
void sh7604_device::sh2_recalc_irq()
|
||||
{
|
||||
int irq = 0;
|
||||
int vector = -1;
|
||||
@ -1444,13 +1444,13 @@ void sh2_sh7604_device::sh2_recalc_irq()
|
||||
*/
|
||||
|
||||
template <int Channel>
|
||||
uint32_t sh2_sh7604_device::vcrdma_r()
|
||||
uint32_t sh7604_device::vcrdma_r()
|
||||
{
|
||||
return m_vcrdma[Channel] & 0x7f;
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
void sh2_sh7604_device::vcrdma_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::vcrdma_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_vcrdma[Channel]);
|
||||
m_irq_vector.dmac[Channel] = m_vcrdma[Channel] & 0x7f;
|
||||
@ -1458,63 +1458,63 @@ void sh2_sh7604_device::vcrdma_w(offs_t offset, uint32_t data, uint32_t mem_mask
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
uint8_t sh2_sh7604_device::drcr_r()
|
||||
uint8_t sh7604_device::drcr_r()
|
||||
{
|
||||
return m_dmac[Channel].drcr & 3;
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
void sh2_sh7604_device::drcr_w(uint8_t data)
|
||||
void sh7604_device::drcr_w(uint8_t data)
|
||||
{
|
||||
m_dmac[Channel].drcr = data & 3;
|
||||
sh2_recalc_irq();
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
uint32_t sh2_sh7604_device::sar_r()
|
||||
uint32_t sh7604_device::sar_r()
|
||||
{
|
||||
return m_dmac[Channel].sar;
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
void sh2_sh7604_device::sar_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::sar_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_dmac[Channel].sar);
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
uint32_t sh2_sh7604_device::dar_r()
|
||||
uint32_t sh7604_device::dar_r()
|
||||
{
|
||||
return m_dmac[Channel].dar;
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
void sh2_sh7604_device::dar_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::dar_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_dmac[Channel].dar);
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
uint32_t sh2_sh7604_device::dmac_tcr_r()
|
||||
uint32_t sh7604_device::dmac_tcr_r()
|
||||
{
|
||||
return m_dmac[Channel].tcr;
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
void sh2_sh7604_device::dmac_tcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::dmac_tcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
COMBINE_DATA(&m_dmac[Channel].tcr);
|
||||
m_dmac[Channel].tcr &= 0xffffff;
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
uint32_t sh2_sh7604_device::chcr_r()
|
||||
uint32_t sh7604_device::chcr_r()
|
||||
{
|
||||
return m_dmac[Channel].chcr;
|
||||
}
|
||||
|
||||
template <int Channel>
|
||||
void sh2_sh7604_device::chcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::chcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
uint32_t old;
|
||||
old = m_dmac[Channel].chcr;
|
||||
@ -1523,12 +1523,12 @@ void sh2_sh7604_device::chcr_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
sh2_dmac_check(Channel);
|
||||
}
|
||||
|
||||
uint32_t sh2_sh7604_device::dmaor_r()
|
||||
uint32_t sh7604_device::dmaor_r()
|
||||
{
|
||||
return m_dmaor & 0xf;
|
||||
}
|
||||
|
||||
void sh2_sh7604_device::dmaor_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
void sh7604_device::dmaor_w(offs_t offset, uint32_t data, uint32_t mem_mask)
|
||||
{
|
||||
if (ACCESSING_BITS_0_7)
|
||||
{
|
||||
|
||||
@ -1,6 +1,8 @@
|
||||
// license:BSD-3-Clause
|
||||
// copyright-holders:Juergen Buchmueller, R. Belmont
|
||||
|
||||
// sh7604, sh2 variant
|
||||
|
||||
#ifndef MAME_CPU_SH_SH7604_H
|
||||
#define MAME_CPU_SH_SH7604_H
|
||||
|
||||
@ -13,14 +15,14 @@
|
||||
#define SH2_FTCSR_READ_CB(name) void name(uint32_t data)
|
||||
|
||||
|
||||
class sh2_sh7604_device : public sh2_device
|
||||
class sh7604_device : public sh2_device
|
||||
{
|
||||
public:
|
||||
typedef device_delegate<int (uint32_t src, uint32_t dst, uint32_t data, int size)> dma_kludge_delegate;
|
||||
typedef device_delegate<int (uint32_t src, uint32_t dst, uint32_t data, int size)> dma_fifo_data_available_delegate;
|
||||
typedef device_delegate<void (uint32_t data)> ftcsr_read_delegate;
|
||||
|
||||
sh2_sh7604_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
sh7604_device(const machine_config &mconfig, const char *tag, device_t *owner, uint32_t clock);
|
||||
|
||||
void set_is_slave(int slave) { m_is_slave = slave; }
|
||||
|
||||
@ -33,7 +35,7 @@ public:
|
||||
void sh2_notify_dma_data_available();
|
||||
|
||||
protected:
|
||||
sh2_sh7604_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int cpu_type, address_map_constructor internal_map, int addrlines);
|
||||
sh7604_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, int cpu_type, address_map_constructor internal_map, int addrlines);
|
||||
|
||||
virtual void device_start() override;
|
||||
virtual void device_reset() override;
|
||||
@ -257,6 +259,6 @@ private:
|
||||
void sh2_recalc_irq();
|
||||
};
|
||||
|
||||
DECLARE_DEVICE_TYPE(SH2_SH7604, sh2_sh7604_device)
|
||||
DECLARE_DEVICE_TYPE(SH7604, sh7604_device)
|
||||
|
||||
#endif // MAME_CPU_SH_SH7604_H
|
||||
|
||||
@ -84,7 +84,7 @@ private:
|
||||
bool m_t1md;
|
||||
bool m_tenb;
|
||||
|
||||
required_device<sh2_sh7604_device> m_hostcpu;
|
||||
required_device<sh7604_device> m_hostcpu;
|
||||
address_space *m_hostspace;
|
||||
void test_pending_irqs();
|
||||
|
||||
|
||||
@ -2489,7 +2489,7 @@ void cps3_state::simm6_128mbit(machine_config &config)
|
||||
void cps3_state::cps3(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
SH2_SH7604(config, m_maincpu, 6250000*4); // external clock is 6.25 Mhz, it sets the internal multiplier to 4x (this should probably be handled in the core..)
|
||||
SH7604(config, m_maincpu, 6250000*4); // external clock is 6.25 Mhz, it sets the internal multiplier to 4x (this should probably be handled in the core..)
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &cps3_state::cps3_map);
|
||||
m_maincpu->set_addrmap(AS_OPCODES, &cps3_state::decrypted_opcodes_map);
|
||||
m_maincpu->set_dma_kludge_callback(FUNC(cps3_state::dma_callback));
|
||||
|
||||
@ -82,7 +82,7 @@ protected:
|
||||
|
||||
void copy_from_nvram();
|
||||
u32 m_current_table_address;
|
||||
required_device<sh2_sh7604_device> m_maincpu;
|
||||
required_device<sh7604_device> m_maincpu;
|
||||
required_device<gfxdecode_device> m_gfxdecode;
|
||||
required_device<palette_device> m_palette;
|
||||
required_device<cps3_sound_device> m_cps3sound;
|
||||
|
||||
@ -539,7 +539,7 @@ void deco_mlc_state::machine_reset()
|
||||
void deco_mlc_state::avengrgs(machine_config &config)
|
||||
{
|
||||
// basic machine hardware
|
||||
SH2_SH7604(config, m_maincpu, 42000000/2); // 21 MHz clock confirmed on real board
|
||||
SH7604(config, m_maincpu, 42000000/2); // 21 MHz clock confirmed on real board
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &deco_mlc_state::avengrgs_map);
|
||||
|
||||
EEPROM_93C46_16BIT(config, m_eeprom); // Actually 93c45
|
||||
@ -1036,16 +1036,16 @@ u32 deco_mlc_state::avengrgs_speedup_r()
|
||||
void deco_mlc_state::init_avengrgs()
|
||||
{
|
||||
// init options
|
||||
dynamic_cast<sh2_sh7604_device *>(m_maincpu.target())->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
|
||||
dynamic_cast<sh7604_device *>(m_maincpu.target())->sh2drc_set_options(SH2DRC_FASTEST_OPTIONS);
|
||||
|
||||
// set up speed cheat
|
||||
dynamic_cast<sh2_sh7604_device *>(m_maincpu.target())->sh2drc_add_pcflush(0x3234);
|
||||
dynamic_cast<sh2_sh7604_device *>(m_maincpu.target())->sh2drc_add_pcflush(0x32dc);
|
||||
dynamic_cast<sh7604_device *>(m_maincpu.target())->sh2drc_add_pcflush(0x3234);
|
||||
dynamic_cast<sh7604_device *>(m_maincpu.target())->sh2drc_add_pcflush(0x32dc);
|
||||
|
||||
dynamic_cast<sh2_sh7604_device *>(m_maincpu.target())->sh2drc_add_fastram(0x0100000, 0x01088ff, 0, &m_mainram[0]);
|
||||
dynamic_cast<sh2_sh7604_device *>(m_maincpu.target())->sh2drc_add_fastram(0x0108a00, 0x011ffff, 0, &m_mainram[0x8a00 / 4]);
|
||||
dynamic_cast<sh2_sh7604_device *>(m_maincpu.target())->sh2drc_add_fastram(0x0200080, 0x02000ff, 0, &m_clip_ram[0]);
|
||||
dynamic_cast<sh2_sh7604_device *>(m_maincpu.target())->sh2drc_add_fastram(0x0280000, 0x029ffff, 0, &m_vram[0]);
|
||||
dynamic_cast<sh7604_device *>(m_maincpu.target())->sh2drc_add_fastram(0x0100000, 0x01088ff, 0, &m_mainram[0]);
|
||||
dynamic_cast<sh7604_device *>(m_maincpu.target())->sh2drc_add_fastram(0x0108a00, 0x011ffff, 0, &m_mainram[0x8a00 / 4]);
|
||||
dynamic_cast<sh7604_device *>(m_maincpu.target())->sh2drc_add_fastram(0x0200080, 0x02000ff, 0, &m_clip_ram[0]);
|
||||
dynamic_cast<sh7604_device *>(m_maincpu.target())->sh2drc_add_fastram(0x0280000, 0x029ffff, 0, &m_vram[0]);
|
||||
|
||||
m_irqLevel = 1;
|
||||
m_maincpu->space(AS_PROGRAM).install_read_handler(0x01089a0, 0x01089a3, read32smo_delegate(*this, FUNC(deco_mlc_state::avengrgs_speedup_r)));
|
||||
|
||||
@ -763,7 +763,7 @@ GFXDECODE_END
|
||||
// XTALs : 28.636MHz, 33.3333MHz, 21.504MHz
|
||||
void skns_state::skns(machine_config &config)
|
||||
{
|
||||
SH2_SH7604(config, m_maincpu, XTAL(28'636'000));
|
||||
SH7604(config, m_maincpu, XTAL(28'636'000));
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &skns_state::skns_map);
|
||||
|
||||
TIMER(config, "scantimer").configure_scanline(FUNC(skns_state::irq), "screen", 0, 1);
|
||||
|
||||
@ -84,7 +84,7 @@ private:
|
||||
uint8_t disconnect = 0;
|
||||
};
|
||||
|
||||
required_device<sh2_sh7604_device> m_maincpu;
|
||||
required_device<sh7604_device> m_maincpu;
|
||||
required_device<sknsspr_device> m_spritegen;
|
||||
required_device<gfxdecode_device> m_gfxdecode;
|
||||
required_device<palette_device> m_palette;
|
||||
|
||||
@ -108,7 +108,7 @@ void hideseek_state::hideseek_palette(palette_device &palette) const
|
||||
void hideseek_state::hideseek(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
SH2_SH7604(config, m_maincpu, 7372800 * 4);
|
||||
SH7604(config, m_maincpu, 7372800 * 4);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &hideseek_state::mem_map);
|
||||
// TIMER(config, "scantimer").configure_scanline(FUNC(hideseek_state::hideseek_scanline), "screen", 0, 1);
|
||||
|
||||
|
||||
@ -85,7 +85,7 @@ void namcos12_cdxa_device::device_reset()
|
||||
|
||||
void namcos12_cdxa_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
SH2_SH7014(config, m_maincpu, XTAL(14'745'600));
|
||||
SH7014(config, m_maincpu, XTAL(14'745'600));
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &namcos12_cdxa_device::sh7014_map);
|
||||
|
||||
ATA_INTERFACE(config, m_ata).options([] (device_slot_interface &device) { device.option_add("cdrom", TOSHIBA_XM6402B_CDROM); }, "cdrom", nullptr, true);
|
||||
|
||||
@ -69,7 +69,7 @@ private:
|
||||
|
||||
void mb87078_gain_changed(offs_t offset, uint8_t data);
|
||||
|
||||
required_device<sh2_sh7014_device> m_maincpu;
|
||||
required_device<sh7014_device> m_maincpu;
|
||||
required_shared_ptr<uint32_t> m_cram;
|
||||
required_shared_ptr<uint32_t> m_sram;
|
||||
required_device<ata_interface_device> m_ata;
|
||||
|
||||
@ -1764,7 +1764,7 @@ private:
|
||||
required_shared_ptr<uint32_t> m_charram;
|
||||
required_shared_ptr<uint32_t> m_textram;
|
||||
optional_shared_ptr<uint32_t> m_czattr;
|
||||
optional_device<sh2_sh7604_device> m_gmen_sh2;
|
||||
optional_device<sh7604_device> m_gmen_sh2;
|
||||
optional_shared_ptr<uint32_t> m_gmen_sh2_shared;
|
||||
required_device<gfxdecode_device> m_gfxdecode;
|
||||
optional_ioport m_lightx;
|
||||
@ -3981,7 +3981,7 @@ void namcos23_state::gmen(machine_config &config)
|
||||
/* basic machine hardware */
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &namcos23_state::gmen_mips_map);
|
||||
|
||||
SH2_SH7604(config, m_gmen_sh2, XTAL(28'700'000));
|
||||
SH7604(config, m_gmen_sh2, XTAL(28'700'000));
|
||||
m_gmen_sh2->set_addrmap(AS_PROGRAM, &namcos23_state::gmen_sh2_map);
|
||||
|
||||
MCFG_MACHINE_RESET_OVERRIDE(namcos23_state,gmen)
|
||||
|
||||
@ -605,7 +605,7 @@ void psikyo4_state::machine_reset()
|
||||
void psikyo4_state::ps4big(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
SH2_SH7604(config, m_maincpu, 57272700/2);
|
||||
SH7604(config, m_maincpu, 57272700/2);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &psikyo4_state::ps4_map);
|
||||
m_maincpu->set_vblank_int("lscreen", FUNC(psikyo4_state::interrupt));
|
||||
|
||||
|
||||
@ -57,7 +57,7 @@ private:
|
||||
double m_oldbrt[2]{};
|
||||
|
||||
/* devices */
|
||||
required_device<sh2_sh7604_device> m_maincpu;
|
||||
required_device<sh7604_device> m_maincpu;
|
||||
required_device<eeprom_serial_93cxx_device> m_eeprom;
|
||||
required_device<gfxdecode_device> m_gfxdecode;
|
||||
required_device_array<palette_device, 2> m_palette;
|
||||
|
||||
@ -837,7 +837,7 @@ void psikyosh_state::machine_start()
|
||||
void psikyosh_state::psikyo3v1(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
SH2_SH7604(config, m_maincpu, MASTER_CLOCK/2);
|
||||
SH7604(config, m_maincpu, MASTER_CLOCK/2);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &psikyosh_state::ps3v1_map);
|
||||
m_maincpu->set_vblank_int("screen", FUNC(psikyosh_state::interrupt));
|
||||
|
||||
|
||||
@ -88,7 +88,7 @@ private:
|
||||
const struct sprite_t *m_sprite_end;
|
||||
|
||||
/* devices */
|
||||
required_device<sh2_sh7604_device> m_maincpu;
|
||||
required_device<sh7604_device> m_maincpu;
|
||||
required_device<eeprom_serial_93cxx_device> m_eeprom;
|
||||
required_device<gfxdecode_device> m_gfxdecode;
|
||||
required_device<screen_device> m_screen;
|
||||
|
||||
@ -351,8 +351,8 @@ public:
|
||||
uint32_t m_clipvals[2][3];
|
||||
uint8_t m_clipblitterMode[2]; // hack
|
||||
|
||||
required_device<sh2_sh7604_device> m_maincpu;
|
||||
required_device<sh1_sh7032_device> m_subcpu;
|
||||
required_device<sh7604_device> m_maincpu;
|
||||
required_device<sh7032_device> m_subcpu;
|
||||
required_device<cpu_device> m_soundcpu;
|
||||
//required_device<am9517a_device> m_dmac;
|
||||
|
||||
@ -3228,14 +3228,14 @@ void coolridr_state::scsp2_to_sh1_irq(int state)
|
||||
|
||||
void coolridr_state::coolridr(machine_config &config)
|
||||
{
|
||||
SH2_SH7604(config, m_maincpu, XTAL(28'000'000)); // 28 MHz
|
||||
SH7604(config, m_maincpu, XTAL(28'000'000)); // 28 MHz
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &coolridr_state::coolridr_h1_map);
|
||||
TIMER(config, "scantimer").configure_scanline(FUNC(coolridr_state::interrupt_main), "screen", 0, 1);
|
||||
|
||||
M68000(config, m_soundcpu, XTAL(32'000'000)/2); // 16 MHz
|
||||
m_soundcpu->set_addrmap(AS_PROGRAM, &coolridr_state::system_h1_sound_map);
|
||||
|
||||
SH1_SH7032(config, m_subcpu, XTAL(32'000'000)/2); // SH7032 HD6417032F20!! 16 MHz
|
||||
SH7032(config, m_subcpu, XTAL(32'000'000)/2); // SH7032 HD6417032F20!! 16 MHz
|
||||
m_subcpu->set_addrmap(AS_PROGRAM, &coolridr_state::coolridr_submap);
|
||||
TIMER(config, "scantimer2").configure_scanline(FUNC(coolridr_state::interrupt_sub), "screen", 0, 1);
|
||||
|
||||
|
||||
@ -811,12 +811,12 @@ uint8_t sat_console_state::smpc_direct_mode(uint16_t in_value,bool which)
|
||||
void sat_console_state::saturn(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
SH2_SH7604(config, m_maincpu, MASTER_CLOCK_352/2); // 28.6364 MHz
|
||||
SH7604(config, m_maincpu, MASTER_CLOCK_352/2); // 28.6364 MHz
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &sat_console_state::saturn_mem);
|
||||
m_maincpu->set_is_slave(0);
|
||||
TIMER(config, "scantimer").configure_scanline(FUNC(sat_console_state::saturn_scanline), "screen", 0, 1);
|
||||
|
||||
SH2_SH7604(config, m_slave, MASTER_CLOCK_352/2); // 28.6364 MHz
|
||||
SH7604(config, m_slave, MASTER_CLOCK_352/2); // 28.6364 MHz
|
||||
m_slave->set_addrmap(AS_PROGRAM, &sat_console_state::saturn_mem);
|
||||
m_slave->set_is_slave(1);
|
||||
TIMER(config, "slave_scantimer").configure_scanline(FUNC(sat_console_state::saturn_slave_scanline), "screen", 0, 1);
|
||||
|
||||
@ -119,8 +119,8 @@ protected:
|
||||
int old_tvmd = 0;
|
||||
}m_vdp2;
|
||||
|
||||
required_device<sh2_sh7604_device> m_maincpu;
|
||||
required_device<sh2_sh7604_device> m_slave;
|
||||
required_device<sh7604_device> m_maincpu;
|
||||
required_device<sh7604_device> m_slave;
|
||||
required_device<m68000_base_device> m_audiocpu;
|
||||
required_device<scsp_device> m_scsp;
|
||||
required_device<smpc_hle_device> m_smpc_hle;
|
||||
|
||||
@ -30,7 +30,7 @@ void saturn_cdb_device::saturn_cdb_map(address_map &map)
|
||||
|
||||
void saturn_cdb_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
sh1_sh7032_device &cdbcpu(SH1_SH7032(config, "cdbcpu", DERIVED_CLOCK(1, 1)));
|
||||
sh7032_device &cdbcpu(SH7032(config, "cdbcpu", DERIVED_CLOCK(1, 1)));
|
||||
cdbcpu.set_addrmap(AS_PROGRAM, &saturn_cdb_device::saturn_cdb_map);
|
||||
cdbcpu.set_disable(); // we're not actually using the CD Block ROM for now
|
||||
}
|
||||
|
||||
@ -1113,12 +1113,12 @@ void stv_state::pdr2_output_w(uint8_t data)
|
||||
void stv_state::stv(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
SH2_SH7604(config, m_maincpu, MASTER_CLOCK_352/2); // 28.6364 MHz
|
||||
SH7604(config, m_maincpu, MASTER_CLOCK_352/2); // 28.6364 MHz
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &stv_state::stv_mem);
|
||||
m_maincpu->set_is_slave(0);
|
||||
TIMER(config, "scantimer").configure_scanline(FUNC(stv_state::saturn_scanline), "screen", 0, 1);
|
||||
|
||||
SH2_SH7604(config, m_slave, MASTER_CLOCK_352/2); // 28.6364 MHz
|
||||
SH7604(config, m_slave, MASTER_CLOCK_352/2); // 28.6364 MHz
|
||||
m_slave->set_addrmap(AS_PROGRAM, &stv_state::stv_mem);
|
||||
m_slave->set_is_slave(1);
|
||||
TIMER(config, "slave_scantimer").configure_scanline(FUNC(stv_state::saturn_slave_scanline), "screen", 0, 1);
|
||||
|
||||
@ -126,7 +126,7 @@ private:
|
||||
required_ioport_array<2> m_in;
|
||||
output_finder<7> m_lamps;
|
||||
|
||||
required_device<sh2_sh7604_device> m_maincpu;
|
||||
required_device<sh7604_device> m_maincpu;
|
||||
required_device<okim6295_device> m_oki;
|
||||
required_device<eeprom_serial_93cxx_device> m_eeprom;
|
||||
required_device<jrc6355e_device> m_rtc;
|
||||
@ -297,7 +297,7 @@ void feversoc_state::machine_start()
|
||||
void feversoc_state::feversoc(machine_config &config)
|
||||
{
|
||||
/* basic machine hardware */
|
||||
SH2_SH7604(config, m_maincpu, MASTER_CLOCK);
|
||||
SH7604(config, m_maincpu, MASTER_CLOCK);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &feversoc_state::feversoc_map);
|
||||
|
||||
/* video hardware */
|
||||
|
||||
@ -1681,17 +1681,17 @@ const rom_entry *sega_32x_device::device_rom_region() const
|
||||
void sega_32x_device::device_add_mconfig(machine_config &config)
|
||||
{
|
||||
#ifndef _32X_SWAP_MASTER_SLAVE_HACK
|
||||
SH2_SH7604(config, m_master_cpu, DERIVED_CLOCK(1, 1));
|
||||
SH7604(config, m_master_cpu, DERIVED_CLOCK(1, 1));
|
||||
m_master_cpu->set_is_slave(0);
|
||||
m_master_cpu->set_dma_fifo_data_available_callback(FUNC(sega_32x_device::_32x_fifo_available_callback));
|
||||
#endif
|
||||
|
||||
SH2_SH7604(config, m_slave_cpu, DERIVED_CLOCK(1, 1));
|
||||
SH7604(config, m_slave_cpu, DERIVED_CLOCK(1, 1));
|
||||
m_slave_cpu->set_is_slave(1);
|
||||
m_slave_cpu->set_dma_fifo_data_available_callback(FUNC(sega_32x_device::_32x_fifo_available_callback));
|
||||
|
||||
#ifdef _32X_SWAP_MASTER_SLAVE_HACK
|
||||
SH2_SH7604(config, m_master_cpu, DERIVED_CLOCK(1, 1));
|
||||
SH7604(config, m_master_cpu, DERIVED_CLOCK(1, 1));
|
||||
m_master_cpu->set_is_slave(0);
|
||||
m_master_cpu->set_dma_fifo_data_available_callback(FUNC(sega_32x_device::_32x_fifo_available_callback));
|
||||
#endif
|
||||
|
||||
@ -115,8 +115,8 @@ protected:
|
||||
|
||||
/* our main vblank handler resets this */
|
||||
required_device<m68000_base_device> m_main_cpu;
|
||||
required_device<sh2_sh7604_device> m_master_cpu;
|
||||
required_device<sh2_sh7604_device> m_slave_cpu;
|
||||
required_device<sh7604_device> m_master_cpu;
|
||||
required_device<sh7604_device> m_slave_cpu;
|
||||
required_device<dac_word_interface> m_ldac;
|
||||
required_device<dac_word_interface> m_rdac;
|
||||
required_device<timer_device> m_scan_timer;
|
||||
|
||||
@ -33,7 +33,7 @@ void psr540_state::machine_start()
|
||||
|
||||
void psr540_state::psr540(machine_config &config)
|
||||
{
|
||||
SH2_SH7014(config, m_maincpu, 7_MHz_XTAL);
|
||||
SH7014(config, m_maincpu, 7_MHz_XTAL);
|
||||
m_maincpu->set_addrmap(AS_PROGRAM, &psr540_state::map);
|
||||
|
||||
SPEAKER(config, "lspeaker").front_left();
|
||||
|
||||
Loading…
Reference in New Issue
Block a user