From 430324dbedb34c7c30d4d7177f98bfbe795a1f35 Mon Sep 17 00:00:00 2001 From: hap Date: Fri, 10 Dec 2021 15:49:33 +0100 Subject: [PATCH] sdtor: fix small contrast problem in internal artwork --- src/mame/drivers/im01.cpp | 6 ++++-- src/mame/drivers/mattelchess.cpp | 19 +++++++++---------- src/mame/layout/cxg_dominator.lay | 14 ++++++-------- src/mame/layout/fidel_cc10.lay | 2 +- 4 files changed, 20 insertions(+), 21 deletions(-) diff --git a/src/mame/drivers/im01.cpp b/src/mame/drivers/im01.cpp index 82c00e23461..9cdf6b9f157 100644 --- a/src/mame/drivers/im01.cpp +++ b/src/mame/drivers/im01.cpp @@ -17,9 +17,11 @@ TODO: around 1.1 times faster, maybe К1801ВМ1 internal timing differs from T11, and/or T11 core timing itself is not 100% accurate. - verify actual XTAL, the label couldn't be seen -- Is ИМ-01Т extra RAM chip used at all, and if so, where is it mapped? +- Is im01t extra RAM chip used at all, and if so, where is it mapped? Even when trying to solve mate problems (level 7, and overclocked CPU), there are no unmapped writes. +- What is 0x6000-0x7fff for? im01 will test for both RAM and ROM in this + area if no bus error was triggered, and will fail to boot up. ******************************************************************************* @@ -193,7 +195,7 @@ u16 im01_state::input_r(offs_t offset, u16 mem_mask) void im01_state::error_w(offs_t offset, u16 data, u16 mem_mask) { - // unmapped port, expects a bus error + // unmapped port, it expects a bus error m_maincpu->pulse_input_line(t11_device::BUS_ERROR, attotime::zero); } diff --git a/src/mame/drivers/mattelchess.cpp b/src/mame/drivers/mattelchess.cpp index 849214f32e8..db338168144 100644 --- a/src/mame/drivers/mattelchess.cpp +++ b/src/mame/drivers/mattelchess.cpp @@ -10,6 +10,9 @@ Hardware notes: - 2*HLCD0569(also seen with 2*HLCD0601, functionally same?) - custom LCD screen with chess squares background +It was also released in the USSR as Электроника ИМ-29 Шахматный партнёр, +assumed to be an unlicensed clone. + ******************************************************************************/ #include "emu.h" @@ -49,9 +52,6 @@ private: required_ioport_array<4> m_inputs; output_finder<2, 8, 22> m_out_x; - u8 m_inp_mux; - u8 m_lcd_control; - void update_reset(ioport_value state); // I/O handlers @@ -60,6 +60,9 @@ private: u8 input_r(); void lcd_w(u8 data); u8 lcd_r(); + + u8 m_inp_mux = 0; + u8 m_lcd_control = 0; }; void mchess_state::machine_start() @@ -67,10 +70,6 @@ void mchess_state::machine_start() // resolve handlers m_out_x.resolve(); - // zerofill - m_inp_mux = 0; - m_lcd_control = 0; - // register for savestates save_item(NAME(m_inp_mux)); save_item(NAME(m_lcd_control)); @@ -150,7 +149,7 @@ u8 mchess_state::lcd_r() // d7: 2nd LCDC DATA OUT u8 r0 = m_lcd[0]->data_r(); u8 r1 = m_lcd[1]->data_r(); - return (0x84^0xff) | r0 << 2 | r1 << 7; + return ~0x84 | r0 << 2 | r1 << 7; } @@ -193,14 +192,14 @@ INPUT_PORTS_END void mchess_state::mchess(machine_config &config) { - /* basic machine hardware */ + // basic machine hardware I8050(config, m_maincpu, 6_MHz_XTAL); m_maincpu->p1_out_cb().set(FUNC(mchess_state::input_w)); m_maincpu->p1_in_cb().set(FUNC(mchess_state::input_r)); m_maincpu->p2_out_cb().set(FUNC(mchess_state::lcd_w)); m_maincpu->p2_in_cb().set(FUNC(mchess_state::lcd_r)); - /* video hardware */ + // video hardware HLCD0569(config, m_lcd[0], 500); // C=0.01uF m_lcd[0]->write_cols().set(FUNC(mchess_state::lcd_output_w<0>)); HLCD0569(config, m_lcd[1], 500); // C=0.01uF diff --git a/src/mame/layout/cxg_dominator.lay b/src/mame/layout/cxg_dominator.lay index ecf8ff61970..00e4b123a93 100644 --- a/src/mame/layout/cxg_dominator.lay +++ b/src/mame/layout/cxg_dominator.lay @@ -512,13 +512,12 @@ license:CC0 - - + + - - + @@ -590,11 +589,12 @@ license:CC0 - - + + + @@ -649,8 +649,6 @@ license:CC0 - - diff --git a/src/mame/layout/fidel_cc10.lay b/src/mame/layout/fidel_cc10.lay index 15b4e8655b8..9d21449ff67 100644 --- a/src/mame/layout/fidel_cc10.lay +++ b/src/mame/layout/fidel_cc10.lay @@ -41,7 +41,7 @@ license:CC0 - +