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sparc: Disassembler fixes

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- Compare architecture versions against correct enum values
- FLUSH exists (at least nominally) on v7 under the name IFLUSH
This commit is contained in:
AJR 2022-06-29 21:21:07 -04:00
parent b3ce12d0c0
commit b5d8cdc065
1 changed files with 27 additions and 31 deletions
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54
src/devices/cpu/sparc/sparcdasm.cpp
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@ -577,7 +577,7 @@ const sparc_disassembler::vis_op_desc_map::value_type sparc_disassembler::VIS3B_
inline uint32_t sparc_disassembler::freg(uint32_t val, bool shift) const inline uint32_t sparc_disassembler::freg(uint32_t val, bool shift) const
{ {
return (shift && (m_version >= 9)) ? ((val & 0x1e) | ((val << 5) & 0x20)) : val; return (shift && (m_version >= v9)) ? ((val & 0x1e) | ((val << 5) & 0x20)) : val;
} }
template <typename T> inline void sparc_disassembler::add_int_op_desc(const T &desc) template <typename T> inline void sparc_disassembler::add_int_op_desc(const T &desc)
@ -756,7 +756,7 @@ offs_t sparc_disassembler::dasm(std::ostream &stream, offs_t pc, uint32_t op) co
switch (OP2) switch (OP2)
{ {
case 0: case 0:
util::stream_format(stream, "%-*s0x%06x", m_op_field_width, (m_version >= 9) ? "illtrap" : "unimp", CONST22); util::stream_format(stream, "%-*s0x%06x", m_op_field_width, (m_version >= v9) ? "illtrap" : "unimp", CONST22);
break; break;
case 4: case 4:
if (IMM22 == 0 && RD == 0) if (IMM22 == 0 && RD == 0)
@ -873,14 +873,14 @@ offs_t sparc_disassembler::dasm(std::ostream &stream, offs_t pc, uint32_t op) co
case 0x28: case 0x28:
return dasm_read_state_reg(stream, pc, op); return dasm_read_state_reg(stream, pc, op);
case 0x29: case 0x29:
if (m_version <= 8) if (m_version <= v8)
{ {
util::stream_format(stream, "%-*s%%psr,%s", m_op_field_width, "rd", REG_NAMES[RD]); util::stream_format(stream, "%-*s%%psr,%s", m_op_field_width, "rd", REG_NAMES[RD]);
return 4 | SUPPORTED; return 4 | SUPPORTED;
} }
break; break;
case 0x2a: case 0x2a:
if (m_version >= 9) if (m_version >= v9)
{ {
if (V9_PRIV_REG_NAMES[RS1]) if (V9_PRIV_REG_NAMES[RS1])
{ {
@ -895,7 +895,7 @@ offs_t sparc_disassembler::dasm(std::ostream &stream, offs_t pc, uint32_t op) co
} }
break; break;
case 0x2b: case 0x2b:
if (m_version >= 9) if (m_version >= v9)
{ {
if (!USEIMM) if (!USEIMM)
{ {
@ -912,7 +912,7 @@ offs_t sparc_disassembler::dasm(std::ostream &stream, offs_t pc, uint32_t op) co
case 0x2c: case 0x2c:
return dasm_move_cond(stream, pc, op); return dasm_move_cond(stream, pc, op);
case 0x2e: case 0x2e:
if ((m_version >= 9) && (RS1 == 0)) if ((m_version >= v9) && (RS1 == 0))
{ {
if (USEIMM) util::stream_format(stream, "%-*s%d,%s", m_op_field_width, "popc", SIMM13, REG_NAMES[RD]); if (USEIMM) util::stream_format(stream, "%-*s%d,%s", m_op_field_width, "popc", SIMM13, REG_NAMES[RD]);
else util::stream_format(stream, "%-*s%s,%s", m_op_field_width, "popc", REG_NAMES[RS2], REG_NAMES[RD]); else util::stream_format(stream, "%-*s%s,%s", m_op_field_width, "popc", REG_NAMES[RS2], REG_NAMES[RD]);
@ -924,7 +924,7 @@ offs_t sparc_disassembler::dasm(std::ostream &stream, offs_t pc, uint32_t op) co
case 0x30: case 0x30:
return dasm_write_state_reg(stream, pc, op); return dasm_write_state_reg(stream, pc, op);
case 0x31: case 0x31:
if (m_version >= 9) if (m_version >= v9)
{ {
switch (RD) switch (RD)
{ {
@ -952,7 +952,7 @@ offs_t sparc_disassembler::dasm(std::ostream &stream, offs_t pc, uint32_t op) co
} }
break; break;
case 0x32: case 0x32:
if (m_version >= 9) if (m_version >= v9)
{ {
if (V9_PRIV_REG_NAMES[RD]) if (V9_PRIV_REG_NAMES[RD])
{ {
@ -979,7 +979,7 @@ offs_t sparc_disassembler::dasm(std::ostream &stream, offs_t pc, uint32_t op) co
} }
break; break;
case 0x33: case 0x33:
if (m_version <= 8) if (m_version <= v8)
{ {
if (RS1 == 0) if (RS1 == 0)
{ {
@ -1010,13 +1010,9 @@ offs_t sparc_disassembler::dasm(std::ostream &stream, offs_t pc, uint32_t op) co
case 0x3a: case 0x3a:
return dasm_tcc(stream, pc, op); return dasm_tcc(stream, pc, op);
case 0x3b: case 0x3b:
if (m_version >= 8) util::stream_format(stream, "%-*s", m_op_field_width, m_version >= v8 ? "flush" : "iflush");
{
util::stream_format(stream, "%-*s", m_op_field_width, "flush");
dasm_address(stream, op); dasm_address(stream, op);
return 4 | SUPPORTED; return 4 | SUPPORTED;
}
break;
case 0x3c: case 0x3c:
if (!USEIMM && (RS1 == RS2) && (RS2 == RD) && (RD == 0)) if (!USEIMM && (RS1 == RS2) && (RS2 == RD) && (RD == 0))
{ {
@ -1032,7 +1028,7 @@ offs_t sparc_disassembler::dasm(std::ostream &stream, offs_t pc, uint32_t op) co
} }
break; break;
case 0x3e: case 0x3e:
if ((m_version >= 9) & ((op & 0x7ffff) == 0)) if ((m_version >= v9) & ((op & 0x7ffff) == 0))
{ {
switch (RD) switch (RD)
{ {
@ -1088,7 +1084,7 @@ offs_t sparc_disassembler::dasm_invalid(std::ostream &stream, offs_t pc, uint32_
} }
else if ((OP == 2) && ((OP3 == 0x36) || (OP3 == 0x37))) else if ((OP == 2) && ((OP3 == 0x36) || (OP3 == 0x37)))
{ {
if (m_version >= 9) if (m_version >= v9)
util::stream_format(stream, "IMPDEP%d impl-dep=%02x impl-dep=%05x", 1 + (OP3 & 1), RD, op & 0x7ffff); util::stream_format(stream, "IMPDEP%d impl-dep=%02x impl-dep=%05x", 1 + (OP3 & 1), RD, op & 0x7ffff);
else else
util::stream_format(stream, "CPop%d opf=%03x rd=%d rs1=%d rs2=%d", 1 + (OP3 & 1), OPC, RD, RS1, RS2); util::stream_format(stream, "CPop%d opf=%03x rd=%d rs1=%d rs2=%d", 1 + (OP3 & 1), OPC, RD, RS1, RS2);
@ -1126,7 +1122,7 @@ offs_t sparc_disassembler::dasm_branch(std::ostream &stream, offs_t pc, uint32_t
offs_t sparc_disassembler::dasm_shift(std::ostream &stream, offs_t pc, uint32_t op, const char *mnemonic, const char *mnemonicx, const char *mnemonicx0) const offs_t sparc_disassembler::dasm_shift(std::ostream &stream, offs_t pc, uint32_t op, const char *mnemonic, const char *mnemonicx, const char *mnemonicx0) const
{ {
if ((m_version >= 9) && USEEXT) if ((m_version >= v9) && USEEXT)
{ {
if (USEIMM) if (USEIMM)
util::stream_format(stream, "%-*s%s,%d,%s", m_op_field_width, mnemonicx, REG_NAMES[RS1], SHCNT64, REG_NAMES[RD]); util::stream_format(stream, "%-*s%s,%d,%s", m_op_field_width, mnemonicx, REG_NAMES[RS1], SHCNT64, REG_NAMES[RD]);
@ -1156,7 +1152,7 @@ offs_t sparc_disassembler::dasm_read_state_reg(std::ostream &stream, offs_t pc,
util::stream_format(stream, "%-*s%%y,%s", m_op_field_width, "rd", REG_NAMES[RD]); util::stream_format(stream, "%-*s%%y,%s", m_op_field_width, "rd", REG_NAMES[RD]);
return 4 | SUPPORTED; return 4 | SUPPORTED;
} }
else if ((m_version == 8) || ((m_version >= 9) && !USEIMM)) else if ((m_version == v8) || ((m_version >= v9) && !USEIMM))
{ {
if (!USEIMM && (RS1 == 15) && (RD == 0)) if (!USEIMM && (RS1 == 15) && (RD == 0))
{ {
@ -1176,7 +1172,7 @@ offs_t sparc_disassembler::dasm_read_state_reg(std::ostream &stream, offs_t pc,
} }
} }
} }
else if ((m_version >= 9) && USEIMM && (RS1 == 15) && (RD == 0)) else if ((m_version >= v9) && USEIMM && (RS1 == 15) && (RD == 0))
{ {
util::stream_format(stream, "%-*s", m_op_field_width, "membar"); util::stream_format(stream, "%-*s", m_op_field_width, "membar");
uint32_t mask(MMASK | (CMASK << 4)); uint32_t mask(MMASK | (CMASK << 4));
@ -1216,9 +1212,9 @@ offs_t sparc_disassembler::dasm_write_state_reg(std::ostream &stream, offs_t pc,
} }
return 4 | SUPPORTED; return 4 | SUPPORTED;
} }
else if (m_version >= 8) else if (m_version >= v8)
{ {
if ((m_version >= 9) && USEIMM && (RS1 == 0) && (RD == 15)) if ((m_version >= v9) && USEIMM && (RS1 == 0) && (RD == 15))
{ {
util::stream_format(stream, "%-*s%d", m_op_field_width, "sir", SIMM13); util::stream_format(stream, "%-*s%d", m_op_field_width, "sir", SIMM13);
return 4 | SUPPORTED; return 4 | SUPPORTED;
@ -1265,7 +1261,7 @@ offs_t sparc_disassembler::dasm_write_state_reg(std::ostream &stream, offs_t pc,
offs_t sparc_disassembler::dasm_move_cond(std::ostream &stream, offs_t pc, uint32_t op) const offs_t sparc_disassembler::dasm_move_cond(std::ostream &stream, offs_t pc, uint32_t op) const
{ {
if ((m_version < 9) || !MOVCC_CC_NAMES[MOVCC]) return dasm_invalid(stream, pc, op); if ((m_version < v9) || !MOVCC_CC_NAMES[MOVCC]) return dasm_invalid(stream, pc, op);
const std::streampos start_position(stream.tellp()); const std::streampos start_position(stream.tellp());
util::stream_format(stream, "mov%s", MOVCC_COND_NAMES[MOVCOND | ((MOVCC << 2) & 16)]); util::stream_format(stream, "mov%s", MOVCC_COND_NAMES[MOVCOND | ((MOVCC << 2) & 16)]);
@ -1280,7 +1276,7 @@ offs_t sparc_disassembler::dasm_move_cond(std::ostream &stream, offs_t pc, uint3
offs_t sparc_disassembler::dasm_move_reg_cond(std::ostream &stream, offs_t pc, uint32_t op) const offs_t sparc_disassembler::dasm_move_reg_cond(std::ostream &stream, offs_t pc, uint32_t op) const
{ {
if ((m_version < 9) || !MOVE_INT_COND_MNEMONICS[RCOND]) return dasm_invalid(stream, pc, op); if ((m_version < v9) || !MOVE_INT_COND_MNEMONICS[RCOND]) return dasm_invalid(stream, pc, op);
if (USEIMM) if (USEIMM)
util::stream_format(stream, "%-*s%s,%d,%s", m_op_field_width, MOVE_INT_COND_MNEMONICS[RCOND], REG_NAMES[RS1], SIMM10, REG_NAMES[RD]); util::stream_format(stream, "%-*s%s,%d,%s", m_op_field_width, MOVE_INT_COND_MNEMONICS[RCOND], REG_NAMES[RS1], SIMM10, REG_NAMES[RD]);
@ -1307,7 +1303,7 @@ offs_t sparc_disassembler::dasm_fpop1(std::ostream &stream, offs_t pc, uint32_t
offs_t sparc_disassembler::dasm_fpop2(std::ostream &stream, offs_t pc, uint32_t op) const offs_t sparc_disassembler::dasm_fpop2(std::ostream &stream, offs_t pc, uint32_t op) const
{ {
// Move Floating-Point Register on Condition // Move Floating-Point Register on Condition
if ((m_version >= 9) && (((op >> 18) & 1) == 0) && MOVCC_CC_NAMES[OPFCC]) if ((m_version >= v9) && (((op >> 18) & 1) == 0) && MOVCC_CC_NAMES[OPFCC])
{ {
const char *mnemonic; const char *mnemonic;
bool shift; bool shift;
@ -1331,7 +1327,7 @@ offs_t sparc_disassembler::dasm_fpop2(std::ostream &stream, offs_t pc, uint32_t
const auto it(m_fpop2_desc.find(OPF)); const auto it(m_fpop2_desc.find(OPF));
if (it != m_fpop2_desc.end()) if (it != m_fpop2_desc.end())
{ {
if (m_version >= 9) if (m_version >= v9)
{ {
if (it->second.int_rs1) if (it->second.int_rs1)
{ {
@ -1428,7 +1424,7 @@ offs_t sparc_disassembler::dasm_jmpl(std::ostream &stream, offs_t pc, uint32_t o
offs_t sparc_disassembler::dasm_return(std::ostream &stream, offs_t pc, uint32_t op) const offs_t sparc_disassembler::dasm_return(std::ostream &stream, offs_t pc, uint32_t op) const
{ {
util::stream_format(stream, "%-*s", m_op_field_width, (m_version >= 9) ? "return" : "rett"); util::stream_format(stream, "%-*s", m_op_field_width, (m_version >= v9) ? "return" : "rett");
dasm_address(stream, op); dasm_address(stream, op);
return 4 | STEP_OUT | step_over_extra(1) | SUPPORTED; return 4 | STEP_OUT | step_over_extra(1) | SUPPORTED;
} }
@ -1442,7 +1438,7 @@ offs_t sparc_disassembler::dasm_tcc(std::ostream &stream, offs_t pc, uint32_t op
}; };
static const char *const cc_names[4] = { "%icc", nullptr, "%xcc", nullptr }; static const char *const cc_names[4] = { "%icc", nullptr, "%xcc", nullptr };
const char *const mnemonic(tcc_names[COND]); const char *const mnemonic(tcc_names[COND]);
if (m_version >= 9) if (m_version >= v9)
{ {
const char *const cc(cc_names[TCCCC]); const char *const cc(cc_names[TCCCC]);
if (!cc) return dasm_invalid(stream, pc, op); if (!cc) return dasm_invalid(stream, pc, op);
@ -1469,7 +1465,7 @@ offs_t sparc_disassembler::dasm_tcc(std::ostream &stream, offs_t pc, uint32_t op
offs_t sparc_disassembler::dasm_ldst(std::ostream &stream, offs_t pc, uint32_t op) const offs_t sparc_disassembler::dasm_ldst(std::ostream &stream, offs_t pc, uint32_t op) const
{ {
if (m_version >= 9) if (m_version >= v9)
{ {
switch (OP3) switch (OP3)
{ {
@ -1565,7 +1561,7 @@ offs_t sparc_disassembler::dasm_ldst(std::ostream &stream, offs_t pc, uint32_t o
if (it == m_ldst_desc.end()) if (it == m_ldst_desc.end())
return dasm_invalid(stream, pc, op); return dasm_invalid(stream, pc, op);
if (it->second.alternate && USEIMM && (m_version < 9)) if (it->second.alternate && USEIMM && (m_version < v9))
return dasm_invalid(stream, pc, op); return dasm_invalid(stream, pc, op);
if (it->second.g0_synth && (RD == 0)) if (it->second.g0_synth && (RD == 0))