From b63e1f9fddbb46342ccadfe97fb42042267ec095 Mon Sep 17 00:00:00 2001 From: Wilbert Pol Date: Mon, 7 Jul 2014 20:02:49 +0000 Subject: [PATCH] sh4: Modernized cpu core (nw) --- src/emu/cpu/sh4/sh3comn.c | 383 ++-- src/emu/cpu/sh4/sh4.c | 3592 ++++++++++++++++++----------------- src/emu/cpu/sh4/sh4.h | 659 ++++++- src/emu/cpu/sh4/sh4comn.c | 876 ++++----- src/emu/cpu/sh4/sh4comn.h | 198 +- src/emu/cpu/sh4/sh4dmac.c | 463 +++-- src/emu/cpu/sh4/sh4dmac.h | 68 +- src/emu/cpu/sh4/sh4tmu.c | 245 ++- src/emu/cpu/sh4/sh4tmu.h | 28 - src/mame/drivers/aristmk6.c | 12 +- src/mame/drivers/atvtrack.c | 23 +- src/mame/drivers/cv1k.c | 40 +- src/mame/drivers/naomi.c | 13 +- src/mame/includes/dc.h | 2 +- src/mame/machine/dc.c | 6 +- src/mame/machine/maple-dc.c | 8 +- src/mess/drivers/dccons.c | 13 +- src/mess/drivers/sh4robot.c | 12 +- src/mess/machine/dccons.c | 2 +- 19 files changed, 3578 insertions(+), 3065 deletions(-) diff --git a/src/emu/cpu/sh4/sh3comn.c b/src/emu/cpu/sh4/sh3comn.c index 5dd27fb8862..01bb157758c 100644 --- a/src/emu/cpu/sh4/sh3comn.c +++ b/src/emu/cpu/sh4/sh3comn.c @@ -10,59 +10,58 @@ /* High internal area (ffffxxxx) */ -WRITE32_MEMBER( sh3_device::sh3_internal_high_w ) +WRITE32_MEMBER( sh3_base_device::sh3_internal_high_w ) { - sh4_state *sh4 = get_safe_token(this); - COMBINE_DATA(&sh4->m_sh3internal_upper[offset]); + COMBINE_DATA(&m_sh3internal_upper[offset]); switch (offset) { case SH3_ICR0_IPRA_ADDR: if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - ICR0)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); - sh4_handler_ipra_w(sh4,data&0xffff,mem_mask&0xffff); + logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_ICR0_IPRA_ADDR - IPRA)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + sh4_handler_ipra_w(data&0xffff,mem_mask&0xffff); } break; case SH3_IPRB_ADDR: - logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_IPRB_ADDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (SH3_IPRB_ADDR)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); break; case SH3_TOCR_TSTR_ADDR: - logerror("'%s' (%08x): TMU internal write to %08x = %08x & %08x (SH3_TOCR_TSTR_ADDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + logerror("'%s' (%08x): TMU internal write to %08x = %08x & %08x (SH3_TOCR_TSTR_ADDR)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); if (mem_mask&0xff000000) { - sh4_handle_tocr_addr_w(sh4, (data>>24)&0xffff, (mem_mask>>24)&0xff); + sh4_handle_tocr_addr_w((data>>24)&0xffff, (mem_mask>>24)&0xff); } if (mem_mask&0x0000ff00) { - sh4_handle_tstr_addr_w(sh4, (data>>8)&0xff, (mem_mask>>8)&0xff); + sh4_handle_tstr_addr_w((data>>8)&0xff, (mem_mask>>8)&0xff); } if (mem_mask&0x00ff00ff) { fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (write)\n"); } break; - case SH3_TCOR0_ADDR: sh4_handle_tcor0_addr_w(sh4, data, mem_mask);break; - case SH3_TCOR1_ADDR: sh4_handle_tcor1_addr_w(sh4, data, mem_mask);break; - case SH3_TCOR2_ADDR: sh4_handle_tcor2_addr_w(sh4, data, mem_mask);break; - case SH3_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(sh4, data, mem_mask);break; - case SH3_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(sh4, data, mem_mask);break; - case SH3_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(sh4, data, mem_mask);break; - case SH3_TCR0_ADDR: sh4_handle_tcr0_addr_w(sh4, data>>16, mem_mask>>16);break; - case SH3_TCR1_ADDR: sh4_handle_tcr1_addr_w(sh4, data>>16, mem_mask>>16);break; - case SH3_TCR2_ADDR: sh4_handle_tcr2_addr_w(sh4, data>>16, mem_mask>>16);break; - case SH3_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(sh4,data, mem_mask);break; + case SH3_TCOR0_ADDR: sh4_handle_tcor0_addr_w(data, mem_mask);break; + case SH3_TCOR1_ADDR: sh4_handle_tcor1_addr_w(data, mem_mask);break; + case SH3_TCOR2_ADDR: sh4_handle_tcor2_addr_w(data, mem_mask);break; + case SH3_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(data, mem_mask);break; + case SH3_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(data, mem_mask);break; + case SH3_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(data, mem_mask);break; + case SH3_TCR0_ADDR: sh4_handle_tcr0_addr_w(data>>16, mem_mask>>16);break; + case SH3_TCR1_ADDR: sh4_handle_tcr1_addr_w(data>>16, mem_mask>>16);break; + case SH3_TCR2_ADDR: sh4_handle_tcr2_addr_w(data>>16, mem_mask>>16);break; + case SH3_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data, mem_mask);break; default: - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (unk)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (unk)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,data,mem_mask); break; } @@ -72,101 +71,97 @@ WRITE32_MEMBER( sh3_device::sh3_internal_high_w ) } -READ32_MEMBER( sh3_device::sh3_internal_high_r ) +READ32_MEMBER( sh3_base_device::sh3_internal_high_r ) { - sh4_state *sh4 = get_safe_token(this); - UINT32 ret = 0; switch (offset) { case SH3_ICR0_IPRA_ADDR: - logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_ICR0_IPRA_ADDR - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]); - return (sh4->m_sh3internal_upper[offset] & 0xffff0000) | (sh4->SH4_IPRA & 0xffff); + logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_ICR0_IPRA_ADDR - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]); + return (m_sh3internal_upper[offset] & 0xffff0000) | (m_SH4_IPRA & 0xffff); case SH3_IPRB_ADDR: - logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_IPRB_ADDR - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]); - return sh4->m_sh3internal_upper[offset]; + logerror("'%s' (%08x): INTC internal read from %08x mask %08x (SH3_IPRB_ADDR - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]); + return m_sh3internal_upper[offset]; case SH3_TOCR_TSTR_ADDR: if (mem_mask&0xff00000) { - ret |= (sh4_handle_tocr_addr_r(sh4, mem_mask)&0xff)<<24; + ret |= (sh4_handle_tocr_addr_r(mem_mask)&0xff)<<24; } if (mem_mask&0x0000ff00) { - ret |= (sh4_handle_tstr_addr_r(sh4, mem_mask)&0xff)<<8; + ret |= (sh4_handle_tstr_addr_r(mem_mask)&0xff)<<8; } if (mem_mask&0x00ff00ff) { fatalerror("SH3_TOCR_TSTR_ADDR unused bits accessed (read)\n"); } return ret; - case SH3_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(sh4, mem_mask); - case SH3_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(sh4, mem_mask); - case SH3_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(sh4, mem_mask); - case SH3_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(sh4, mem_mask); - case SH3_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(sh4, mem_mask); - case SH3_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(sh4, mem_mask); - case SH3_TCR0_ADDR: return sh4_handle_tcr0_addr_r(sh4, mem_mask)<<16; - case SH3_TCR1_ADDR: return sh4_handle_tcr1_addr_r(sh4, mem_mask)<<16; - case SH3_TCR2_ADDR: return sh4_handle_tcr2_addr_r(sh4, mem_mask)<<16; - case SH3_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(sh4, mem_mask); + case SH3_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(mem_mask); + case SH3_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(mem_mask); + case SH3_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(mem_mask); + case SH3_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(mem_mask); + case SH3_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(mem_mask); + case SH3_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(mem_mask); + case SH3_TCR0_ADDR: return sh4_handle_tcr0_addr_r(mem_mask)<<16; + case SH3_TCR1_ADDR: return sh4_handle_tcr1_addr_r(mem_mask)<<16; + case SH3_TCR2_ADDR: return sh4_handle_tcr2_addr_r(mem_mask)<<16; + case SH3_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(mem_mask); case SH3_TRA_ADDR: - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]); - return sh4->m_sh3internal_upper[offset]; + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 TRA - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]); + return m_sh3internal_upper[offset]; case SH3_EXPEVT_ADDR: - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]); - return sh4->m_sh3internal_upper[offset]; + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 EXPEVT - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]); + return m_sh3internal_upper[offset]; case SH3_INTEVT_ADDR: - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, sh4->m_sh3internal_upper[offset]); + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SH3 INTEVT - %08x)\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask, m_sh3internal_upper[offset]); fatalerror("INTEVT unsupported on SH3\n"); - return sh4->m_sh3internal_upper[offset]; + return m_sh3internal_upper[offset]; default: - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask); - return sh4->m_sh3internal_upper[offset]; + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n",tag(), m_pc & AM,(offset *4)+SH3_UPPER_REGBASE,mem_mask); + return m_sh3internal_upper[offset]; } } -READ32_MEMBER( sh3_device::sh3_internal_r ) +READ32_MEMBER( sh3_base_device::sh3_internal_r ) { - sh4_state *sh4 = get_safe_token(this); - if (offset<0x1000) { switch (offset) { - case SH3_SAR0_ADDR: return sh4_handle_sar0_addr_r(sh4,mem_mask); - case SH3_SAR1_ADDR: return sh4_handle_sar1_addr_r(sh4,mem_mask); - case SH3_SAR2_ADDR: return sh4_handle_sar2_addr_r(sh4,mem_mask); - case SH3_SAR3_ADDR: return sh4_handle_sar3_addr_r(sh4,mem_mask); - case SH3_DAR0_ADDR: return sh4_handle_dar0_addr_r(sh4,mem_mask); - case SH3_DAR1_ADDR: return sh4_handle_dar1_addr_r(sh4,mem_mask); - case SH3_DAR2_ADDR: return sh4_handle_dar2_addr_r(sh4,mem_mask); - case SH3_DAR3_ADDR: return sh4_handle_dar3_addr_r(sh4,mem_mask); - case SH3_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(sh4,mem_mask); - case SH3_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(sh4,mem_mask); - case SH3_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(sh4,mem_mask); - case SH3_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(sh4,mem_mask); - case SH3_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(sh4,mem_mask); - case SH3_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(sh4,mem_mask); - case SH3_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(sh4,mem_mask); - case SH3_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(sh4,mem_mask); - case SH3_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(sh4,mem_mask)<<16; + case SH3_SAR0_ADDR: return sh4_handle_sar0_addr_r(mem_mask); + case SH3_SAR1_ADDR: return sh4_handle_sar1_addr_r(mem_mask); + case SH3_SAR2_ADDR: return sh4_handle_sar2_addr_r(mem_mask); + case SH3_SAR3_ADDR: return sh4_handle_sar3_addr_r(mem_mask); + case SH3_DAR0_ADDR: return sh4_handle_dar0_addr_r(mem_mask); + case SH3_DAR1_ADDR: return sh4_handle_dar1_addr_r(mem_mask); + case SH3_DAR2_ADDR: return sh4_handle_dar2_addr_r(mem_mask); + case SH3_DAR3_ADDR: return sh4_handle_dar3_addr_r(mem_mask); + case SH3_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(mem_mask); + case SH3_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(mem_mask); + case SH3_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(mem_mask); + case SH3_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(mem_mask); + case SH3_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(mem_mask); + case SH3_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(mem_mask); + case SH3_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(mem_mask); + case SH3_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(mem_mask); + case SH3_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(mem_mask)<<16; case INTEVT2: { - // logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + // logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (INTEVT2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } break; @@ -176,17 +171,17 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xff000000) { - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } if (mem_mask & 0x0000ff00) { - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR1)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } - fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); + fatalerror("'%s' (%08x): unmapped internal read from %08x mask %08x (IRR0/1 unused bits)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); } } break; @@ -195,14 +190,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xffff0000) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_A)<<24; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_A)<<24; } if (mem_mask & 0x0000ffff) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_B)<<8; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_B)<<8; } } break; @@ -211,14 +206,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xffff0000) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_C)<<24; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PCDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_C)<<24; } if (mem_mask & 0x0000ffff) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_D)<<8; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PDDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_D)<<8; } } break; @@ -227,14 +222,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xffff0000) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_E)<<24; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PEDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_E)<<24; } if (mem_mask & 0x0000ffff) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_F)<<8; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PFDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_F)<<8; } } break; @@ -243,14 +238,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xffff0000) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_G)<<24; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PGDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_G)<<24; } if (mem_mask & 0x0000ffff) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_H)<<8; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PHDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_H)<<8; } } break; @@ -259,14 +254,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xffff0000) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_J)<<24; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PJDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_J)<<24; } if (mem_mask & 0x0000ffff) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_K)<<8; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PKDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_K)<<8; } } break; @@ -275,14 +270,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xffff0000) { - //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PLDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->io->read_qword(SH3_PORT_L)<<24; + //logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (PLDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_io->read_qword(SH3_PORT_L)<<24; } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SCPDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - //return sh4->io->read_qword(SH3_PORT_K)<<8; + logerror("'%s' (%08x): unmapped internal read from %08x mask %08x (SCPDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + //return m_io->read_qword(SH3_PORT_K)<<8; } } break; @@ -292,14 +287,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xff000000) { - logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSMR2 - Serial Mode Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } if (mem_mask & 0x0000ff00) { - logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCBRR2 - Bit Rate Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } } break; @@ -308,14 +303,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xff000000) { - logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSCR2 - Serial Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } if (mem_mask & 0x0000ff00) { - logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } } break; @@ -324,14 +319,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCSSR2 - Serial Status Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } if (mem_mask & 0x0000ff00) { - logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } } break; @@ -340,14 +335,14 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) { if (mem_mask & 0xff000000) { - logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFCR2 - Fifo Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,mem_mask); - return sh4->m_sh3internal_lower[offset]; + logerror("'%s' (%08x): SCIF internal read from %08x mask %08x (SCFDR2 - Fifo Data Count Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,mem_mask); + return m_sh3internal_lower[offset]; } } break; @@ -356,7 +351,7 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) default: { logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n", - sh4->device->tag(), sh4->pc & AM, + tag(), m_pc & AM, (offset *4)+0x4000000, mem_mask); } @@ -368,7 +363,7 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) else { logerror("'%s' (%08x): unmapped internal read from %08x mask %08x\n", - sh4->device->tag(), sh4->pc & AM, + tag(), m_pc & AM, (offset *4)+0x4000000, mem_mask); } @@ -378,36 +373,32 @@ READ32_MEMBER( sh3_device::sh3_internal_r ) /* Lower internal area */ -WRITE32_MEMBER( sh3_device::sh3_internal_w ) +WRITE32_MEMBER( sh3_base_device::sh3_internal_w ) { - sh4_state *sh4 = get_safe_token(this); - - - if (offset<0x1000) { - //UINT32 old = sh4->m_sh3internal_lower[offset]; - COMBINE_DATA(&sh4->m_sh3internal_lower[offset]); + //UINT32 old = m_sh3internal_lower[offset]; + COMBINE_DATA(&m_sh3internal_lower[offset]); switch (offset) { - case SH3_SAR0_ADDR: sh4_handle_sar0_addr_w(sh4,data,mem_mask); break; - case SH3_SAR1_ADDR: sh4_handle_sar1_addr_w(sh4,data,mem_mask); break; - case SH3_SAR2_ADDR: sh4_handle_sar2_addr_w(sh4,data,mem_mask); break; - case SH3_SAR3_ADDR: sh4_handle_sar3_addr_w(sh4,data,mem_mask); break; - case SH3_DAR0_ADDR: sh4_handle_dar0_addr_w(sh4,data,mem_mask); break; - case SH3_DAR1_ADDR: sh4_handle_dar1_addr_w(sh4,data,mem_mask); break; - case SH3_DAR2_ADDR: sh4_handle_dar2_addr_w(sh4,data,mem_mask); break; - case SH3_DAR3_ADDR: sh4_handle_dar3_addr_w(sh4,data,mem_mask); break; - case SH3_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(sh4,data,mem_mask); break; - case SH3_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(sh4,data,mem_mask); break; - case SH3_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(sh4,data,mem_mask); break; - case SH3_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(sh4,data,mem_mask); break; - case SH3_CHCR0_ADDR: sh4_handle_chcr0_addr_w(sh4,data,mem_mask); break; - case SH3_CHCR1_ADDR: sh4_handle_chcr1_addr_w(sh4,data,mem_mask); break; - case SH3_CHCR2_ADDR: sh4_handle_chcr2_addr_w(sh4,data,mem_mask); break; - case SH3_CHCR3_ADDR: sh4_handle_chcr3_addr_w(sh4,data,mem_mask); break; - case SH3_DMAOR_ADDR: sh4_handle_dmaor_addr_w(sh4,data>>16,mem_mask>>16); break; + case SH3_SAR0_ADDR: sh4_handle_sar0_addr_w(data,mem_mask); break; + case SH3_SAR1_ADDR: sh4_handle_sar1_addr_w(data,mem_mask); break; + case SH3_SAR2_ADDR: sh4_handle_sar2_addr_w(data,mem_mask); break; + case SH3_SAR3_ADDR: sh4_handle_sar3_addr_w(data,mem_mask); break; + case SH3_DAR0_ADDR: sh4_handle_dar0_addr_w(data,mem_mask); break; + case SH3_DAR1_ADDR: sh4_handle_dar1_addr_w(data,mem_mask); break; + case SH3_DAR2_ADDR: sh4_handle_dar2_addr_w(data,mem_mask); break; + case SH3_DAR3_ADDR: sh4_handle_dar3_addr_w(data,mem_mask); break; + case SH3_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data,mem_mask); break; + case SH3_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data,mem_mask); break; + case SH3_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data,mem_mask); break; + case SH3_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data,mem_mask); break; + case SH3_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data,mem_mask); break; + case SH3_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data,mem_mask); break; + case SH3_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data,mem_mask); break; + case SH3_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data,mem_mask); break; + case SH3_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data>>16,mem_mask>>16); break; case IRR0_IRR1: @@ -415,21 +406,21 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xff000000) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); // not sure if this is how we should clear lines in this core... - if (!(data & 0x01000000)) sh4_set_irq_line(sh4, 0, CLEAR_LINE); - if (!(data & 0x02000000)) sh4_set_irq_line(sh4, 1, CLEAR_LINE); - if (!(data & 0x04000000)) sh4_set_irq_line(sh4, 2, CLEAR_LINE); - if (!(data & 0x08000000)) sh4_set_irq_line(sh4, 3, CLEAR_LINE); + if (!(data & 0x01000000)) execute_set_input(0, CLEAR_LINE); + if (!(data & 0x02000000)) execute_set_input(1, CLEAR_LINE); + if (!(data & 0x04000000)) execute_set_input(2, CLEAR_LINE); + if (!(data & 0x08000000)) execute_set_input(3, CLEAR_LINE); } if (mem_mask & 0x0000ff00) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR1)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x00ff00ff) { - fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + fatalerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (IRR0/1 unused bits)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } } @@ -439,19 +430,19 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PINTER)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { data &= 0xffff; mem_mask &= 0xffff; - COMBINE_DATA(&sh4->SH4_IPRC); - logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); - sh4->exception_priority[SH4_INTC_IRL0] = INTPRI((sh4->SH4_IPRC & 0x000f)>>0, SH4_INTC_IRL0); - sh4->exception_priority[SH4_INTC_IRL1] = INTPRI((sh4->SH4_IPRC & 0x00f0)>>4, SH4_INTC_IRL1); - sh4->exception_priority[SH4_INTC_IRL2] = INTPRI((sh4->SH4_IPRC & 0x0f00)>>8, SH4_INTC_IRL2); - sh4->exception_priority[SH4_INTC_IRL3] = INTPRI((sh4->SH4_IPRC & 0xf000)>>12,SH4_INTC_IRL3); - sh4_exception_recompute(sh4); + COMBINE_DATA(&m_SH4_IPRC); + logerror("'%s' (%08x): INTC internal write to %08x = %08x & %08x (IPRC)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_exception_priority[SH4_INTC_IRL0] = INTPRI((m_SH4_IPRC & 0x000f)>>0, SH4_INTC_IRL0); + m_exception_priority[SH4_INTC_IRL1] = INTPRI((m_SH4_IPRC & 0x00f0)>>4, SH4_INTC_IRL1); + m_exception_priority[SH4_INTC_IRL2] = INTPRI((m_SH4_IPRC & 0x0f00)>>8, SH4_INTC_IRL2); + m_exception_priority[SH4_INTC_IRL3] = INTPRI((m_SH4_IPRC & 0xf000)>>12,SH4_INTC_IRL3); + sh4_exception_recompute(); } } break; @@ -460,12 +451,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PCCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PDCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -474,12 +465,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PECR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -489,12 +480,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -504,12 +495,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -519,12 +510,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PLCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (SCPCR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -533,14 +524,14 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - sh4->io->write_qword(SH3_PORT_A, (data>>24)&0xff); - // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_io->write_qword(SH3_PORT_A, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - sh4->io->write_qword(SH3_PORT_B, (data>>8)&0xff); - // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_io->write_qword(SH3_PORT_B, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -549,14 +540,14 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - sh4->io->write_qword(SH3_PORT_C, (data>>24)&0xff); - // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_io->write_qword(SH3_PORT_C, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PADR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - sh4->io->write_qword(SH3_PORT_D, (data>>8)&0xff); - // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_io->write_qword(SH3_PORT_D, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PBDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -564,14 +555,14 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - sh4->io->write_qword(SH3_PORT_E, (data>>24)&0xff); - // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_io->write_qword(SH3_PORT_E, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PEDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - sh4->io->write_qword(SH3_PORT_F, (data>>8)&0xff); - // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_io->write_qword(SH3_PORT_F, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PFDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -580,14 +571,14 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - sh4->io->write_qword(SH3_PORT_G, (data>>24)&0xff); - // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_io->write_qword(SH3_PORT_G, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PGDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - sh4->io->write_qword(SH3_PORT_H, (data>>8)&0xff); - // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_io->write_qword(SH3_PORT_H, (data>>8)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PHDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -597,14 +588,14 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - sh4->io->write_qword(SH3_PORT_J, (data>>24)&0xff); - // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_io->write_qword(SH3_PORT_J, (data>>24)&0xff); + // logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PJDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - sh4->io->write_qword(SH3_PORT_K, (data>>8)&0xff); - //logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + m_io->write_qword(SH3_PORT_K, (data>>8)&0xff); + //logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x (PKDR)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -613,12 +604,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xff000000) { - logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSMR2 - Serial Mode Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ff00) { - logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCBRR2 - Bit Rate Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -627,12 +618,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xff000000) { - logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSCR2 - Serial Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ff00) { - logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFTDR2 - Transmit FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -641,12 +632,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xffff0000) { - logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCSSR2 - Serial Status Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ff00) { - logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFRDR2 - Receive FIFO Data Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -655,12 +646,12 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) { if (mem_mask & 0xff000000) { - logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFCR2 - Fifo Control Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } if (mem_mask & 0x0000ffff) { - logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n",sh4->device->tag(), sh4->pc & AM,(offset *4)+0x4000000,data,mem_mask); + logerror("'%s' (%08x): SCIF internal write to %08x = %08x & %08x (SCFDR2 - Fifo Data Count Register 2)\n",tag(), m_pc & AM,(offset *4)+0x4000000,data,mem_mask); } } break; @@ -668,7 +659,7 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) default: { logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n", - sh4->device->tag(), sh4->pc & AM, + tag(), m_pc & AM, (offset *4)+0x4000000, data, mem_mask); @@ -680,7 +671,7 @@ WRITE32_MEMBER( sh3_device::sh3_internal_w ) else { logerror("'%s' (%08x): unmapped internal write to %08x = %08x & %08x\n", - sh4->device->tag(), sh4->pc & AM, + tag(), m_pc & AM, (offset *4)+0x4000000, data, mem_mask); diff --git a/src/emu/cpu/sh4/sh4.c b/src/emu/cpu/sh4/sh4.c index 93022061be0..ac369d79f29 100644 --- a/src/emu/cpu/sh4/sh4.c +++ b/src/emu/cpu/sh4/sh4.c @@ -30,46 +30,150 @@ #include "sh3comn.h" #include "sh4tmu.h" -#ifndef USE_SH4DRC CPU_DISASSEMBLE( sh4 ); CPU_DISASSEMBLE( sh4be ); -typedef const void (*sh4ophandler)(sh4_state*, const UINT16); -sh4ophandler master_ophandler_table[0x10000]; -void sh4_build_optable(sh4_state* sh4); +const device_type SH3LE = &device_creator; +const device_type SH3BE = &device_creator; +const device_type SH4LE = &device_creator; +const device_type SH4BE = &device_creator; + + +#if 0 +/*When OC index mode is off (CCR.OIX = 0)*/ +static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64, sh4_base_device ) + AM_RANGE(0x1C000000, 0x1C000FFF) AM_RAM AM_MIRROR(0x03FFD000) + AM_RANGE(0x1C002000, 0x1C002FFF) AM_RAM AM_MIRROR(0x03FFD000) + AM_RANGE(0xE0000000, 0xE000003F) AM_RAM AM_MIRROR(0x03FFFFC0) +ADDRESS_MAP_END +#endif + +/*When OC index mode is on (CCR.OIX = 1)*/ +static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64, sh4_base_device ) + AM_RANGE(0x1C000000, 0x1C000FFF) AM_RAM AM_MIRROR(0x01FFF000) + AM_RANGE(0x1E000000, 0x1E000FFF) AM_RAM AM_MIRROR(0x01FFF000) + AM_RANGE(0xE0000000, 0xE000003F) AM_RAM AM_MIRROR(0x03FFFFC0) // todo: store queues should be write only on DC's SH4, executing PREFM shouldn't cause an actual memory read access! + AM_RANGE(0xF6000000, 0xF7FFFFFF) AM_READWRITE(sh4_tlb_r,sh4_tlb_w) + AM_RANGE(0xFE000000, 0xFFFFFFFF) AM_READWRITE32(sh4_internal_r, sh4_internal_w, U64(0xffffffffffffffff)) +ADDRESS_MAP_END + +static ADDRESS_MAP_START( sh3_internal_map, AS_PROGRAM, 64, sh3_base_device ) + AM_RANGE(SH3_LOWER_REGBASE, SH3_LOWER_REGEND) AM_READWRITE32(sh3_internal_r, sh3_internal_w, U64(0xffffffffffffffff)) + AM_RANGE(SH3_UPPER_REGBASE, SH3_UPPER_REGEND) AM_READWRITE32(sh3_internal_high_r, sh3_internal_high_w, U64(0xffffffffffffffff)) +ADDRESS_MAP_END + + +sh34_base_device::sh34_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness, address_map_constructor internal) + : cpu_device(mconfig, type, name, tag, owner, clock, shortname, __FILE__) + , m_program_config("program", endianness, 64, 32, 0, internal) + , m_io_config("io", endianness, 64, 8) + , c_md2(0) + , c_md1(0) + , c_md0(0) + , c_md6(0) + , c_md4(0) + , c_md3(0) + , c_md5(0) + , c_md7(0) + , c_md8(0) + , c_clock(0) +{ +} + + +sh3_base_device::sh3_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness) + : sh34_base_device(mconfig, type, name, tag, owner, clock, shortname, endianness, ADDRESS_MAP_NAME(sh3_internal_map)) +{ + m_cpu_type = CPU_TYPE_SH3; +} + + +sh4_base_device::sh4_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness) + : sh34_base_device(mconfig, type, name, tag, owner, clock, shortname, endianness, ADDRESS_MAP_NAME(sh4_internal_map)) +{ + m_cpu_type = CPU_TYPE_SH4; +} + + +sh3_device::sh3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : sh3_base_device(mconfig, SH3LE, "SH-3 (little)", tag, owner, clock, "sh3", ENDIANNESS_LITTLE) +{ +} + + +sh3be_device::sh3be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : sh3_base_device(mconfig, SH3BE, "SH-3 (big)", tag, owner, clock, "sh3be", ENDIANNESS_BIG) +{ +} + + +sh4_device::sh4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : sh4_base_device(mconfig, SH4LE, "SH-4 (little)", tag, owner, clock, "sh4", ENDIANNESS_LITTLE) +{ +} + + +sh4be_device::sh4be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock) + : sh4_base_device(mconfig, SH4BE, "SH-4 (big)", tag, owner, clock, "sh4be", ENDIANNESS_BIG) +{ +} + + +offs_t sh34_base_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( sh4 ); + + return CPU_DISASSEMBLE_NAME(sh4)(this, buffer, pc, oprom, opram, options); +} + + +offs_t sh3be_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( sh4be ); + + return CPU_DISASSEMBLE_NAME(sh4be)(this, buffer, pc, oprom, opram, options); +} + + +offs_t sh4be_device::disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options) +{ + extern CPU_DISASSEMBLE( sh4be ); + + return CPU_DISASSEMBLE_NAME(sh4be)(this, buffer, pc, oprom, opram, options); +} /* Called for unimplemented opcodes */ -const void TODO(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::TODO(const UINT16 opcode) { } #if 0 int sign_of(int n) { - return(sh4->fr[n]>>31); + return(m_fr[n]>>31); } void zero(int n,int sign) { if (sign == 0) - sh4->fr[n] = 0x00000000; + m_fr[n] = 0x00000000; else - sh4->fr[n] = 0x80000000; -if ((sh4->fpscr & PR) == 1) - sh4->fr[n+1] = 0x00000000; + m_fr[n] = 0x80000000; +if ((m_fpscr & PR) == 1) + m_fr[n+1] = 0x00000000; } int data_type_of(int n) { UINT32 abs; - abs = sh4->fr[n] & 0x7fffffff; - if ((sh4->fpscr & PR) == 0) { /* Single-precision */ + abs = m_fr[n] & 0x7fffffff; + if ((m_fpscr & PR) == 0) { /* Single-precision */ if (abs < 0x00800000) { - if (((sh4->fpscr & DN) == 1) || (abs == 0x00000000)) { + if (((m_fpscr & DN) == 1) || (abs == 0x00000000)) { if (sign_of(n) == 0) { zero(n, 0); return(SH4_FPU_PZERO); @@ -95,7 +199,7 @@ UINT32 abs; return(SH4_FPU_sNaN); } else { /* Double-precision */ if (abs < 0x00100000) { - if (((sh4->fpscr & DN) == 1) || ((abs == 0x00000000) && (sh4->fr[n+1] == 0x00000000))) { + if (((m_fpscr & DN) == 1) || ((abs == 0x00000000) && (m_fr[n+1] == 0x00000000))) { if(sign_of(n) == 0) { zero(n, 0); return(SH4_FPU_PZERO); @@ -109,7 +213,7 @@ UINT32 abs; if (abs < 0x7ff00000) return(SH4_FPU_NORM); else - if ((abs == 0x7ff00000) && (sh4->fr[n+1] == 0x00000000)) { + if ((abs == 0x7ff00000) && (m_fr[n+1] == 0x00000000)) { if (sign_of(n) == 0) return(SH4_FPU_PINF); else @@ -124,121 +228,121 @@ UINT32 abs; } #endif -const UINT8 RB(sh4_state *sh4, offs_t A) +UINT8 sh34_base_device::RB(offs_t A) { if (A >= 0xe0000000) - return sh4->program->read_byte(A); + return m_program->read_byte(A); - return sh4->program->read_byte(A & AM); + return m_program->read_byte(A & AM); } -const UINT16 RW(sh4_state *sh4, offs_t A) +UINT16 sh34_base_device::RW(offs_t A) { if (A >= 0xe0000000) - return sh4->program->read_word(A); + return m_program->read_word(A); - return sh4->program->read_word(A & AM); + return m_program->read_word(A & AM); } -const UINT32 RL(sh4_state *sh4, offs_t A) +UINT32 sh34_base_device::RL(offs_t A) { if (A >= 0xe0000000) - return sh4->program->read_dword(A); + return m_program->read_dword(A); - return sh4->program->read_dword(A & AM); + return m_program->read_dword(A & AM); } -const void WB(sh4_state *sh4, offs_t A, UINT8 V) +void sh34_base_device::WB(offs_t A, UINT8 V) { if (A >= 0xe0000000) { - sh4->program->write_byte(A,V); + m_program->write_byte(A,V); return; } - sh4->program->write_byte(A & AM,V); + m_program->write_byte(A & AM,V); } -const void WW(sh4_state *sh4, offs_t A, UINT16 V) +void sh34_base_device::WW(offs_t A, UINT16 V) { if (A >= 0xe0000000) { - sh4->program->write_word(A,V); + m_program->write_word(A,V); return; } - sh4->program->write_word(A & AM,V); + m_program->write_word(A & AM,V); } -const void WL(sh4_state *sh4, offs_t A, UINT32 V) +void sh34_base_device::WL(offs_t A, UINT32 V) { if (A >= 0xe0000000) { - sh4->program->write_dword(A,V); + m_program->write_dword(A,V); return; } - sh4->program->write_dword(A & AM,V); + m_program->write_dword(A & AM,V); } /* code cycles t-bit * 0011 nnnn mmmm 1100 1 - * ADD Rm,Rn */ -const void ADD(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ADD(const UINT16 opcode) { - sh4->r[Rn] += sh4->r[Rm]; + m_r[Rn] += m_r[Rm]; } /* code cycles t-bit * 0111 nnnn iiii iiii 1 - * ADD #imm,Rn */ -const void ADDI(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ADDI(const UINT16 opcode) { - sh4->r[Rn] += (INT32)(INT16)(INT8)(opcode&0xff); + m_r[Rn] += (INT32)(INT16)(INT8)(opcode&0xff); } /* code cycles t-bit * 0011 nnnn mmmm 1110 1 carry * ADDC Rm,Rn */ -const void ADDC(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ADDC(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; UINT32 tmp0, tmp1; - tmp1 = sh4->r[n] + sh4->r[m]; - tmp0 = sh4->r[n]; - sh4->r[n] = tmp1 + (sh4->sr & T); + tmp1 = m_r[n] + m_r[m]; + tmp0 = m_r[n]; + m_r[n] = tmp1 + (m_sr & T); if (tmp0 > tmp1) - sh4->sr |= T; + m_sr |= T; else - sh4->sr &= ~T; - if (tmp1 > sh4->r[n]) - sh4->sr |= T; + m_sr &= ~T; + if (tmp1 > m_r[n]) + m_sr |= T; } /* code cycles t-bit * 0011 nnnn mmmm 1111 1 overflow * ADDV Rm,Rn */ -const void ADDV(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ADDV(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; INT32 dest, src, ans; - if ((INT32) sh4->r[n] >= 0) + if ((INT32) m_r[n] >= 0) dest = 0; else dest = 1; - if ((INT32) sh4->r[m] >= 0) + if ((INT32) m_r[m] >= 0) src = 0; else src = 1; src += dest; - sh4->r[n] += sh4->r[m]; - if ((INT32) sh4->r[n] >= 0) + m_r[n] += m_r[m]; + if ((INT32) m_r[n] >= 0) ans = 0; else ans = 1; @@ -246,21 +350,21 @@ const void ADDV(sh4_state *sh4, const UINT16 opcode) if (src == 0 || src == 2) { if (ans == 1) - sh4->sr |= T; + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } else - sh4->sr &= ~T; + m_sr &= ~T; } /* code cycles t-bit * 0010 nnnn mmmm 1001 1 - * AND Rm,Rn */ -const void AND(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::AND(const UINT16 opcode) { - sh4->r[Rn] &= sh4->r[Rm]; + m_r[Rn] &= m_r[Rm]; } @@ -268,36 +372,36 @@ const void AND(sh4_state *sh4, const UINT16 opcode) * 1100 1001 iiii iiii 1 - * AND #imm,R0 */ -const void ANDI(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ANDI(const UINT16 opcode) { - sh4->r[0] &= (opcode&0xff); + m_r[0] &= (opcode&0xff); } /* code cycles t-bit * 1100 1101 iiii iiii 1 - * AND.B #imm,@(R0,GBR) */ -const void ANDM(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ANDM(const UINT16 opcode) { UINT32 temp; - sh4->ea = sh4->gbr + sh4->r[0]; - temp = (opcode&0xff) & RB(sh4, sh4->ea ); - WB(sh4, sh4->ea, temp ); - sh4->sh4_icount -= 2; + m_ea = m_gbr + m_r[0]; + temp = (opcode&0xff) & RB( m_ea ); + WB(m_ea, temp ); + m_sh4_icount -= 2; } /* code cycles t-bit * 1000 1011 dddd dddd 3/1 - * BF disp8 */ -const void BF(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::BF(const UINT16 opcode) { - if ((sh4->sr & T) == 0) + if ((m_sr & T) == 0) { INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24; - sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; - sh4->sh4_icount -= 2; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount -= 2; } } @@ -305,14 +409,14 @@ const void BF(sh4_state *sh4, const UINT16 opcode) * 1000 1111 dddd dddd 3/1 - * BFS disp8 */ -const void BFS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::BFS(const UINT16 opcode) { - if ((sh4->sr & T) == 0) + if ((m_sr & T) == 0) { INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24; - sh4->delay = sh4->pc; - sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; - sh4->sh4_icount--; + m_delay = m_pc; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount--; } } @@ -320,74 +424,74 @@ const void BFS(sh4_state *sh4, const UINT16 opcode) * 1010 dddd dddd dddd 2 - * BRA disp12 */ -const void BRA(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::BRA(const UINT16 opcode) { INT32 disp = ((INT32)(opcode&0xfff) << 20) >> 20; #if BUSY_LOOP_HACKS if (disp == -2) { - UINT32 next_opcode = RW(sh4,sh4->ppc & AM); + UINT32 next_opcode = RW(m_ppc & AM); /* BRA $ * NOP */ if (next_opcode == 0x0009) - sh4->sh4_icount %= 3; /* cycles for BRA $ and NOP taken (3) */ + m_sh4_icount %= 3; /* cycles for BRA $ and NOP taken (3) */ } #endif - sh4->delay = sh4->pc; - sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; - sh4->sh4_icount--; + m_delay = m_pc; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount--; } /* code cycles t-bit * 0000 mmmm 0010 0011 2 - * BRAF Rm */ -const void BRAF(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::BRAF(const UINT16 opcode) { - sh4->delay = sh4->pc; - sh4->pc += sh4->r[Rn] + 2; - sh4->sh4_icount--; + m_delay = m_pc; + m_pc += m_r[Rn] + 2; + m_sh4_icount--; } /* code cycles t-bit * 1011 dddd dddd dddd 2 - * BSR disp12 */ -const void BSR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::BSR(const UINT16 opcode) { INT32 disp = ((INT32)(opcode&0xfff) << 20) >> 20; - sh4->pr = sh4->pc + 2; - sh4->delay = sh4->pc; - sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; - sh4->sh4_icount--; + m_pr = m_pc + 2; + m_delay = m_pc; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount--; } /* code cycles t-bit * 0000 mmmm 0000 0011 2 - * BSRF Rm */ -const void BSRF(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::BSRF(const UINT16 opcode) { - sh4->pr = sh4->pc + 2; - sh4->delay = sh4->pc; - sh4->pc += sh4->r[Rn] + 2; - sh4->sh4_icount--; + m_pr = m_pc + 2; + m_delay = m_pc; + m_pc += m_r[Rn] + 2; + m_sh4_icount--; } /* code cycles t-bit * 1000 1001 dddd dddd 3/1 - * BT disp8 */ -const void BT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::BT(const UINT16 opcode) { - if ((sh4->sr & T) != 0) + if ((m_sr & T) != 0) { INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24; - sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; - sh4->sh4_icount -= 2; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount -= 2; } } @@ -395,14 +499,14 @@ const void BT(sh4_state *sh4, const UINT16 opcode) * 1000 1101 dddd dddd 2/1 - * BTS disp8 */ -const void BTS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::BTS(const UINT16 opcode) { - if ((sh4->sr & T) != 0) + if ((m_sr & T) != 0) { INT32 disp = ((INT32)(opcode&0xff) << 24) >> 24; - sh4->delay = sh4->pc; - sh4->pc = sh4->ea = sh4->pc + disp * 2 + 2; - sh4->sh4_icount--; + m_delay = m_pc; + m_pc = m_ea = m_pc + disp * 2 + 2; + m_sh4_icount--; } } @@ -410,79 +514,79 @@ const void BTS(sh4_state *sh4, const UINT16 opcode) * 0000 0000 0010 1000 1 - * CLRMAC */ -const void CLRMAC(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CLRMAC(const UINT16 opcode) { - sh4->mach = 0; - sh4->macl = 0; + m_mach = 0; + m_macl = 0; } /* code cycles t-bit * 0000 0000 0000 1000 1 - * CLRT */ -const void CLRT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CLRT(const UINT16 opcode) { - sh4->sr &= ~T; + m_sr &= ~T; } /* code cycles t-bit * 0011 nnnn mmmm 0000 1 comparison result * CMP_EQ Rm,Rn */ -const void CMPEQ(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CMPEQ(const UINT16 opcode) { - if (sh4->r[Rn] == sh4->r[Rm]) - sh4->sr |= T; + if (m_r[Rn] == m_r[Rm]) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* code cycles t-bit * 0011 nnnn mmmm 0011 1 comparison result * CMP_GE Rm,Rn */ -const void CMPGE(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CMPGE(const UINT16 opcode) { - if ((INT32) sh4->r[Rn] >= (INT32) sh4->r[Rm]) - sh4->sr |= T; + if ((INT32) m_r[Rn] >= (INT32) m_r[Rm]) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* code cycles t-bit * 0011 nnnn mmmm 0111 1 comparison result * CMP_GT Rm,Rn */ -const void CMPGT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CMPGT(const UINT16 opcode) { - if ((INT32) sh4->r[Rn] > (INT32) sh4->r[Rm]) - sh4->sr |= T; + if ((INT32) m_r[Rn] > (INT32) m_r[Rm]) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* code cycles t-bit * 0011 nnnn mmmm 0110 1 comparison result * CMP_HI Rm,Rn */ -const void CMPHI(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CMPHI(const UINT16 opcode) { - if ((UINT32) sh4->r[Rn] > (UINT32) sh4->r[Rm]) - sh4->sr |= T; + if ((UINT32) m_r[Rn] > (UINT32) m_r[Rm]) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* code cycles t-bit * 0011 nnnn mmmm 0010 1 comparison result * CMP_HS Rm,Rn */ -const void CMPHS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CMPHS(const UINT16 opcode) { - if ((UINT32) sh4->r[Rn] >= (UINT32) sh4->r[Rm]) - sh4->sr |= T; + if ((UINT32) m_r[Rn] >= (UINT32) m_r[Rm]) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } @@ -490,43 +594,43 @@ const void CMPHS(sh4_state *sh4, const UINT16 opcode) * 0100 nnnn 0001 0101 1 comparison result * CMP_PL Rn */ -const void CMPPL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CMPPL(const UINT16 opcode) { - if ((INT32) sh4->r[Rn] > 0) - sh4->sr |= T; + if ((INT32) m_r[Rn] > 0) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* code cycles t-bit * 0100 nnnn 0001 0001 1 comparison result * CMP_PZ Rn */ -const void CMPPZ(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CMPPZ(const UINT16 opcode) { - if ((INT32) sh4->r[Rn] >= 0) - sh4->sr |= T; + if ((INT32) m_r[Rn] >= 0) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* code cycles t-bit * 0010 nnnn mmmm 1100 1 comparison result * CMP_STR Rm,Rn */ -const void CMPSTR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CMPSTR(const UINT16 opcode) { UINT32 temp; INT32 HH, HL, LH, LL; - temp = sh4->r[Rn] ^ sh4->r[Rm]; + temp = m_r[Rn] ^ m_r[Rm]; HH = (temp >> 24) & 0xff; HL = (temp >> 16) & 0xff; LH = (temp >> 8) & 0xff; LL = temp & 0xff; if (HH && HL && LH && LL) - sh4->sr &= ~T; + m_sr &= ~T; else - sh4->sr |= T; + m_sr |= T; } @@ -534,146 +638,146 @@ const void CMPSTR(sh4_state *sh4, const UINT16 opcode) * 1000 1000 iiii iiii 1 comparison result * CMP/EQ #imm,R0 */ -const void CMPIM(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CMPIM(const UINT16 opcode) { UINT32 imm = (UINT32)(INT32)(INT16)(INT8)(opcode&0xff); - if (sh4->r[0] == imm) - sh4->sr |= T; + if (m_r[0] == imm) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* code cycles t-bit * 0010 nnnn mmmm 0111 1 calculation result * DIV0S Rm,Rn */ -const void DIV0S(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::DIV0S(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if ((sh4->r[n] & 0x80000000) == 0) - sh4->sr &= ~Q; + if ((m_r[n] & 0x80000000) == 0) + m_sr &= ~Q; else - sh4->sr |= Q; - if ((sh4->r[m] & 0x80000000) == 0) - sh4->sr &= ~M; + m_sr |= Q; + if ((m_r[m] & 0x80000000) == 0) + m_sr &= ~M; else - sh4->sr |= M; - if ((sh4->r[m] ^ sh4->r[n]) & 0x80000000) - sh4->sr |= T; + m_sr |= M; + if ((m_r[m] ^ m_r[n]) & 0x80000000) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* code cycles t-bit * 0000 0000 0001 1001 1 0 * DIV0U */ -const void DIV0U(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::DIV0U(const UINT16 opcode) { - sh4->sr &= ~(M | Q | T); + m_sr &= ~(M | Q | T); } /* code cycles t-bit * 0011 nnnn mmmm 0100 1 calculation result * DIV1 Rm,Rn */ -const void DIV1(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::DIV1(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; UINT32 tmp0; UINT32 old_q; - old_q = sh4->sr & Q; - if (0x80000000 & sh4->r[n]) - sh4->sr |= Q; + old_q = m_sr & Q; + if (0x80000000 & m_r[n]) + m_sr |= Q; else - sh4->sr &= ~Q; + m_sr &= ~Q; - sh4->r[n] = (sh4->r[n] << 1) | (sh4->sr & T); + m_r[n] = (m_r[n] << 1) | (m_sr & T); if (!old_q) { - if (!(sh4->sr & M)) + if (!(m_sr & M)) { - tmp0 = sh4->r[n]; - sh4->r[n] -= sh4->r[m]; - if(!(sh4->sr & Q)) - if(sh4->r[n] > tmp0) - sh4->sr |= Q; + tmp0 = m_r[n]; + m_r[n] -= m_r[m]; + if(!(m_sr & Q)) + if(m_r[n] > tmp0) + m_sr |= Q; else - sh4->sr &= ~Q; + m_sr &= ~Q; else - if(sh4->r[n] > tmp0) - sh4->sr &= ~Q; + if(m_r[n] > tmp0) + m_sr &= ~Q; else - sh4->sr |= Q; + m_sr |= Q; } else { - tmp0 = sh4->r[n]; - sh4->r[n] += sh4->r[m]; - if(!(sh4->sr & Q)) + tmp0 = m_r[n]; + m_r[n] += m_r[m]; + if(!(m_sr & Q)) { - if(sh4->r[n] < tmp0) - sh4->sr &= ~Q; + if(m_r[n] < tmp0) + m_sr &= ~Q; else - sh4->sr |= Q; + m_sr |= Q; } else { - if(sh4->r[n] < tmp0) - sh4->sr |= Q; + if(m_r[n] < tmp0) + m_sr |= Q; else - sh4->sr &= ~Q; + m_sr &= ~Q; } } } else { - if (!(sh4->sr & M)) + if (!(m_sr & M)) { - tmp0 = sh4->r[n]; - sh4->r[n] += sh4->r[m]; - if(!(sh4->sr & Q)) - if(sh4->r[n] < tmp0) - sh4->sr |= Q; + tmp0 = m_r[n]; + m_r[n] += m_r[m]; + if(!(m_sr & Q)) + if(m_r[n] < tmp0) + m_sr |= Q; else - sh4->sr &= ~Q; + m_sr &= ~Q; else - if(sh4->r[n] < tmp0) - sh4->sr &= ~Q; + if(m_r[n] < tmp0) + m_sr &= ~Q; else - sh4->sr |= Q; + m_sr |= Q; } else { - tmp0 = sh4->r[n]; - sh4->r[n] -= sh4->r[m]; - if(!(sh4->sr & Q)) - if(sh4->r[n] > tmp0) - sh4->sr &= ~Q; + tmp0 = m_r[n]; + m_r[n] -= m_r[m]; + if(!(m_sr & Q)) + if(m_r[n] > tmp0) + m_sr &= ~Q; else - sh4->sr |= Q; + m_sr |= Q; else - if(sh4->r[n] > tmp0) - sh4->sr |= Q; + if(m_r[n] > tmp0) + m_sr |= Q; else - sh4->sr &= ~Q; + m_sr &= ~Q; } } - tmp0 = (sh4->sr & (Q | M)); + tmp0 = (m_sr & (Q | M)); if((!tmp0) || (tmp0 == 0x300)) /* if Q == M set T else clear T */ - sh4->sr |= T; + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* DMULS.L Rm,Rn */ -const void DMULS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::DMULS(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; @@ -681,13 +785,13 @@ const void DMULS(sh4_state *sh4, const UINT16 opcode) UINT32 temp0, temp1, temp2, temp3; INT32 tempm, tempn, fnLmL; - tempn = (INT32) sh4->r[n]; - tempm = (INT32) sh4->r[m]; + tempn = (INT32) m_r[n]; + tempm = (INT32) m_r[m]; if (tempn < 0) tempn = 0 - tempn; if (tempm < 0) tempm = 0 - tempm; - if ((INT32) (sh4->r[n] ^ sh4->r[m]) < 0) + if ((INT32) (m_r[n] ^ m_r[m]) < 0) fnLmL = -1; else fnLmL = 0; @@ -718,23 +822,23 @@ const void DMULS(sh4_state *sh4, const UINT16 opcode) else Res0 = (~Res0) + 1; } - sh4->mach = Res2; - sh4->macl = Res0; - sh4->sh4_icount--; + m_mach = Res2; + m_macl = Res0; + m_sh4_icount--; } /* DMULU.L Rm,Rn */ -const void DMULU(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::DMULU(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; UINT32 RnL, RnH, RmL, RmH, Res0, Res1, Res2; UINT32 temp0, temp1, temp2, temp3; - RnL = sh4->r[n] & 0x0000ffff; - RnH = (sh4->r[n] >> 16) & 0x0000ffff; - RmL = sh4->r[m] & 0x0000ffff; - RmH = (sh4->r[m] >> 16) & 0x0000ffff; + RnL = m_r[n] & 0x0000ffff; + RnH = (m_r[n] >> 16) & 0x0000ffff; + RmL = m_r[m] & 0x0000ffff; + RmH = (m_r[m] >> 16) & 0x0000ffff; temp0 = RmL * RnL; temp1 = RmH * RnL; temp2 = RmL * RnH; @@ -748,33 +852,33 @@ const void DMULU(sh4_state *sh4, const UINT16 opcode) if (Res0 < temp0) Res2++; Res2 = Res2 + ((Res1 >> 16) & 0x0000ffff) + temp3; - sh4->mach = Res2; - sh4->macl = Res0; - sh4->sh4_icount--; + m_mach = Res2; + m_macl = Res0; + m_sh4_icount--; } /* DT Rn */ -const void DT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::DT(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n]--; - if (sh4->r[n] == 0) - sh4->sr |= T; + m_r[n]--; + if (m_r[n] == 0) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; #if BUSY_LOOP_HACKS { - UINT32 next_opcode = RW(sh4,sh4->ppc & AM); + UINT32 next_opcode = RW(m_ppc & AM); /* DT Rn * BF $-2 */ if (next_opcode == 0x8bfd) { - while (sh4->r[n] > 1 && sh4->sh4_icount > 4) + while (m_r[n] > 1 && m_sh4_icount > 4) { - sh4->r[n]--; - sh4->sh4_icount -= 4; /* cycles for DT (1) and BF taken (3) */ + m_r[n]--; + m_sh4_icount -= 4; /* cycles for DT (1) and BF taken (3) */ } } } @@ -782,151 +886,151 @@ const void DT(sh4_state *sh4, const UINT16 opcode) } /* EXTS.B Rm,Rn */ -const void EXTSB(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::EXTSB(const UINT16 opcode) { - sh4->r[Rn] = ((INT32)sh4->r[Rm] << 24) >> 24; + m_r[Rn] = ((INT32)m_r[Rm] << 24) >> 24; } /* EXTS.W Rm,Rn */ -const void EXTSW(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::EXTSW(const UINT16 opcode) { - sh4->r[Rn] = ((INT32)sh4->r[Rm] << 16) >> 16; + m_r[Rn] = ((INT32)m_r[Rm] << 16) >> 16; } /* EXTU.B Rm,Rn */ -const void EXTUB(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::EXTUB(const UINT16 opcode) { - sh4->r[Rn] = sh4->r[Rm] & 0x000000ff; + m_r[Rn] = m_r[Rm] & 0x000000ff; } /* EXTU.W Rm,Rn */ -const void EXTUW(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::EXTUW(const UINT16 opcode) { - sh4->r[Rn] = sh4->r[Rm] & 0x0000ffff; + m_r[Rn] = m_r[Rm] & 0x0000ffff; } /* JMP @Rm */ -const void JMP(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::JMP(const UINT16 opcode) { - sh4->delay = sh4->pc; - sh4->pc = sh4->ea = sh4->r[Rn]; + m_delay = m_pc; + m_pc = m_ea = m_r[Rn]; } /* JSR @Rm */ -const void JSR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::JSR(const UINT16 opcode) { - sh4->delay = sh4->pc; - sh4->pr = sh4->pc + 2; - sh4->pc = sh4->ea = sh4->r[Rn]; - sh4->sh4_icount--; + m_delay = m_pc; + m_pr = m_pc + 2; + m_pc = m_ea = m_r[Rn]; + m_sh4_icount--; } /* LDC Rm,SR */ -const void LDCSR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCSR(const UINT16 opcode) { UINT32 reg; - reg = sh4->r[Rn]; - if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) - sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29); - if ((sh4->r[Rn] & sRB) != (sh4->sr & sRB)) - sh4_change_register_bank(sh4, sh4->r[Rn] & sRB ? 1 : 0); - sh4->sr = reg & FLAGS; - sh4_exception_recompute(sh4); + reg = m_r[Rn]; + if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + sh4_syncronize_register_bank((m_sr & sRB) >> 29); + if ((m_r[Rn] & sRB) != (m_sr & sRB)) + sh4_change_register_bank(m_r[Rn] & sRB ? 1 : 0); + m_sr = reg & FLAGS; + sh4_exception_recompute(); } /* LDC Rm,GBR */ -const void LDCGBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCGBR(const UINT16 opcode) { - sh4->gbr = sh4->r[Rn]; + m_gbr = m_r[Rn]; } /* LDC Rm,VBR */ -const void LDCVBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCVBR(const UINT16 opcode) { - sh4->vbr = sh4->r[Rn]; + m_vbr = m_r[Rn]; } /* LDC.L @Rm+,SR */ -const void LDCMSR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCMSR(const UINT16 opcode) { UINT32 old; - old = sh4->sr; - sh4->ea = sh4->r[Rn]; - sh4->sr = RL(sh4, sh4->ea ) & FLAGS; - if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) - sh4_syncronize_register_bank(sh4, (old & sRB) >> 29); - if ((old & sRB) != (sh4->sr & sRB)) - sh4_change_register_bank(sh4, sh4->sr & sRB ? 1 : 0); - sh4->r[Rn] += 4; - sh4->sh4_icount -= 2; - sh4_exception_recompute(sh4); + old = m_sr; + m_ea = m_r[Rn]; + m_sr = RL(m_ea ) & FLAGS; + if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + sh4_syncronize_register_bank((old & sRB) >> 29); + if ((old & sRB) != (m_sr & sRB)) + sh4_change_register_bank(m_sr & sRB ? 1 : 0); + m_r[Rn] += 4; + m_sh4_icount -= 2; + sh4_exception_recompute(); } /* LDC.L @Rm+,GBR */ -const void LDCMGBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCMGBR(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - sh4->gbr = RL(sh4, sh4->ea ); - sh4->r[Rn] += 4; - sh4->sh4_icount -= 2; + m_ea = m_r[Rn]; + m_gbr = RL(m_ea ); + m_r[Rn] += 4; + m_sh4_icount -= 2; } /* LDC.L @Rm+,VBR */ -const void LDCMVBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCMVBR(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - sh4->vbr = RL(sh4, sh4->ea ); - sh4->r[Rn] += 4; - sh4->sh4_icount -= 2; + m_ea = m_r[Rn]; + m_vbr = RL(m_ea ); + m_r[Rn] += 4; + m_sh4_icount -= 2; } /* LDS Rm,MACH */ -const void LDSMACH(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDSMACH(const UINT16 opcode) { - sh4->mach = sh4->r[Rn]; + m_mach = m_r[Rn]; } /* LDS Rm,MACL */ -const void LDSMACL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDSMACL(const UINT16 opcode) { - sh4->macl = sh4->r[Rn]; + m_macl = m_r[Rn]; } /* LDS Rm,PR */ -const void LDSPR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDSPR(const UINT16 opcode) { - sh4->pr = sh4->r[Rn]; + m_pr = m_r[Rn]; } /* LDS.L @Rm+,MACH */ -const void LDSMMACH(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDSMMACH(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - sh4->mach = RL(sh4, sh4->ea ); - sh4->r[Rn] += 4; + m_ea = m_r[Rn]; + m_mach = RL(m_ea ); + m_r[Rn] += 4; } /* LDS.L @Rm+,MACL */ -const void LDSMMACL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDSMMACL(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - sh4->macl = RL(sh4, sh4->ea ); - sh4->r[Rn] += 4; + m_ea = m_r[Rn]; + m_macl = RL(m_ea ); + m_r[Rn] += 4; } /* LDS.L @Rm+,PR */ -const void LDSMPR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDSMPR(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - sh4->pr = RL(sh4, sh4->ea ); - sh4->r[Rn] += 4; + m_ea = m_r[Rn]; + m_pr = RL(m_ea ); + m_r[Rn] += 4; } /* MAC.L @Rm+,@Rn+ */ -const void MAC_L(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MAC_L(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; @@ -934,10 +1038,10 @@ const void MAC_L(sh4_state *sh4, const UINT16 opcode) UINT32 temp0, temp1, temp2, temp3; INT32 tempm, tempn, fnLmL; - tempn = (INT32) RL(sh4, sh4->r[n] ); - sh4->r[n] += 4; - tempm = (INT32) RL(sh4, sh4->r[m] ); - sh4->r[m] += 4; + tempn = (INT32) RL(m_r[n] ); + m_r[n] += 4; + tempm = (INT32) RL(m_r[m] ); + m_r[m] += 4; if ((INT32) (tempn ^ tempm) < 0) fnLmL = -1; else @@ -973,12 +1077,12 @@ const void MAC_L(sh4_state *sh4, const UINT16 opcode) else Res0 = (~Res0) + 1; } - if (sh4->sr & S) + if (m_sr & S) { - Res0 = sh4->macl + Res0; - if (sh4->macl > Res0) + Res0 = m_macl + Res0; + if (m_macl > Res0) Res2++; - Res2 += (sh4->mach & 0x0000ffff); + Res2 += (m_mach & 0x0000ffff); if (((INT32) Res2 < 0) && (Res2 < 0xffff8000)) { Res2 = 0x00008000; @@ -989,36 +1093,36 @@ const void MAC_L(sh4_state *sh4, const UINT16 opcode) Res2 = 0x00007fff; Res0 = 0xffffffff; } - sh4->mach = Res2; - sh4->macl = Res0; + m_mach = Res2; + m_macl = Res0; } else { - Res0 = sh4->macl + Res0; - if (sh4->macl > Res0) + Res0 = m_macl + Res0; + if (m_macl > Res0) Res2++; - Res2 += sh4->mach; - sh4->mach = Res2; - sh4->macl = Res0; + Res2 += m_mach; + m_mach = Res2; + m_macl = Res0; } - sh4->sh4_icount -= 2; + m_sh4_icount -= 2; } /* MAC.W @Rm+,@Rn+ */ -const void MAC_W(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MAC_W(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; INT32 tempm, tempn, dest, src, ans; UINT32 templ; - tempn = (INT32) RW(sh4, sh4->r[n] ); - sh4->r[n] += 2; - tempm = (INT32) RW(sh4, sh4->r[m] ); - sh4->r[m] += 2; - templ = sh4->macl; + tempn = (INT32) RW(m_r[n] ); + m_r[n] += 2; + tempm = (INT32) RW(m_r[m] ); + m_r[m] += 2; + templ = m_macl; tempm = ((INT32) (short) tempn * (INT32) (short) tempm); - if ((INT32) sh4->macl >= 0) + if ((INT32) m_macl >= 0) dest = 0; else dest = 1; @@ -1033,684 +1137,684 @@ const void MAC_W(sh4_state *sh4, const UINT16 opcode) tempn = 0xffffffff; } src += dest; - sh4->macl += tempm; - if ((INT32) sh4->macl >= 0) + m_macl += tempm; + if ((INT32) m_macl >= 0) ans = 0; else ans = 1; ans += dest; - if (sh4->sr & S) + if (m_sr & S) { if (ans == 1) { if (src == 0) - sh4->macl = 0x7fffffff; + m_macl = 0x7fffffff; if (src == 2) - sh4->macl = 0x80000000; + m_macl = 0x80000000; } } else { - sh4->mach += tempn; - if (templ > sh4->macl) - sh4->mach += 1; + m_mach += tempn; + if (templ > m_macl) + m_mach += 1; } - sh4->sh4_icount -= 2; + m_sh4_icount -= 2; } /* MOV Rm,Rn */ -const void MOV(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOV(const UINT16 opcode) { - sh4->r[Rn] = sh4->r[Rm]; + m_r[Rn] = m_r[Rm]; } /* MOV.B Rm,@Rn */ -const void MOVBS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVBS(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - WB(sh4, sh4->ea, sh4->r[Rm] & 0x000000ff); + m_ea = m_r[Rn]; + WB(m_ea, m_r[Rm] & 0x000000ff); } /* MOV.W Rm,@Rn */ -const void MOVWS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWS(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - WW(sh4, sh4->ea, sh4->r[Rm] & 0x0000ffff); + m_ea = m_r[Rn]; + WW(m_ea, m_r[Rm] & 0x0000ffff); } /* MOV.L Rm,@Rn */ -const void MOVLS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLS(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - WL(sh4, sh4->ea, sh4->r[Rm] ); + m_ea = m_r[Rn]; + WL(m_ea, m_r[Rm] ); } /* MOV.B @Rm,Rn */ -const void MOVBL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVBL(const UINT16 opcode) { - sh4->ea = sh4->r[Rm]; - sh4->r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->ea ); + m_ea = m_r[Rm]; + m_r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea ); } /* MOV.W @Rm,Rn */ -const void MOVWL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWL(const UINT16 opcode) { - sh4->ea = sh4->r[Rm]; - sh4->r[Rn] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea ); + m_ea = m_r[Rm]; + m_r[Rn] = (UINT32)(INT32)(INT16) RW(m_ea ); } /* MOV.L @Rm,Rn */ -const void MOVLL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLL(const UINT16 opcode) { - sh4->ea = sh4->r[Rm]; - sh4->r[Rn] = RL(sh4, sh4->ea ); + m_ea = m_r[Rm]; + m_r[Rn] = RL(m_ea ); } /* MOV.B Rm,@-Rn */ -const void MOVBM(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVBM(const UINT16 opcode) { - UINT32 data = sh4->r[Rm] & 0x000000ff; + UINT32 data = m_r[Rm] & 0x000000ff; - sh4->r[Rn] -= 1; - WB(sh4, sh4->r[Rn], data ); + m_r[Rn] -= 1; + WB(m_r[Rn], data ); } /* MOV.W Rm,@-Rn */ -const void MOVWM(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWM(const UINT16 opcode) { - UINT32 data = sh4->r[Rm] & 0x0000ffff; + UINT32 data = m_r[Rm] & 0x0000ffff; - sh4->r[Rn] -= 2; - WW(sh4, sh4->r[Rn], data ); + m_r[Rn] -= 2; + WW(m_r[Rn], data ); } /* MOV.L Rm,@-Rn */ -const void MOVLM(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLM(const UINT16 opcode) { - UINT32 data = sh4->r[Rm]; + UINT32 data = m_r[Rm]; - sh4->r[Rn] -= 4; - WL(sh4, sh4->r[Rn], data ); + m_r[Rn] -= 4; + WL(m_r[Rn], data ); } /* MOV.B @Rm+,Rn */ -const void MOVBP(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVBP(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - sh4->r[n] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->r[m] ); + m_r[n] = (UINT32)(INT32)(INT16)(INT8) RB( m_r[m] ); if (n != m) - sh4->r[m] += 1; + m_r[m] += 1; } /* MOV.W @Rm+,Rn */ -const void MOVWP(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWP(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - sh4->r[n] = (UINT32)(INT32)(INT16) RW(sh4, sh4->r[m] ); + m_r[n] = (UINT32)(INT32)(INT16) RW(m_r[m] ); if (n != m) - sh4->r[m] += 2; + m_r[m] += 2; } /* MOV.L @Rm+,Rn */ -const void MOVLP(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLP(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - sh4->r[n] = RL(sh4, sh4->r[m] ); + m_r[n] = RL(m_r[m] ); if (n != m) - sh4->r[m] += 4; + m_r[m] += 4; } /* MOV.B Rm,@(R0,Rn) */ -const void MOVBS0(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVBS0(const UINT16 opcode) { - sh4->ea = sh4->r[Rn] + sh4->r[0]; - WB(sh4, sh4->ea, sh4->r[Rm] & 0x000000ff ); + m_ea = m_r[Rn] + m_r[0]; + WB(m_ea, m_r[Rm] & 0x000000ff ); } /* MOV.W Rm,@(R0,Rn) */ -const void MOVWS0(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWS0(const UINT16 opcode) { - sh4->ea = sh4->r[Rn] + sh4->r[0]; - WW(sh4, sh4->ea, sh4->r[Rm] & 0x0000ffff ); + m_ea = m_r[Rn] + m_r[0]; + WW(m_ea, m_r[Rm] & 0x0000ffff ); } /* MOV.L Rm,@(R0,Rn) */ -const void MOVLS0(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLS0(const UINT16 opcode) { - sh4->ea = sh4->r[Rn] + sh4->r[0]; - WL(sh4, sh4->ea, sh4->r[Rm] ); + m_ea = m_r[Rn] + m_r[0]; + WL(m_ea, m_r[Rm] ); } /* MOV.B @(R0,Rm),Rn */ -const void MOVBL0(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVBL0(const UINT16 opcode) { - sh4->ea = sh4->r[Rm] + sh4->r[0]; - sh4->r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->ea ); + m_ea = m_r[Rm] + m_r[0]; + m_r[Rn] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea ); } /* MOV.W @(R0,Rm),Rn */ -const void MOVWL0(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWL0(const UINT16 opcode) { - sh4->ea = sh4->r[Rm] + sh4->r[0]; - sh4->r[Rn] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea ); + m_ea = m_r[Rm] + m_r[0]; + m_r[Rn] = (UINT32)(INT32)(INT16) RW(m_ea ); } /* MOV.L @(R0,Rm),Rn */ -const void MOVLL0(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLL0(const UINT16 opcode) { - sh4->ea = sh4->r[Rm] + sh4->r[0]; - sh4->r[Rn] = RL(sh4, sh4->ea ); + m_ea = m_r[Rm] + m_r[0]; + m_r[Rn] = RL(m_ea ); } /* MOV #imm,Rn */ -const void MOVI(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVI(const UINT16 opcode) { - sh4->r[Rn] = (UINT32)(INT32)(INT16)(INT8)(opcode&0xff); + m_r[Rn] = (UINT32)(INT32)(INT16)(INT8)(opcode&0xff); } /* MOV.W @(disp8,PC),Rn */ -const void MOVWI(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWI(const UINT16 opcode) { UINT32 disp = opcode & 0xff; - sh4->ea = sh4->pc + disp * 2 + 2; - sh4->r[Rn] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea ); + m_ea = m_pc + disp * 2 + 2; + m_r[Rn] = (UINT32)(INT32)(INT16) RW(m_ea ); } /* MOV.L @(disp8,PC),Rn */ -const void MOVLI(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLI(const UINT16 opcode) { UINT32 disp = opcode & 0xff; - sh4->ea = ((sh4->pc + 2) & ~3) + disp * 4; - sh4->r[Rn] = RL(sh4, sh4->ea ); + m_ea = ((m_pc + 2) & ~3) + disp * 4; + m_r[Rn] = RL(m_ea ); } /* MOV.B @(disp8,GBR),R0 */ -const void MOVBLG(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVBLG(const UINT16 opcode) { UINT32 disp = opcode & 0xff; - sh4->ea = sh4->gbr + disp; - sh4->r[0] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->ea ); + m_ea = m_gbr + disp; + m_r[0] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea ); } /* MOV.W @(disp8,GBR),R0 */ -const void MOVWLG(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWLG(const UINT16 opcode) { UINT32 disp = opcode & 0xff; - sh4->ea = sh4->gbr + disp * 2; - sh4->r[0] = (INT32)(INT16) RW(sh4, sh4->ea ); + m_ea = m_gbr + disp * 2; + m_r[0] = (INT32)(INT16) RW(m_ea ); } /* MOV.L @(disp8,GBR),R0 */ -const void MOVLLG(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLLG(const UINT16 opcode) { UINT32 disp = opcode & 0xff; - sh4->ea = sh4->gbr + disp * 4; - sh4->r[0] = RL(sh4, sh4->ea ); + m_ea = m_gbr + disp * 4; + m_r[0] = RL(m_ea ); } /* MOV.B R0,@(disp8,GBR) */ -const void MOVBSG(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVBSG(const UINT16 opcode) { UINT32 disp = opcode & 0xff; - sh4->ea = sh4->gbr + disp; - WB(sh4, sh4->ea, sh4->r[0] & 0x000000ff ); + m_ea = m_gbr + disp; + WB(m_ea, m_r[0] & 0x000000ff ); } /* MOV.W R0,@(disp8,GBR) */ -const void MOVWSG(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWSG(const UINT16 opcode) { UINT32 disp = opcode & 0xff; - sh4->ea = sh4->gbr + disp * 2; - WW(sh4, sh4->ea, sh4->r[0] & 0x0000ffff ); + m_ea = m_gbr + disp * 2; + WW(m_ea, m_r[0] & 0x0000ffff ); } /* MOV.L R0,@(disp8,GBR) */ -const void MOVLSG(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLSG(const UINT16 opcode) { UINT32 disp = opcode & 0xff; - sh4->ea = sh4->gbr + disp * 4; - WL(sh4, sh4->ea, sh4->r[0] ); + m_ea = m_gbr + disp * 4; + WL(m_ea, m_r[0] ); } /* MOV.B R0,@(disp4,Rm) */ -const void MOVBS4(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVBS4(const UINT16 opcode) { UINT32 disp = opcode & 0x0f; - sh4->ea = sh4->r[Rm] + disp; - WB(sh4, sh4->ea, sh4->r[0] & 0x000000ff ); + m_ea = m_r[Rm] + disp; + WB(m_ea, m_r[0] & 0x000000ff ); } /* MOV.W R0,@(disp4,Rm) */ -const void MOVWS4(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWS4(const UINT16 opcode) { UINT32 disp = opcode & 0x0f; - sh4->ea = sh4->r[Rm] + disp * 2; - WW(sh4, sh4->ea, sh4->r[0] & 0x0000ffff ); + m_ea = m_r[Rm] + disp * 2; + WW(m_ea, m_r[0] & 0x0000ffff ); } /* MOV.L Rm,@(disp4,Rn) */ -const void MOVLS4(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLS4(const UINT16 opcode) { UINT32 disp = opcode & 0x0f; - sh4->ea = sh4->r[Rn] + disp * 4; - WL(sh4, sh4->ea, sh4->r[Rm] ); + m_ea = m_r[Rn] + disp * 4; + WL(m_ea, m_r[Rm] ); } /* MOV.B @(disp4,Rm),R0 */ -const void MOVBL4(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVBL4(const UINT16 opcode) { UINT32 disp = opcode & 0x0f; - sh4->ea = sh4->r[Rm] + disp; - sh4->r[0] = (UINT32)(INT32)(INT16)(INT8) RB(sh4, sh4->ea ); + m_ea = m_r[Rm] + disp; + m_r[0] = (UINT32)(INT32)(INT16)(INT8) RB( m_ea ); } /* MOV.W @(disp4,Rm),R0 */ -const void MOVWL4(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVWL4(const UINT16 opcode) { UINT32 disp = opcode & 0x0f; - sh4->ea = sh4->r[Rm] + disp * 2; - sh4->r[0] = (UINT32)(INT32)(INT16) RW(sh4, sh4->ea ); + m_ea = m_r[Rm] + disp * 2; + m_r[0] = (UINT32)(INT32)(INT16) RW(m_ea ); } /* MOV.L @(disp4,Rm),Rn */ -const void MOVLL4(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVLL4(const UINT16 opcode) { UINT32 disp = opcode & 0x0f; - sh4->ea = sh4->r[Rm] + disp * 4; - sh4->r[Rn] = RL(sh4, sh4->ea ); + m_ea = m_r[Rm] + disp * 4; + m_r[Rn] = RL(m_ea ); } /* MOVA @(disp8,PC),R0 */ -const void MOVA(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVA(const UINT16 opcode) { UINT32 disp = opcode & 0xff; - sh4->ea = ((sh4->pc + 2) & ~3) + disp * 4; - sh4->r[0] = sh4->ea; + m_ea = ((m_pc + 2) & ~3) + disp * 4; + m_r[0] = m_ea; } /* MOVT Rn */ -const void MOVT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVT(const UINT16 opcode) { - sh4->r[Rn] = sh4->sr & T; + m_r[Rn] = m_sr & T; } /* MUL.L Rm,Rn */ -const void MULL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MULL(const UINT16 opcode) { - sh4->macl = sh4->r[Rn] * sh4->r[Rm]; - sh4->sh4_icount--; + m_macl = m_r[Rn] * m_r[Rm]; + m_sh4_icount--; } /* MULS Rm,Rn */ -const void MULS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MULS(const UINT16 opcode) { - sh4->macl = (INT16) sh4->r[Rn] * (INT16) sh4->r[Rm]; + m_macl = (INT16) m_r[Rn] * (INT16) m_r[Rm]; } /* MULU Rm,Rn */ -const void MULU(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MULU(const UINT16 opcode) { - sh4->macl = (UINT16) sh4->r[Rn] * (UINT16) sh4->r[Rm]; + m_macl = (UINT16) m_r[Rn] * (UINT16) m_r[Rm]; } /* NEG Rm,Rn */ -const void NEG(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::NEG(const UINT16 opcode) { - sh4->r[Rn] = 0 - sh4->r[Rm]; + m_r[Rn] = 0 - m_r[Rm]; } /* NEGC Rm,Rn */ -const void NEGC(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::NEGC(const UINT16 opcode) { UINT32 temp; - temp = sh4->r[Rm]; - sh4->r[Rn] = -temp - (sh4->sr & T); - if (temp || (sh4->sr & T)) - sh4->sr |= T; + temp = m_r[Rm]; + m_r[Rn] = -temp - (m_sr & T); + if (temp || (m_sr & T)) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* NOP */ -const void NOP(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::NOP(const UINT16 opcode) { } /* NOT Rm,Rn */ -const void NOT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::NOT(const UINT16 opcode) { - sh4->r[Rn] = ~sh4->r[Rm]; + m_r[Rn] = ~m_r[Rm]; } /* OR Rm,Rn */ -const void OR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::OR(const UINT16 opcode) { - sh4->r[Rn] |= sh4->r[Rm]; + m_r[Rn] |= m_r[Rm]; } /* OR #imm,R0 */ -const void ORI(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ORI(const UINT16 opcode) { - sh4->r[0] |= (opcode&0xff); - sh4->sh4_icount -= 2; + m_r[0] |= (opcode&0xff); + m_sh4_icount -= 2; } /* OR.B #imm,@(R0,GBR) */ -const void ORM(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ORM(const UINT16 opcode) { UINT32 temp; - sh4->ea = sh4->gbr + sh4->r[0]; - temp = RB(sh4, sh4->ea ); + m_ea = m_gbr + m_r[0]; + temp = RB( m_ea ); temp |= (opcode&0xff); - WB(sh4, sh4->ea, temp ); + WB(m_ea, temp ); } /* ROTCL Rn */ -const void ROTCL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ROTCL(const UINT16 opcode) { UINT32 n = Rn; UINT32 temp; - temp = (sh4->r[n] >> 31) & T; - sh4->r[n] = (sh4->r[n] << 1) | (sh4->sr & T); - sh4->sr = (sh4->sr & ~T) | temp; + temp = (m_r[n] >> 31) & T; + m_r[n] = (m_r[n] << 1) | (m_sr & T); + m_sr = (m_sr & ~T) | temp; } /* ROTCR Rn */ -const void ROTCR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ROTCR(const UINT16 opcode) { UINT32 n = Rn; UINT32 temp; - temp = (sh4->sr & T) << 31; - if (sh4->r[n] & T) - sh4->sr |= T; + temp = (m_sr & T) << 31; + if (m_r[n] & T) + m_sr |= T; else - sh4->sr &= ~T; - sh4->r[n] = (sh4->r[n] >> 1) | temp; + m_sr &= ~T; + m_r[n] = (m_r[n] >> 1) | temp; } /* ROTL Rn */ -const void ROTL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ROTL(const UINT16 opcode) { UINT32 n = Rn; - sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T); - sh4->r[n] = (sh4->r[n] << 1) | (sh4->r[n] >> 31); + m_sr = (m_sr & ~T) | ((m_r[n] >> 31) & T); + m_r[n] = (m_r[n] << 1) | (m_r[n] >> 31); } /* ROTR Rn */ -const void ROTR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::ROTR(const UINT16 opcode) { UINT32 n = Rn; - sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T); - sh4->r[n] = (sh4->r[n] >> 1) | (sh4->r[n] << 31); + m_sr = (m_sr & ~T) | (m_r[n] & T); + m_r[n] = (m_r[n] >> 1) | (m_r[n] << 31); } /* RTE */ -const void RTE(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::RTE(const UINT16 opcode) { - sh4->delay = sh4->pc; - sh4->pc = sh4->ea = sh4->spc; - if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) - sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29); - if ((sh4->ssr & sRB) != (sh4->sr & sRB)) - sh4_change_register_bank(sh4, sh4->ssr & sRB ? 1 : 0); - sh4->sr = sh4->ssr; - sh4->sh4_icount--; - sh4_exception_recompute(sh4); + m_delay = m_pc; + m_pc = m_ea = m_spc; + if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + sh4_syncronize_register_bank((m_sr & sRB) >> 29); + if ((m_ssr & sRB) != (m_sr & sRB)) + sh4_change_register_bank(m_ssr & sRB ? 1 : 0); + m_sr = m_ssr; + m_sh4_icount--; + sh4_exception_recompute(); } /* RTS */ -const void RTS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::RTS(const UINT16 opcode) { - sh4->delay = sh4->pc; - sh4->pc = sh4->ea = sh4->pr; - sh4->sh4_icount--; + m_delay = m_pc; + m_pc = m_ea = m_pr; + m_sh4_icount--; } /* SETT */ -const void SETT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SETT(const UINT16 opcode) { - sh4->sr |= T; + m_sr |= T; } /* SHAL Rn (same as SHLL) */ -const void SHAL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHAL(const UINT16 opcode) { UINT32 n = Rn; - sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T); - sh4->r[n] <<= 1; + m_sr = (m_sr & ~T) | ((m_r[n] >> 31) & T); + m_r[n] <<= 1; } /* SHAR Rn */ -const void SHAR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHAR(const UINT16 opcode) { UINT32 n = Rn; - sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T); - sh4->r[n] = (UINT32)((INT32)sh4->r[n] >> 1); + m_sr = (m_sr & ~T) | (m_r[n] & T); + m_r[n] = (UINT32)((INT32)m_r[n] >> 1); } /* SHLL Rn (same as SHAL) */ -const void SHLL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHLL(const UINT16 opcode) { UINT32 n = Rn; - sh4->sr = (sh4->sr & ~T) | ((sh4->r[n] >> 31) & T); - sh4->r[n] <<= 1; + m_sr = (m_sr & ~T) | ((m_r[n] >> 31) & T); + m_r[n] <<= 1; } /* SHLL2 Rn */ -const void SHLL2(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHLL2(const UINT16 opcode) { - sh4->r[Rn] <<= 2; + m_r[Rn] <<= 2; } /* SHLL8 Rn */ -const void SHLL8(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHLL8(const UINT16 opcode) { - sh4->r[Rn] <<= 8; + m_r[Rn] <<= 8; } /* SHLL16 Rn */ -const void SHLL16(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHLL16(const UINT16 opcode) { - sh4->r[Rn] <<= 16; + m_r[Rn] <<= 16; } /* SHLR Rn */ -const void SHLR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHLR(const UINT16 opcode) { UINT32 n = Rn; - sh4->sr = (sh4->sr & ~T) | (sh4->r[n] & T); - sh4->r[n] >>= 1; + m_sr = (m_sr & ~T) | (m_r[n] & T); + m_r[n] >>= 1; } /* SHLR2 Rn */ -const void SHLR2(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHLR2(const UINT16 opcode) { - sh4->r[Rn] >>= 2; + m_r[Rn] >>= 2; } /* SHLR8 Rn */ -const void SHLR8(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHLR8(const UINT16 opcode) { - sh4->r[Rn] >>= 8; + m_r[Rn] >>= 8; } /* SHLR16 Rn */ -const void SHLR16(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHLR16(const UINT16 opcode) { - sh4->r[Rn] >>= 16; + m_r[Rn] >>= 16; } /* SLEEP */ -const void SLEEP(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SLEEP(const UINT16 opcode) { /* 0 = normal mode */ /* 1 = enters into power-down mode */ /* 2 = go out the power-down mode after an exception */ - if(sh4->sleep_mode != 2) - sh4->pc -= 2; - sh4->sh4_icount -= 2; + if(m_sleep_mode != 2) + m_pc -= 2; + m_sh4_icount -= 2; /* Wait_for_exception; */ - if(sh4->sleep_mode == 0) - sh4->sleep_mode = 1; - else if(sh4->sleep_mode == 2) - sh4->sleep_mode = 0; + if(m_sleep_mode == 0) + m_sleep_mode = 1; + else if(m_sleep_mode == 2) + m_sleep_mode = 0; } /* STC SR,Rn */ -const void STCSR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCSR(const UINT16 opcode) { - sh4->r[Rn] = sh4->sr; + m_r[Rn] = m_sr; } /* STC GBR,Rn */ -const void STCGBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCGBR(const UINT16 opcode) { - sh4->r[Rn] = sh4->gbr; + m_r[Rn] = m_gbr; } /* STC VBR,Rn */ -const void STCVBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCVBR(const UINT16 opcode) { - sh4->r[Rn] = sh4->vbr; + m_r[Rn] = m_vbr; } /* STC.L SR,@-Rn */ -const void STCMSR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCMSR(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->sr ); - sh4->sh4_icount--; + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_sr ); + m_sh4_icount--; } /* STC.L GBR,@-Rn */ -const void STCMGBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCMGBR(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->gbr ); - sh4->sh4_icount--; + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_gbr ); + m_sh4_icount--; } /* STC.L VBR,@-Rn */ -const void STCMVBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCMVBR(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->vbr ); - sh4->sh4_icount--; + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_vbr ); + m_sh4_icount--; } /* STS MACH,Rn */ -const void STSMACH(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STSMACH(const UINT16 opcode) { - sh4->r[Rn] = sh4->mach; + m_r[Rn] = m_mach; } /* STS MACL,Rn */ -const void STSMACL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STSMACL(const UINT16 opcode) { - sh4->r[Rn] = sh4->macl; + m_r[Rn] = m_macl; } /* STS PR,Rn */ -const void STSPR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STSPR(const UINT16 opcode) { - sh4->r[Rn] = sh4->pr; + m_r[Rn] = m_pr; } /* STS.L MACH,@-Rn */ -const void STSMMACH(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STSMMACH(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->mach ); + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_mach ); } /* STS.L MACL,@-Rn */ -const void STSMMACL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STSMMACL(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->macl ); + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_macl ); } /* STS.L PR,@-Rn */ -const void STSMPR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STSMPR(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->pr ); + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_pr ); } /* SUB Rm,Rn */ -const void SUB(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SUB(const UINT16 opcode) { - sh4->r[Rn] -= sh4->r[Rm]; + m_r[Rn] -= m_r[Rm]; } /* SUBC Rm,Rn */ -const void SUBC(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SUBC(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; UINT32 tmp0, tmp1; - tmp1 = sh4->r[n] - sh4->r[m]; - tmp0 = sh4->r[n]; - sh4->r[n] = tmp1 - (sh4->sr & T); + tmp1 = m_r[n] - m_r[m]; + tmp0 = m_r[n]; + m_r[n] = tmp1 - (m_sr & T); if (tmp0 < tmp1) - sh4->sr |= T; + m_sr |= T; else - sh4->sr &= ~T; - if (tmp1 < sh4->r[n]) - sh4->sr |= T; + m_sr &= ~T; + if (tmp1 < m_r[n]) + m_sr |= T; } /* SUBV Rm,Rn */ -const void SUBV(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SUBV(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; INT32 dest, src, ans; - if ((INT32) sh4->r[n] >= 0) + if ((INT32) m_r[n] >= 0) dest = 0; else dest = 1; - if ((INT32) sh4->r[m] >= 0) + if ((INT32) m_r[m] >= 0) src = 0; else src = 1; src += dest; - sh4->r[n] -= sh4->r[m]; - if ((INT32) sh4->r[n] >= 0) + m_r[n] -= m_r[m]; + if ((INT32) m_r[n] >= 0) ans = 0; else ans = 1; @@ -1718,455 +1822,455 @@ const void SUBV(sh4_state *sh4, const UINT16 opcode) if (src == 1) { if (ans == 1) - sh4->sr |= T; + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } else - sh4->sr &= ~T; + m_sr &= ~T; } /* SWAP.B Rm,Rn */ -const void SWAPB(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SWAPB(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; UINT32 temp0, temp1; - temp0 = sh4->r[m] & 0xffff0000; - temp1 = (sh4->r[m] & 0x000000ff) << 8; - sh4->r[n] = (sh4->r[m] >> 8) & 0x000000ff; - sh4->r[n] = sh4->r[n] | temp1 | temp0; + temp0 = m_r[m] & 0xffff0000; + temp1 = (m_r[m] & 0x000000ff) << 8; + m_r[n] = (m_r[m] >> 8) & 0x000000ff; + m_r[n] = m_r[n] | temp1 | temp0; } /* SWAP.W Rm,Rn */ -const void SWAPW(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SWAPW(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; UINT32 temp; - temp = (sh4->r[m] >> 16) & 0x0000ffff; - sh4->r[n] = (sh4->r[m] << 16) | temp; + temp = (m_r[m] >> 16) & 0x0000ffff; + m_r[n] = (m_r[m] << 16) | temp; } /* TAS.B @Rn */ -const void TAS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::TAS(const UINT16 opcode) { UINT32 n = Rn; UINT32 temp; - sh4->ea = sh4->r[n]; + m_ea = m_r[n]; /* Bus Lock enable */ - temp = RB(sh4, sh4->ea ); + temp = RB( m_ea ); if (temp == 0) - sh4->sr |= T; + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; temp |= 0x80; /* Bus Lock disable */ - WB(sh4, sh4->ea, temp ); - sh4->sh4_icount -= 3; + WB(m_ea, temp ); + m_sh4_icount -= 3; } /* TRAPA #imm */ -const void TRAPA(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::TRAPA(const UINT16 opcode) { UINT32 imm = opcode & 0xff; - if (sh4->cpu_type == CPU_TYPE_SH4) + if (m_cpu_type == CPU_TYPE_SH4) { - sh4->m[TRA] = imm << 2; + m_m[TRA] = imm << 2; } else /* SH3 */ { - sh4->m_sh3internal_upper[SH3_TRA_ADDR] = imm << 2; + m_sh3internal_upper[SH3_TRA_ADDR] = imm << 2; } - sh4->ssr = sh4->sr; - sh4->spc = sh4->pc; - sh4->sgr = sh4->r[15]; + m_ssr = m_sr; + m_spc = m_pc; + m_sgr = m_r[15]; - sh4->sr |= MD; - if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) - sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29); - if (!(sh4->sr & sRB)) - sh4_change_register_bank(sh4, 1); - sh4->sr |= sRB; - sh4->sr |= BL; - sh4_exception_recompute(sh4); + m_sr |= MD; + if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + sh4_syncronize_register_bank((m_sr & sRB) >> 29); + if (!(m_sr & sRB)) + sh4_change_register_bank(1); + m_sr |= sRB; + m_sr |= BL; + sh4_exception_recompute(); - if (sh4->cpu_type == CPU_TYPE_SH4) + if (m_cpu_type == CPU_TYPE_SH4) { - sh4->m[EXPEVT] = 0x00000160; + m_m[EXPEVT] = 0x00000160; } else /* SH3 */ { - sh4->m_sh3internal_upper[SH3_EXPEVT_ADDR] = 0x00000160; + m_sh3internal_upper[SH3_EXPEVT_ADDR] = 0x00000160; } - sh4->pc = sh4->vbr + 0x00000100; + m_pc = m_vbr + 0x00000100; - sh4->sh4_icount -= 7; + m_sh4_icount -= 7; } /* TST Rm,Rn */ -const void TST(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::TST(const UINT16 opcode) { - if ((sh4->r[Rn] & sh4->r[Rm]) == 0) - sh4->sr |= T; + if ((m_r[Rn] & m_r[Rm]) == 0) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* TST #imm,R0 */ -const void TSTI(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::TSTI(const UINT16 opcode) { UINT32 imm = opcode & 0xff; - if ((imm & sh4->r[0]) == 0) - sh4->sr |= T; + if ((imm & m_r[0]) == 0) + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } /* TST.B #imm,@(R0,GBR) */ -const void TSTM(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::TSTM(const UINT16 opcode) { UINT32 imm = opcode & 0xff; - sh4->ea = sh4->gbr + sh4->r[0]; - if ((imm & RB(sh4, sh4->ea )) == 0) - sh4->sr |= T; + m_ea = m_gbr + m_r[0]; + if ((imm & RB( m_ea )) == 0) + m_sr |= T; else - sh4->sr &= ~T; - sh4->sh4_icount -= 2; + m_sr &= ~T; + m_sh4_icount -= 2; } /* XOR Rm,Rn */ -const void XOR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::XOR(const UINT16 opcode) { - sh4->r[Rn] ^= sh4->r[Rm]; + m_r[Rn] ^= m_r[Rm]; } /* XOR #imm,R0 */ -const void XORI(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::XORI(const UINT16 opcode) { UINT32 imm = opcode & 0xff; - sh4->r[0] ^= imm; + m_r[0] ^= imm; } /* XOR.B #imm,@(R0,GBR) */ -const void XORM(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::XORM(const UINT16 opcode) { UINT32 imm = opcode & 0xff; UINT32 temp; - sh4->ea = sh4->gbr + sh4->r[0]; - temp = RB(sh4, sh4->ea ); + m_ea = m_gbr + m_r[0]; + temp = RB( m_ea ); temp ^= imm; - WB(sh4, sh4->ea, temp ); - sh4->sh4_icount -= 2; + WB(m_ea, temp ); + m_sh4_icount -= 2; } /* XTRCT Rm,Rn */ -const void XTRCT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::XTRCT(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; UINT32 temp; - temp = (sh4->r[m] << 16) & 0xffff0000; - sh4->r[n] = (sh4->r[n] >> 16) & 0x0000ffff; - sh4->r[n] |= temp; + temp = (m_r[m] << 16) & 0xffff0000; + m_r[n] = (m_r[n] >> 16) & 0x0000ffff; + m_r[n] |= temp; } /* STC SSR,Rn */ -const void STCSSR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCSSR(const UINT16 opcode) { - sh4->r[Rn] = sh4->ssr; + m_r[Rn] = m_ssr; } /* STC SPC,Rn */ -const void STCSPC(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCSPC(const UINT16 opcode) { - sh4->r[Rn] = sh4->spc; + m_r[Rn] = m_spc; } /* STC SGR,Rn */ -const void STCSGR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCSGR(const UINT16 opcode) { - sh4->r[Rn] = sh4->sgr; + m_r[Rn] = m_sgr; } /* STS FPUL,Rn */ -const void STSFPUL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STSFPUL(const UINT16 opcode) { - sh4->r[Rn] = sh4->fpul; + m_r[Rn] = m_fpul; } /* STS FPSCR,Rn */ -const void STSFPSCR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STSFPSCR(const UINT16 opcode) { - sh4->r[Rn] = sh4->fpscr & 0x003FFFFF; + m_r[Rn] = m_fpscr & 0x003FFFFF; } /* STC DBR,Rn */ -const void STCDBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCDBR(const UINT16 opcode) { - sh4->r[Rn] = sh4->dbr; + m_r[Rn] = m_dbr; } /* STCRBANK Rm_BANK,Rn */ -const void STCRBANK(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCRBANK(const UINT16 opcode) { UINT32 m = Rm; - sh4->r[Rn] = sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7]; + m_r[Rn] = m_rbnk[m_sr&sRB ? 0 : 1][m & 7]; } /* STCMRBANK Rm_BANK,@-Rn */ -const void STCMRBANK(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCMRBANK(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7]); - sh4->sh4_icount--; + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_rbnk[m_sr&sRB ? 0 : 1][m & 7]); + m_sh4_icount--; } /* MOVCA.L R0,@Rn */ -const void MOVCAL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::MOVCAL(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - WL(sh4, sh4->ea, sh4->r[0] ); + m_ea = m_r[Rn]; + WL(m_ea, m_r[0] ); } -const void CLRS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::CLRS(const UINT16 opcode) { - sh4->sr &= ~S; + m_sr &= ~S; } -const void SETS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SETS(const UINT16 opcode) { - sh4->sr |= S; + m_sr |= S; } /* STS.L SGR,@-Rn */ -const void STCMSGR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCMSGR(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->sgr ); + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_sgr ); } /* STS.L FPUL,@-Rn */ -const void STSMFPUL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STSMFPUL(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->fpul ); + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_fpul ); } /* STS.L FPSCR,@-Rn */ -const void STSMFPSCR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STSMFPSCR(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->fpscr & 0x003FFFFF); + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_fpscr & 0x003FFFFF); } /* STC.L DBR,@-Rn */ -const void STCMDBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCMDBR(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->dbr ); + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_dbr ); } /* STC.L SSR,@-Rn */ -const void STCMSSR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCMSSR(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->ssr ); + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_ssr ); } /* STC.L SPC,@-Rn */ -const void STCMSPC(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::STCMSPC(const UINT16 opcode) { UINT32 n = Rn; - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea, sh4->spc ); + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea, m_spc ); } /* LDS.L @Rm+,FPUL */ -const void LDSMFPUL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDSMFPUL(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - sh4->fpul = RL(sh4, sh4->ea ); - sh4->r[Rn] += 4; + m_ea = m_r[Rn]; + m_fpul = RL(m_ea ); + m_r[Rn] += 4; } /* LDS.L @Rm+,FPSCR */ -const void LDSMFPSCR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDSMFPSCR(const UINT16 opcode) { UINT32 s; - s = sh4->fpscr; - sh4->ea = sh4->r[Rn]; - sh4->fpscr = RL(sh4, sh4->ea ); - sh4->fpscr &= 0x003FFFFF; - sh4->r[Rn] += 4; - if ((s & FR) != (sh4->fpscr & FR)) - sh4_swap_fp_registers(sh4); + s = m_fpscr; + m_ea = m_r[Rn]; + m_fpscr = RL(m_ea ); + m_fpscr &= 0x003FFFFF; + m_r[Rn] += 4; + if ((s & FR) != (m_fpscr & FR)) + sh4_swap_fp_registers(); #ifdef LSB_FIRST - if ((s & PR) != (sh4->fpscr & PR)) - sh4_swap_fp_couples(sh4); + if ((s & PR) != (m_fpscr & PR)) + sh4_swap_fp_couples(); #endif - sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0; - sh4->fpu_pr = (sh4->fpscr & PR) ? 1 : 0; + m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; + m_fpu_pr = (m_fpscr & PR) ? 1 : 0; } /* LDC.L @Rm+,DBR */ -const void LDCMDBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCMDBR(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - sh4->dbr = RL(sh4, sh4->ea ); - sh4->r[Rn] += 4; + m_ea = m_r[Rn]; + m_dbr = RL(m_ea ); + m_r[Rn] += 4; } /* LDC.L @Rn+,Rm_BANK */ -const void LDCMRBANK(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCMRBANK(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - sh4->ea = sh4->r[n]; - sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7] = RL(sh4, sh4->ea ); - sh4->r[n] += 4; + m_ea = m_r[n]; + m_rbnk[m_sr&sRB ? 0 : 1][m & 7] = RL(m_ea ); + m_r[n] += 4; } /* LDC.L @Rm+,SSR */ -const void LDCMSSR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCMSSR(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - sh4->ssr = RL(sh4, sh4->ea ); - sh4->r[Rn] += 4; + m_ea = m_r[Rn]; + m_ssr = RL(m_ea ); + m_r[Rn] += 4; } /* LDC.L @Rm+,SPC */ -const void LDCMSPC(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCMSPC(const UINT16 opcode) { - sh4->ea = sh4->r[Rn]; - sh4->spc = RL(sh4, sh4->ea ); - sh4->r[Rn] += 4; + m_ea = m_r[Rn]; + m_spc = RL(m_ea ); + m_r[Rn] += 4; } /* LDS Rm,FPUL */ -const void LDSFPUL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDSFPUL(const UINT16 opcode) { - sh4->fpul = sh4->r[Rn]; + m_fpul = m_r[Rn]; } /* LDS Rm,FPSCR */ -const void LDSFPSCR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDSFPSCR(const UINT16 opcode) { UINT32 s; - s = sh4->fpscr; - sh4->fpscr = sh4->r[Rn] & 0x003FFFFF; - if ((s & FR) != (sh4->fpscr & FR)) - sh4_swap_fp_registers(sh4); + s = m_fpscr; + m_fpscr = m_r[Rn] & 0x003FFFFF; + if ((s & FR) != (m_fpscr & FR)) + sh4_swap_fp_registers(); #ifdef LSB_FIRST - if ((s & PR) != (sh4->fpscr & PR)) - sh4_swap_fp_couples(sh4); + if ((s & PR) != (m_fpscr & PR)) + sh4_swap_fp_couples(); #endif - sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0; - sh4->fpu_pr = (sh4->fpscr & PR) ? 1 : 0; + m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; + m_fpu_pr = (m_fpscr & PR) ? 1 : 0; } /* LDC Rm,DBR */ -const void LDCDBR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCDBR(const UINT16 opcode) { - sh4->dbr = sh4->r[Rn]; + m_dbr = m_r[Rn]; } /* SHAD Rm,Rn */ -const void SHAD(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHAD(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if ((sh4->r[m] & 0x80000000) == 0) - sh4->r[n] = sh4->r[n] << (sh4->r[m] & 0x1F); - else if ((sh4->r[m] & 0x1F) == 0) { - if ((sh4->r[n] & 0x80000000) == 0) - sh4->r[n] = 0; + if ((m_r[m] & 0x80000000) == 0) + m_r[n] = m_r[n] << (m_r[m] & 0x1F); + else if ((m_r[m] & 0x1F) == 0) { + if ((m_r[n] & 0x80000000) == 0) + m_r[n] = 0; else - sh4->r[n] = 0xFFFFFFFF; + m_r[n] = 0xFFFFFFFF; } else - sh4->r[n]=(INT32)sh4->r[n] >> ((~sh4->r[m] & 0x1F)+1); + m_r[n]=(INT32)m_r[n] >> ((~m_r[m] & 0x1F)+1); } /* SHLD Rm,Rn */ -const void SHLD(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::SHLD(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if ((sh4->r[m] & 0x80000000) == 0) - sh4->r[n] = sh4->r[n] << (sh4->r[m] & 0x1F); - else if ((sh4->r[m] & 0x1F) == 0) - sh4->r[n] = 0; + if ((m_r[m] & 0x80000000) == 0) + m_r[n] = m_r[n] << (m_r[m] & 0x1F); + else if ((m_r[m] & 0x1F) == 0) + m_r[n] = 0; else - sh4->r[n] = sh4->r[n] >> ((~sh4->r[m] & 0x1F)+1); + m_r[n] = m_r[n] >> ((~m_r[m] & 0x1F)+1); } /* LDCRBANK Rn,Rm_BANK */ -const void LDCRBANK(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCRBANK(const UINT16 opcode) { UINT32 m = Rm; - sh4->rbnk[sh4->sr&sRB ? 0 : 1][m & 7] = sh4->r[Rn]; + m_rbnk[m_sr&sRB ? 0 : 1][m & 7] = m_r[Rn]; } /* LDC Rm,SSR */ -const void LDCSSR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCSSR(const UINT16 opcode) { - sh4->ssr = sh4->r[Rn]; + m_ssr = m_r[Rn]; } /* LDC Rm,SPC */ -const void LDCSPC(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::LDCSPC(const UINT16 opcode) { - sh4->spc = sh4->r[Rn]; + m_spc = m_r[Rn]; } /* PREF @Rn */ -const void PREFM(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::PREFM(const UINT16 opcode) { int a; UINT32 addr,dest,sq; - addr = sh4->r[Rn]; // address + addr = m_r[Rn]; // address if ((addr >= 0xE0000000) && (addr <= 0xE3FFFFFF)) { - if (sh4->sh4_mmu_enabled) + if (m_sh4_mmu_enabled) { addr = addr & 0xFFFFFFE0; - dest = sh4_getsqremap(sh4, addr); // good enough for naomi-gd rom, probably not much else + dest = sh4_getsqremap(addr); // good enough for naomi-gd rom, probably not much else } else @@ -2175,24 +2279,24 @@ const void PREFM(sh4_state *sh4, const UINT16 opcode) dest = addr & 0x03FFFFE0; if (sq == 0) { - if (sh4->cpu_type == CPU_TYPE_SH4) + if (m_cpu_type == CPU_TYPE_SH4) { - dest |= (sh4->m[QACR0] & 0x1C) << 24; + dest |= (m_m[QACR0] & 0x1C) << 24; } else { - fatalerror("sh4->cpu_type != CPU_TYPE_SH4 but access internal regs\n"); + fatalerror("m_cpu_type != CPU_TYPE_SH4 but access internal regs\n"); } } else { - if (sh4->cpu_type == CPU_TYPE_SH4) + if (m_cpu_type == CPU_TYPE_SH4) { - dest |= (sh4->m[QACR1] & 0x1C) << 24; + dest |= (m_m[QACR1] & 0x1C) << 24; } else { - fatalerror("sh4->cpu_type != CPU_TYPE_SH4 but access internal regs\n"); + fatalerror("m_cpu_type != CPU_TYPE_SH4 but access internal regs\n"); } } @@ -2202,7 +2306,7 @@ const void PREFM(sh4_state *sh4, const UINT16 opcode) for (a = 0;a < 4;a++) { // shouldn't be causing a memory read, should store sq writes in registers. - sh4->program->write_qword(dest, sh4->program->read_qword(addr)); + m_program->write_qword(dest, m_program->read_qword(addr)); addr += 8; dest += 8; } @@ -2233,36 +2337,36 @@ const void PREFM(sh4_state *sh4, const UINT16 opcode) /* FMOV @Rm+,DRn PR=0 SZ=1 1111nnn0mmmm1001 */ /* FMOV @Rm+,XDn PR=0 SZ=1 1111nnn1mmmm1001 */ /* FMOV @Rm+,XDn PR=1 1111nnn1mmmm1001 */ -const void FMOVMRIFR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FMOVMRIFR(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n = n & 14; - sh4->ea = sh4->r[m]; - sh4->r[m] += 8; - sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(sh4, sh4->ea ); - sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(sh4, sh4->ea+4 ); + m_ea = m_r[m]; + m_r[m] += 8; + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea ); + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 ); } else { /* PR = 0 */ - if (sh4->fpu_sz) { /* SZ = 1 */ + if (m_fpu_sz) { /* SZ = 1 */ if (n & 1) { n = n & 14; - sh4->ea = sh4->r[m]; - sh4->xf[n] = RL(sh4, sh4->ea ); - sh4->r[m] += 4; - sh4->xf[n+1] = RL(sh4, sh4->ea+4 ); - sh4->r[m] += 4; + m_ea = m_r[m]; + m_xf[n] = RL(m_ea ); + m_r[m] += 4; + m_xf[n+1] = RL(m_ea+4 ); + m_r[m] += 4; } else { - sh4->ea = sh4->r[m]; - sh4->fr[n] = RL(sh4, sh4->ea ); - sh4->r[m] += 4; - sh4->fr[n+1] = RL(sh4, sh4->ea+4 ); - sh4->r[m] += 4; + m_ea = m_r[m]; + m_fr[n] = RL(m_ea ); + m_r[m] += 4; + m_fr[n+1] = RL(m_ea+4 ); + m_r[m] += 4; } } else { /* SZ = 0 */ - sh4->ea = sh4->r[m]; - sh4->fr[n] = RL(sh4, sh4->ea ); - sh4->r[m] += 4; + m_ea = m_r[m]; + m_fr[n] = RL(m_ea ); + m_r[m] += 4; } } } @@ -2271,30 +2375,30 @@ const void FMOVMRIFR(sh4_state *sh4, const UINT16 opcode) /* FMOV DRm,@Rn PR=0 SZ=1 1111nnnnmmm01010 */ /* FMOV XDm,@Rn PR=0 SZ=1 1111nnnnmmm11010 */ /* FMOV XDm,@Rn PR=1 1111nnnnmmm11010 */ -const void FMOVFRMR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FMOVFRMR(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ m= m & 14; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] ); - WL(sh4, sh4->ea+4,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] ); + m_ea = m_r[n]; + WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] ); + WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] ); } else { /* PR = 0 */ - if (sh4->fpu_sz) { /* SZ = 1 */ + if (m_fpu_sz) { /* SZ = 1 */ if (m & 1) { m= m & 14; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea,sh4->xf[m] ); - WL(sh4, sh4->ea+4,sh4->xf[m+1] ); + m_ea = m_r[n]; + WL(m_ea,m_xf[m] ); + WL(m_ea+4,m_xf[m+1] ); } else { - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea,sh4->fr[m] ); - WL(sh4, sh4->ea+4,sh4->fr[m+1] ); + m_ea = m_r[n]; + WL(m_ea,m_fr[m] ); + WL(m_ea+4,m_fr[m+1] ); } } else { /* SZ = 0 */ - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea,sh4->fr[m] ); + m_ea = m_r[n]; + WL(m_ea,m_fr[m] ); } } } @@ -2303,34 +2407,34 @@ const void FMOVFRMR(sh4_state *sh4, const UINT16 opcode) /* FMOV DRm,@-Rn PR=0 SZ=1 1111nnnnmmm01011 */ /* FMOV XDm,@-Rn PR=0 SZ=1 1111nnnnmmm11011 */ /* FMOV XDm,@-Rn PR=1 1111nnnnmmm11011 */ -const void FMOVFRMDR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FMOVFRMDR(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ m= m & 14; - sh4->r[n] -= 8; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] ); - WL(sh4, sh4->ea+4,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] ); + m_r[n] -= 8; + m_ea = m_r[n]; + WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] ); + WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] ); } else { /* PR = 0 */ - if (sh4->fpu_sz) { /* SZ = 1 */ + if (m_fpu_sz) { /* SZ = 1 */ if (m & 1) { m= m & 14; - sh4->r[n] -= 8; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea,sh4->xf[m] ); - WL(sh4, sh4->ea+4,sh4->xf[m+1] ); + m_r[n] -= 8; + m_ea = m_r[n]; + WL(m_ea,m_xf[m] ); + WL(m_ea+4,m_xf[m+1] ); } else { - sh4->r[n] -= 8; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea,sh4->fr[m] ); - WL(sh4, sh4->ea+4,sh4->fr[m+1] ); + m_r[n] -= 8; + m_ea = m_r[n]; + WL(m_ea,m_fr[m] ); + WL(m_ea+4,m_fr[m+1] ); } } else { /* SZ = 0 */ - sh4->r[n] -= 4; - sh4->ea = sh4->r[n]; - WL(sh4, sh4->ea,sh4->fr[m] ); + m_r[n] -= 4; + m_ea = m_r[n]; + WL(m_ea,m_fr[m] ); } } } @@ -2339,30 +2443,30 @@ const void FMOVFRMDR(sh4_state *sh4, const UINT16 opcode) /* FMOV DRm,@(R0,Rn) PR=0 SZ=1 1111nnnnmmm00111 */ /* FMOV XDm,@(R0,Rn) PR=0 SZ=1 1111nnnnmmm10111 */ /* FMOV XDm,@(R0,Rn) PR=1 1111nnnnmmm10111 */ -const void FMOVFRS0(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FMOVFRS0(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ m= m & 14; - sh4->ea = sh4->r[0] + sh4->r[n]; - WL(sh4, sh4->ea,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] ); - WL(sh4, sh4->ea+4,sh4->xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] ); + m_ea = m_r[0] + m_r[n]; + WL(m_ea,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] ); + WL(m_ea+4,m_xf[m+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] ); } else { /* PR = 0 */ - if (sh4->fpu_sz) { /* SZ = 1 */ + if (m_fpu_sz) { /* SZ = 1 */ if (m & 1) { m= m & 14; - sh4->ea = sh4->r[0] + sh4->r[n]; - WL(sh4, sh4->ea,sh4->xf[m] ); - WL(sh4, sh4->ea+4,sh4->xf[m+1] ); + m_ea = m_r[0] + m_r[n]; + WL(m_ea,m_xf[m] ); + WL(m_ea+4,m_xf[m+1] ); } else { - sh4->ea = sh4->r[0] + sh4->r[n]; - WL(sh4, sh4->ea,sh4->fr[m] ); - WL(sh4, sh4->ea+4,sh4->fr[m+1] ); + m_ea = m_r[0] + m_r[n]; + WL(m_ea,m_fr[m] ); + WL(m_ea+4,m_fr[m+1] ); } } else { /* SZ = 0 */ - sh4->ea = sh4->r[0] + sh4->r[n]; - WL(sh4, sh4->ea,sh4->fr[m] ); + m_ea = m_r[0] + m_r[n]; + WL(m_ea,m_fr[m] ); } } } @@ -2371,30 +2475,30 @@ const void FMOVFRS0(sh4_state *sh4, const UINT16 opcode) /* FMOV @(R0,Rm),DRn PR=0 SZ=1 1111nnn0mmmm0110 */ /* FMOV @(R0,Rm),XDn PR=0 SZ=1 1111nnn1mmmm0110 */ /* FMOV @(R0,Rm),XDn PR=1 1111nnn1mmmm0110 */ -const void FMOVS0FR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FMOVS0FR(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n= n & 14; - sh4->ea = sh4->r[0] + sh4->r[m]; - sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(sh4, sh4->ea ); - sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(sh4, sh4->ea+4 ); + m_ea = m_r[0] + m_r[m]; + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea ); + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 ); } else { /* PR = 0 */ - if (sh4->fpu_sz) { /* SZ = 1 */ + if (m_fpu_sz) { /* SZ = 1 */ if (n & 1) { n= n & 14; - sh4->ea = sh4->r[0] + sh4->r[m]; - sh4->xf[n] = RL(sh4, sh4->ea ); - sh4->xf[n+1] = RL(sh4, sh4->ea+4 ); + m_ea = m_r[0] + m_r[m]; + m_xf[n] = RL(m_ea ); + m_xf[n+1] = RL(m_ea+4 ); } else { - sh4->ea = sh4->r[0] + sh4->r[m]; - sh4->fr[n] = RL(sh4, sh4->ea ); - sh4->fr[n+1] = RL(sh4, sh4->ea+4 ); + m_ea = m_r[0] + m_r[m]; + m_fr[n] = RL(m_ea ); + m_fr[n+1] = RL(m_ea+4 ); } } else { /* SZ = 0 */ - sh4->ea = sh4->r[0] + sh4->r[m]; - sh4->fr[n] = RL(sh4, sh4->ea ); + m_ea = m_r[0] + m_r[m]; + m_fr[n] = RL(m_ea ); } } } @@ -2404,38 +2508,38 @@ const void FMOVS0FR(sh4_state *sh4, const UINT16 opcode) /* FMOV @Rm,XDn PR=0 SZ=1 1111nnn1mmmm1000 */ /* FMOV @Rm,XDn PR=1 1111nnn1mmmm1000 */ /* FMOV @Rm,DRn PR=1 1111nnn0mmmm1000 */ -const void FMOVMRFR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FMOVMRFR(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ if (n & 1) { n= n & 14; - sh4->ea = sh4->r[m]; - sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(sh4, sh4->ea ); - sh4->xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(sh4, sh4->ea+4 ); + m_ea = m_r[m]; + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea ); + m_xf[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 ); } else { n= n & 14; - sh4->ea = sh4->r[m]; - sh4->fr[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(sh4, sh4->ea ); - sh4->fr[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(sh4, sh4->ea+4 ); + m_ea = m_r[m]; + m_fr[n+NATIVE_ENDIAN_VALUE_LE_BE(1,0)] = RL(m_ea ); + m_fr[n+NATIVE_ENDIAN_VALUE_LE_BE(0,1)] = RL(m_ea+4 ); } } else { /* PR = 0 */ - if (sh4->fpu_sz) { /* SZ = 1 */ + if (m_fpu_sz) { /* SZ = 1 */ if (n & 1) { n= n & 14; - sh4->ea = sh4->r[m]; - sh4->xf[n] = RL(sh4, sh4->ea ); - sh4->xf[n+1] = RL(sh4, sh4->ea+4 ); + m_ea = m_r[m]; + m_xf[n] = RL(m_ea ); + m_xf[n+1] = RL(m_ea+4 ); } else { n= n & 14; - sh4->ea = sh4->r[m]; - sh4->fr[n] = RL(sh4, sh4->ea ); - sh4->fr[n+1] = RL(sh4, sh4->ea+4 ); + m_ea = m_r[m]; + m_fr[n] = RL(m_ea ); + m_fr[n+1] = RL(m_ea+4 ); } } else { /* SZ = 0 */ - sh4->ea = sh4->r[m]; - sh4->fr[n] = RL(sh4, sh4->ea ); + m_ea = m_r[m]; + m_fr[n] = RL(m_ea ); } } } @@ -2445,113 +2549,113 @@ const void FMOVMRFR(sh4_state *sh4, const UINT16 opcode) /* FMOV XDm,DRn PR=1 XDm -> DRn 1111nnn0mmm11100 */ /* FMOV DRm,XDn PR=1 DRm -> XDn 1111nnn1mmm01100 */ /* FMOV XDm,XDn PR=1 XDm -> XDn 1111nnn1mmm11100 */ -const void FMOVFR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FMOVFR(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if ((sh4->fpu_sz == 0) && (sh4->fpu_pr == 0)) /* SZ = 0 */ - sh4->fr[n] = sh4->fr[m]; + if ((m_fpu_sz == 0) && (m_fpu_pr == 0)) /* SZ = 0 */ + m_fr[n] = m_fr[m]; else { /* SZ = 1 or PR = 1 */ if (m & 1) { if (n & 1) { - sh4->xf[n & 14] = sh4->xf[m & 14]; - sh4->xf[n | 1] = sh4->xf[m | 1]; + m_xf[n & 14] = m_xf[m & 14]; + m_xf[n | 1] = m_xf[m | 1]; } else { - sh4->fr[n] = sh4->xf[m & 14]; - sh4->fr[n | 1] = sh4->xf[m | 1]; + m_fr[n] = m_xf[m & 14]; + m_fr[n | 1] = m_xf[m | 1]; } } else { if (n & 1) { - sh4->xf[n & 14] = sh4->fr[m]; - sh4->xf[n | 1] = sh4->fr[m | 1]; // (a&14)+1 -> a|1 + m_xf[n & 14] = m_fr[m]; + m_xf[n | 1] = m_fr[m | 1]; // (a&14)+1 -> a|1 } else { - sh4->fr[n] = sh4->fr[m]; - sh4->fr[n | 1] = sh4->fr[m | 1]; + m_fr[n] = m_fr[m]; + m_fr[n | 1] = m_fr[m | 1]; } } } } /* FLDI1 FRn 1111nnnn10011101 */ -const void FLDI1(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FLDI1(const UINT16 opcode) { - sh4->fr[Rn] = 0x3F800000; + m_fr[Rn] = 0x3F800000; } /* FLDI0 FRn 1111nnnn10001101 */ -const void FLDI0(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FLDI0(const UINT16 opcode) { - sh4->fr[Rn] = 0; + m_fr[Rn] = 0; } /* FLDS FRm,FPUL 1111mmmm00011101 */ -const void FLDS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device:: FLDS(const UINT16 opcode) { - sh4->fpul = sh4->fr[Rn]; + m_fpul = m_fr[Rn]; } /* FSTS FPUL,FRn 1111nnnn00001101 */ -const void FSTS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device:: FSTS(const UINT16 opcode) { - sh4->fr[Rn] = sh4->fpul; + m_fr[Rn] = m_fpul; } /* FRCHG 1111101111111101 */ -const void FRCHG(sh4_state *sh4) +void sh34_base_device::FRCHG() { - sh4->fpscr ^= FR; - sh4_swap_fp_registers(sh4); + m_fpscr ^= FR; + sh4_swap_fp_registers(); } /* FSCHG 1111001111111101 */ -const void FSCHG(sh4_state *sh4) +void sh34_base_device::FSCHG() { - sh4->fpscr ^= SZ; - sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0; + m_fpscr ^= SZ; + m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; } /* FTRC FRm,FPUL PR=0 1111mmmm00111101 */ /* FTRC DRm,FPUL PR=1 1111mmm000111101 */ -const void FTRC(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FTRC(const UINT16 opcode) { UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ if(n & 1) fatalerror("SH-4: FTRC opcode used with n %d",n); n = n & 14; - *((INT32 *)&sh4->fpul) = (INT32)FP_RFD(n); + *((INT32 *)&m_fpul) = (INT32)FP_RFD(n); } else { /* PR = 0 */ - /* read sh4->fr[n] as float -> truncate -> fpul(32) */ - *((INT32 *)&sh4->fpul) = (INT32)FP_RFS(n); + /* read m_fr[n] as float -> truncate -> fpul(32) */ + *((INT32 *)&m_fpul) = (INT32)FP_RFS(n); } } /* FLOAT FPUL,FRn PR=0 1111nnnn00101101 */ /* FLOAT FPUL,DRn PR=1 1111nnn000101101 */ -const void FLOAT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FLOAT(const UINT16 opcode) { UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ if(n & 1) fatalerror("SH-4: FLOAT opcode used with n %d",n); n = n & 14; - FP_RFD(n) = (double)*((INT32 *)&sh4->fpul); + FP_RFD(n) = (double)*((INT32 *)&m_fpul); } else { /* PR = 0 */ - FP_RFS(n) = (float)*((INT32 *)&sh4->fpul); + FP_RFS(n) = (float)*((INT32 *)&m_fpul); } } /* FNEG FRn PR=0 1111nnnn01001101 */ /* FNEG DRn PR=1 1111nnn001001101 */ -const void FNEG(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FNEG(const UINT16 opcode) { UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ FP_RFD(n) = -FP_RFD(n); } else { /* PR = 0 */ FP_RFS(n) = -FP_RFS(n); @@ -2560,96 +2664,96 @@ const void FNEG(sh4_state *sh4, const UINT16 opcode) /* FABS FRn PR=0 1111nnnn01011101 */ /* FABS DRn PR=1 1111nnn001011101 */ -const void FABS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FABS(const UINT16 opcode) { UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ #ifdef LSB_FIRST n = n | 1; // n & 14 + 1 - sh4->fr[n] = sh4->fr[n] & 0x7fffffff; + m_fr[n] = m_fr[n] & 0x7fffffff; #else n = n & 14; - sh4->fr[n] = sh4->fr[n] & 0x7fffffff; + m_fr[n] = m_fr[n] & 0x7fffffff; #endif } else { /* PR = 0 */ - sh4->fr[n] = sh4->fr[n] & 0x7fffffff; + m_fr[n] = m_fr[n] & 0x7fffffff; } } /* FCMP/EQ FRm,FRn PR=0 1111nnnnmmmm0100 */ /* FCMP/EQ DRm,DRn PR=1 1111nnn0mmm00100 */ -const void FCMP_EQ(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FCMP_EQ(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; if (FP_RFD(n) == FP_RFD(m)) - sh4->sr |= T; + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } else { /* PR = 0 */ if (FP_RFS(n) == FP_RFS(m)) - sh4->sr |= T; + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } } /* FCMP/GT FRm,FRn PR=0 1111nnnnmmmm0101 */ /* FCMP/GT DRm,DRn PR=1 1111nnn0mmm00101 */ -const void FCMP_GT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FCMP_GT(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; if (FP_RFD(n) > FP_RFD(m)) - sh4->sr |= T; + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } else { /* PR = 0 */ if (FP_RFS(n) > FP_RFS(m)) - sh4->sr |= T; + m_sr |= T; else - sh4->sr &= ~T; + m_sr &= ~T; } } /* FCNVDS DRm,FPUL PR=1 1111mmm010111101 */ -const void FCNVDS(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FCNVDS(const UINT16 opcode) { UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n = n & 14; - if (sh4->fpscr & RM) - sh4->fr[n | NATIVE_ENDIAN_VALUE_LE_BE(0,1)] &= 0xe0000000; /* round toward zero*/ - *((float *)&sh4->fpul) = (float)FP_RFD(n); + if (m_fpscr & RM) + m_fr[n | NATIVE_ENDIAN_VALUE_LE_BE(0,1)] &= 0xe0000000; /* round toward zero*/ + *((float *)&m_fpul) = (float)FP_RFD(n); } } /* FCNVSD FPUL, DRn PR=1 1111nnn010101101 */ -const void FCNVSD(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FCNVSD(const UINT16 opcode) { UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n = n & 14; - FP_RFD(n) = (double)*((float *)&sh4->fpul); + FP_RFD(n) = (double)*((float *)&m_fpul); } } /* FADD FRm,FRn PR=0 1111nnnnmmmm0000 */ /* FADD DRm,DRn PR=1 1111nnn0mmm00000 */ -const void FADD(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FADD(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; FP_RFD(n) = FP_RFD(n) + FP_RFD(m); @@ -2660,11 +2764,11 @@ const void FADD(sh4_state *sh4, const UINT16 opcode) /* FSUB FRm,FRn PR=0 1111nnnnmmmm0001 */ /* FSUB DRm,DRn PR=1 1111nnn0mmm00001 */ -const void FSUB(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FSUB(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; FP_RFD(n) = FP_RFD(n) - FP_RFD(m); @@ -2676,11 +2780,11 @@ const void FSUB(sh4_state *sh4, const UINT16 opcode) /* FMUL FRm,FRn PR=0 1111nnnnmmmm0010 */ /* FMUL DRm,DRn PR=1 1111nnn0mmm00010 */ -const void FMUL(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FMUL(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; FP_RFD(n) = FP_RFD(n) * FP_RFD(m); @@ -2691,11 +2795,11 @@ const void FMUL(sh4_state *sh4, const UINT16 opcode) /* FDIV FRm,FRn PR=0 1111nnnnmmmm0011 */ /* FDIV DRm,DRn PR=1 1111nnn0mmm00011 */ -const void FDIV(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FDIV(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n = n & 14; m = m & 14; if (FP_RFD(m) == 0) @@ -2709,22 +2813,22 @@ const void FDIV(sh4_state *sh4, const UINT16 opcode) } /* FMAC FR0,FRm,FRn PR=0 1111nnnnmmmm1110 */ -const void FMAC(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FMAC(const UINT16 opcode) { UINT32 m = Rm; UINT32 n = Rn; - if (sh4->fpu_pr == 0) { /* PR = 0 */ + if (m_fpu_pr == 0) { /* PR = 0 */ FP_RFS(n) = (FP_RFS(0) * FP_RFS(m)) + FP_RFS(n); } } /* FSQRT FRn PR=0 1111nnnn01101101 */ /* FSQRT DRn PR=1 1111nnnn01101101 */ -const void FSQRT(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FSQRT(const UINT16 opcode) { UINT32 n = Rn; - if (sh4->fpu_pr) { /* PR = 1 */ + if (m_fpu_pr) { /* PR = 1 */ n = n & 14; if (FP_RFD(n) < 0) return; @@ -2737,7 +2841,7 @@ const void FSQRT(sh4_state *sh4, const UINT16 opcode) } /* FSRRA FRn PR=0 1111nnnn01111101 */ -const void FSRRA(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FSRRA(const UINT16 opcode) { UINT32 n = Rn; @@ -2747,19 +2851,19 @@ const void FSRRA(sh4_state *sh4, const UINT16 opcode) } /* FSSCA FPUL,FRn PR=0 1111nnn011111101 */ -const void FSSCA(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FSSCA(const UINT16 opcode) { UINT32 n = Rn; float angle; - angle = (((float)(sh4->fpul & 0xFFFF)) / 65536.0) * 2.0 * M_PI; + angle = (((float)(m_fpul & 0xFFFF)) / 65536.0) * 2.0 * M_PI; FP_RFS(n) = sinf(angle); FP_RFS(n+1) = cosf(angle); } /* FIPR FVm,FVn PR=0 1111nnmm11101101 */ -const void FIPR(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FIPR(const UINT16 opcode) { UINT32 n = Rn; @@ -2775,7 +2879,7 @@ int a; } /* FTRV XMTRX,FVn PR=0 1111nn0111111101 */ -const void FTRV(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::FTRV(const UINT16 opcode) { UINT32 n = Rn; @@ -2792,44 +2896,49 @@ float sum[4]; FP_RFS(n + i) = sum[i]; } -const void op1111_0xf13(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::op1111_0xf13(const UINT16 opcode) { if (opcode & 0x100) { if (opcode & 0x200) { switch (opcode & 0xC00) { case 0x000: - FSCHG(sh4); + FSCHG(); break; case 0x800: - FRCHG(sh4); + FRCHG(); break; default: - debugger_break(sh4->device->machine()); + debugger_break(machine()); break; } } else { - FTRV(sh4, opcode); + FTRV(opcode); } } else { - FSSCA(sh4, opcode); + FSSCA(opcode); } } -const void dbreak(sh4_state *sh4, const UINT16 opcode) +void sh34_base_device::dbreak(const UINT16 opcode) { - debugger_break(sh4->device->machine()); + debugger_break(machine()); } -sh4ophandler op1111_0x13_handlers[] = +sh34_base_device::sh4ophandler sh34_base_device::s_master_ophandler_table[0x10000]; + +const sh34_base_device::sh4ophandler sh34_base_device::s_op1111_0x13_handlers[16] = { - FSTS, FLDS, FLOAT, FTRC, FNEG, FABS, FSQRT, FSRRA, FLDI0, FLDI1, FCNVSD, FCNVDS, dbreak, dbreak, FIPR, op1111_0xf13 + &sh34_base_device::FSTS, &sh34_base_device::FLDS, &sh34_base_device::FLOAT, &sh34_base_device::FTRC, + &sh34_base_device::FNEG, &sh34_base_device::FABS, &sh34_base_device::FSQRT, &sh34_base_device::FSRRA, + &sh34_base_device::FLDI0, &sh34_base_device::FLDI1, &sh34_base_device::FCNVSD, &sh34_base_device::FCNVDS, + &sh34_base_device::dbreak, &sh34_base_device::dbreak, &sh34_base_device::FIPR, &sh34_base_device::op1111_0xf13 }; -const void op1111_0x13(sh4_state *sh4, UINT16 opcode) +void sh34_base_device::op1111_0x13(UINT16 opcode) { - op1111_0x13_handlers[(opcode&0xf0)>>4](sh4, opcode); + (this->*s_op1111_0x13_handlers[(opcode&0xf0)>>4])(opcode); } @@ -2837,192 +2946,274 @@ const void op1111_0x13(sh4_state *sh4, UINT16 opcode) * MAME CPU INTERFACE *****************************************************************************/ -static CPU_RESET( common_sh4_reset ) +void sh34_base_device::device_reset() { - sh4_state *sh4 = get_safe_token(device); - emu_timer *tsaved[4]; - emu_timer *tsave[5]; - int save_is_slave; - int savecpu_clock, savebus_clock, savepm_clock; + m_ppc = 0; + m_spc = 0; + m_pr = 0; + m_sr = 0; + m_ssr = 0; + m_gbr = 0; + m_vbr = 0; + m_mach = 0; + m_macl = 0; + memset(m_r, 0, sizeof(m_r)); + memset(m_rbnk, 0, sizeof(m_rbnk)); + m_sgr = 0; + memset(m_fr, 0, sizeof(m_fr)); + memset(m_xf, 0, sizeof(m_xf)); + m_ea = 0; + m_delay = 0; + m_cpu_off = 0; + m_pending_irq = 0; + m_test_irq = 0; + memset(m_exception_priority, 0, sizeof(m_exception_priority)); + memset(m_exception_requesting, 0, sizeof(m_exception_requesting)); + memset(m_m, 0, sizeof(m_m)); + memset(m_sh3internal_upper, 0, sizeof(m_sh3internal_upper)); + memset(m_sh3internal_lower, 0, sizeof(m_sh3internal_lower)); + memset(m_irq_line_state, 0, sizeof(m_irq_line_state)); + m_SH4_TSTR = 0; + m_SH4_TCNT0 = 0; + m_SH4_TCNT1 = 0; + m_SH4_TCNT2 = 0; + m_SH4_TCR0 = 0; + m_SH4_TCR1 = 0; + m_SH4_TCR2 = 0; + m_SH4_TCOR0 = 0; + m_SH4_TCOR1 = 0; + m_SH4_TCOR2 = 0; + m_SH4_TOCR = 0; + m_SH4_TCPR2 = 0; + m_SH4_IPRA = 0; + m_SH4_IPRC = 0; + m_SH4_SAR0 = 0; + m_SH4_SAR1 = 0; + m_SH4_SAR2 = 0; + m_SH4_SAR3 = 0; + m_SH4_DAR0 = 0; + m_SH4_DAR1 = 0; + m_SH4_DAR2 = 0; + m_SH4_DAR3 = 0; + m_SH4_CHCR0 = 0; + m_SH4_CHCR1 = 0; + m_SH4_CHCR2 = 0; + m_SH4_CHCR3 = 0; + m_SH4_DMATCR0 = 0; + m_SH4_DMATCR1 = 0; + m_SH4_DMATCR2 = 0; + m_SH4_DMATCR3 = 0; + m_SH4_DMAOR = 0; + m_nmi_line_state = 0; + m_frt_input = 0; + m_internal_irq_vector = 0; + m_refresh_timer_base = 0; + memset(m_dma_timer_active, 0, sizeof(m_dma_timer_active)); + memset(m_dma_source, 0, sizeof(m_dma_source)); + memset(m_dma_destination, 0, sizeof(m_dma_destination)); + memset(m_dma_count, 0, sizeof(m_dma_count)); + memset(m_dma_wordsize, 0, sizeof(m_dma_wordsize)); + memset(m_dma_source_increment, 0, sizeof(m_dma_source_increment)); + memset(m_dma_destination_increment, 0, sizeof(m_dma_destination_increment)); + memset(m_dma_mode, 0, sizeof(m_dma_mode)); + m_ioport16_pullup = 0; + m_ioport16_direction = 0; + m_ioport4_pullup = 0; + m_ioport4_direction = 0; - void (*f)(UINT32 data); - device_irq_acknowledge_delegate save_irqcallback; + sh4_default_exception_priorities(); - tsaved[0] = sh4->dma_timer[0]; - tsaved[1] = sh4->dma_timer[1]; - tsaved[2] = sh4->dma_timer[2]; - tsaved[3] = sh4->dma_timer[3]; - tsave[0] = sh4->refresh_timer; - tsave[1] = sh4->rtc_timer; - tsave[2] = sh4->timer[0]; - tsave[3] = sh4->timer[1]; - tsave[4] = sh4->timer[2]; + m_rtc_timer->adjust(attotime::from_hz(128)); - f = sh4->ftcsr_read_callback; - save_irqcallback = sh4->irq_callback; - save_is_slave = sh4->is_slave; - savecpu_clock = sh4->cpu_clock; - savebus_clock = sh4->bus_clock; - savepm_clock = sh4->pm_clock; - memset(sh4, 0, sizeof(*sh4)); - sh4->is_slave = save_is_slave; - sh4->cpu_clock = savecpu_clock; - sh4->bus_clock = savebus_clock; - sh4->pm_clock = savepm_clock; - sh4->ftcsr_read_callback = f; - sh4->irq_callback = save_irqcallback; - sh4->device = device; - sh4->internal = &device->space(AS_PROGRAM); - sh4->program = &device->space(AS_PROGRAM); - sh4->direct = &sh4->program->direct(); - sh4->io = &device->space(AS_IO); + m_pc = 0xa0000000; + m_r[15] = RL(4); + m_sr = 0x700000f0; + m_fpscr = 0x00040001; + m_fpu_sz = (m_fpscr & SZ) ? 1 : 0; + m_fpu_pr = (m_fpscr & PR) ? 1 : 0; + m_fpul = 0; + m_dbr = 0; - sh4->dma_timer[0] = tsaved[0]; - sh4->dma_timer[1] = tsaved[1]; - sh4->dma_timer[2] = tsaved[2]; - sh4->dma_timer[3] = tsaved[3]; - sh4->refresh_timer = tsave[0]; - sh4->rtc_timer = tsave[1]; - sh4->timer[0] = tsave[2]; - sh4->timer[1] = tsave[3]; - sh4->timer[2] = tsave[4]; - memset(sh4->m, 0, 16384*4); - sh4_default_exception_priorities(sh4); - memset(sh4->exception_requesting, 0, sizeof(sh4->exception_requesting)); + m_internal_irq_level = -1; + m_irln = 15; + m_sleep_mode = 0; - sh4->rtc_timer->adjust(attotime::from_hz(128)); + m_sh4_mmu_enabled = 0; - - sh4->pc = 0xa0000000; - sh4->r[15] = RL(sh4,4); - sh4->sr = 0x700000f0; - sh4->fpscr = 0x00040001; - sh4->fpu_sz = (sh4->fpscr & SZ) ? 1 : 0; - sh4->fpu_pr = (sh4->fpscr & PR) ? 1 : 0; - sh4->fpul = 0; - sh4->dbr = 0; - - sh4->internal_irq_level = -1; - sh4->irln = 15; - sh4->sleep_mode = 0; - - sh4->sh4_mmu_enabled = 0; - - sh4_build_optable(sh4); + sh4_build_optable(); } /*------------------------------------------------- sh3_reset - reset the processor -------------------------------------------------*/ -static CPU_RESET( sh3 ) +void sh3_base_device::device_reset() { - sh4_state *sh4 = get_safe_token(device); - - CPU_RESET_CALL(common_sh4_reset); - - sh4->cpu_type = CPU_TYPE_SH3; - - sh4->SH4_TCOR0 = 0xffffffff; - sh4->SH4_TCNT0 = 0xffffffff; - sh4->SH4_TCOR1 = 0xffffffff; - sh4->SH4_TCNT1 = 0xffffffff; - sh4->SH4_TCOR2 = 0xffffffff; - sh4->SH4_TCNT2 = 0xffffffff; + sh34_base_device::device_reset(); + m_SH4_TCOR0 = 0xffffffff; + m_SH4_TCNT0 = 0xffffffff; + m_SH4_TCOR1 = 0xffffffff; + m_SH4_TCNT1 = 0xffffffff; + m_SH4_TCOR2 = 0xffffffff; + m_SH4_TCNT2 = 0xffffffff; } -static CPU_RESET( sh4 ) +void sh4_base_device::device_reset() { - sh4_state *sh4 = get_safe_token(device); + sh34_base_device::device_reset(); - CPU_RESET_CALL(common_sh4_reset); - - sh4->cpu_type = CPU_TYPE_SH4; - - sh4->m[RCR2] = 0x09; - sh4->SH4_TCOR0 = 0xffffffff; - sh4->SH4_TCNT0 = 0xffffffff; - sh4->SH4_TCOR1 = 0xffffffff; - sh4->SH4_TCNT1 = 0xffffffff; - sh4->SH4_TCOR2 = 0xffffffff; - sh4->SH4_TCNT2 = 0xffffffff; + m_m[RCR2] = 0x09; + m_SH4_TCOR0 = 0xffffffff; + m_SH4_TCNT0 = 0xffffffff; + m_SH4_TCOR1 = 0xffffffff; + m_SH4_TCNT1 = 0xffffffff; + m_SH4_TCOR2 = 0xffffffff; + m_SH4_TCNT2 = 0xffffffff; } /* These tables are combined into our main opcode jump table, master_ophandler_table in the RESET function */ -sh4ophandler op1000_handler[] = +#define SH4OP(x) &sh34_base_device::x + +const sh34_base_device::sh4ophandler sh34_base_device::s_op1000_handler[16] = { - MOVBS4, MOVWS4, NOP, NOP, MOVBL4, MOVWL4, NOP, NOP, CMPIM, BT, NOP, BF, NOP, BTS, NOP, BFS + SH4OP(MOVBS4), SH4OP(MOVWS4), SH4OP(NOP), SH4OP(NOP), SH4OP(MOVBL4), SH4OP(MOVWL4), SH4OP(NOP), SH4OP(NOP), + SH4OP(CMPIM), SH4OP(BT), SH4OP(NOP), SH4OP(BF), SH4OP(NOP), SH4OP(BTS), SH4OP(NOP), SH4OP(BFS) }; -sh4ophandler op1100_handler[] = +const sh34_base_device::sh4ophandler sh34_base_device::s_op1100_handler[16] = { - MOVBSG, MOVWSG, MOVLSG, TRAPA, MOVBLG, MOVWLG, MOVLLG, MOVA, TSTI, ANDI, XORI, ORI, TSTM, ANDM, XORM, ORM + SH4OP(MOVBSG), SH4OP(MOVWSG), SH4OP(MOVLSG), SH4OP(TRAPA), SH4OP(MOVBLG), SH4OP(MOVWLG), SH4OP(MOVLLG), SH4OP(MOVA), + SH4OP(TSTI), SH4OP(ANDI), SH4OP(XORI), SH4OP(ORI), SH4OP(TSTM), SH4OP(ANDM), SH4OP(XORM), SH4OP(ORM) }; -sh4ophandler op0000_handlers[] = +const sh34_base_device::sh4ophandler sh34_base_device::s_op0000_handlers[256] = { - NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, - NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, - STCSR, STCGBR, STCVBR, STCSSR, STCSPC, NOP, NOP, NOP, STCRBANK, STCRBANK, STCRBANK, STCRBANK, STCRBANK, STCRBANK, STCRBANK, STCRBANK, - BSRF, NOP, BRAF, NOP, NOP, NOP, NOP, NOP, PREFM, TODO, TODO, TODO, MOVCAL, NOP, NOP, NOP, - MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, MOVBS0, - MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, MOVWS0, - MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, MOVLS0, - MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, MULL, - CLRT, SETT, CLRMAC, TODO, CLRS, SETS, NOP, NOP, CLRT, SETT, CLRMAC, TODO, CLRS, SETS, NOP, NOP, - NOP, DIV0U, MOVT, NOP, NOP, DIV0U, MOVT, NOP, NOP, DIV0U, MOVT, NOP, NOP, DIV0U, MOVT, NOP, - STSMACH, STSMACL, STSPR, STCSGR, NOP, STSFPUL, STSFPSCR, STCDBR, STSMACH, STSMACL, STSPR, STCSGR, NOP, STSFPUL, STSFPSCR, STCDBR, - RTS, SLEEP, RTE, NOP, RTS, SLEEP, RTE, NOP, RTS, SLEEP, RTE, NOP, RTS, SLEEP, RTE, NOP, - MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, MOVBL0, - MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, MOVWL0, - MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, MOVLL0, - MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, MAC_L, + SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), + SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), + SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), + SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), + SH4OP(STCSR), SH4OP(STCGBR), SH4OP(STCVBR), SH4OP(STCSSR), SH4OP(STCSPC), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), + SH4OP(STCRBANK), SH4OP(STCRBANK), SH4OP(STCRBANK), SH4OP(STCRBANK), SH4OP(STCRBANK), SH4OP(STCRBANK), SH4OP(STCRBANK), SH4OP(STCRBANK), + SH4OP(BSRF), SH4OP(NOP), SH4OP(BRAF), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), + SH4OP(PREFM), SH4OP(TODO), SH4OP(TODO), SH4OP(TODO), SH4OP(MOVCAL), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), + SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), + SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), SH4OP(MOVBS0), + SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), + SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), SH4OP(MOVWS0), + SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), + SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), SH4OP(MOVLS0), + SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), + SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), SH4OP(MULL), + SH4OP(CLRT), SH4OP(SETT), SH4OP(CLRMAC), SH4OP(TODO), SH4OP(CLRS), SH4OP(SETS), SH4OP(NOP), SH4OP(NOP), + SH4OP(CLRT), SH4OP(SETT), SH4OP(CLRMAC), SH4OP(TODO), SH4OP(CLRS), SH4OP(SETS), SH4OP(NOP), SH4OP(NOP), + SH4OP(NOP), SH4OP(DIV0U), SH4OP(MOVT), SH4OP(NOP), SH4OP(NOP), SH4OP(DIV0U), SH4OP(MOVT), SH4OP(NOP), + SH4OP(NOP), SH4OP(DIV0U), SH4OP(MOVT), SH4OP(NOP), SH4OP(NOP), SH4OP(DIV0U), SH4OP(MOVT), SH4OP(NOP), + SH4OP(STSMACH), SH4OP(STSMACL), SH4OP(STSPR), SH4OP(STCSGR), SH4OP(NOP), SH4OP(STSFPUL), SH4OP(STSFPSCR), SH4OP(STCDBR), + SH4OP(STSMACH), SH4OP(STSMACL), SH4OP(STSPR), SH4OP(STCSGR), SH4OP(NOP), SH4OP(STSFPUL), SH4OP(STSFPSCR), SH4OP(STCDBR), + SH4OP(RTS), SH4OP(SLEEP), SH4OP(RTE), SH4OP(NOP), SH4OP(RTS), SH4OP(SLEEP), SH4OP(RTE), SH4OP(NOP), + SH4OP(RTS), SH4OP(SLEEP), SH4OP(RTE), SH4OP(NOP), SH4OP(RTS), SH4OP(SLEEP), SH4OP(RTE), SH4OP(NOP), + SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), + SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), SH4OP(MOVBL0), + SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), + SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), SH4OP(MOVWL0), + SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), + SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), SH4OP(MOVLL0), + SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), + SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L), SH4OP(MAC_L) }; -sh4ophandler op0100_handlers[] = +const sh34_base_device::sh4ophandler sh34_base_device::s_op0100_handlers[256] = { - SHLL, DT, SHAL, NOP, SHLL, DT, SHAL, NOP, SHLL, DT, SHAL, NOP, SHLL, DT, SHAL, NOP, - SHLR, CMPPZ, SHAR, NOP, SHLR, CMPPZ, SHAR, NOP, SHLR, CMPPZ, SHAR, NOP, SHLR, CMPPZ, SHAR, NOP, - STSMMACH, STSMMACL, STSMPR, STCMSGR, NOP, STSMFPUL, STSMFPSCR, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, STCMDBR, - STCMSR, STCMGBR, STCMVBR, STCMSSR, STCMSPC, NOP, NOP, NOP, STCMRBANK, STCMRBANK, STCMRBANK, STCMRBANK, STCMRBANK, STCMRBANK, STCMRBANK, STCMRBANK, - ROTL, NOP, ROTCL, NOP, ROTL, NOP, ROTCL, NOP, ROTL, NOP, ROTCL, NOP, ROTL, NOP, ROTCL, NOP, - ROTR, CMPPL, ROTCR, NOP, ROTR, CMPPL, ROTCR, NOP, ROTR, CMPPL, ROTCR, NOP, ROTR, CMPPL, ROTCR, NOP, - LDSMMACH, LDSMMACL, LDSMPR, NOP, NOP, LDSMFPUL, LDSMFPSCR, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, LDCMDBR, - LDCMSR, LDCMGBR, LDCMVBR, LDCMSSR, LDCMSPC, NOP, NOP, NOP, LDCMRBANK, LDCMRBANK, LDCMRBANK, LDCMRBANK, LDCMRBANK, LDCMRBANK, LDCMRBANK, LDCMRBANK, - SHLL2, SHLL8, SHLL16, NOP, SHLL2, SHLL8, SHLL16, NOP, SHLL2, SHLL8, SHLL16, NOP, SHLL2, SHLL8, SHLL16, NOP, - SHLR2, SHLR8, SHLR16, NOP, SHLR2, SHLR8, SHLR16, NOP, SHLR2, SHLR8, SHLR16, NOP, SHLR2, SHLR8, SHLR16, NOP, - LDSMACH, LDSMACL, LDSPR, NOP, NOP, LDSFPUL, LDSFPSCR, NOP, NOP, NOP, NOP, NOP, NOP, NOP, NOP, LDCDBR, - JSR, TAS, JMP, NOP, JSR, TAS, JMP, NOP, JSR, TAS, JMP, NOP, JSR, TAS, JMP, NOP, - SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, SHAD, - SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, SHLD, - LDCSR, LDCGBR, LDCVBR, LDCSSR, LDCSPC, NOP, NOP, NOP, LDCRBANK, LDCRBANK, LDCRBANK, LDCRBANK, LDCRBANK, LDCRBANK, LDCRBANK, LDCRBANK, - MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, MAC_W, + SH4OP(SHLL), SH4OP(DT), SH4OP(SHAL), SH4OP(NOP), SH4OP(SHLL), SH4OP(DT), SH4OP(SHAL), SH4OP(NOP), + SH4OP(SHLL), SH4OP(DT), SH4OP(SHAL), SH4OP(NOP), SH4OP(SHLL), SH4OP(DT), SH4OP(SHAL), SH4OP(NOP), + SH4OP(SHLR), SH4OP(CMPPZ), SH4OP(SHAR), SH4OP(NOP), SH4OP(SHLR), SH4OP(CMPPZ), SH4OP(SHAR), SH4OP(NOP), + SH4OP(SHLR), SH4OP(CMPPZ), SH4OP(SHAR), SH4OP(NOP), SH4OP(SHLR), SH4OP(CMPPZ), SH4OP(SHAR), SH4OP(NOP), + SH4OP(STSMMACH), SH4OP(STSMMACL), SH4OP(STSMPR), SH4OP(STCMSGR), SH4OP(NOP), SH4OP(STSMFPUL), SH4OP(STSMFPSCR), SH4OP(NOP), + SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(STCMDBR), + SH4OP(STCMSR), SH4OP(STCMGBR), SH4OP(STCMVBR), SH4OP(STCMSSR), SH4OP(STCMSPC), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), + SH4OP(STCMRBANK), SH4OP(STCMRBANK), SH4OP(STCMRBANK), SH4OP(STCMRBANK), SH4OP(STCMRBANK), SH4OP(STCMRBANK), SH4OP(STCMRBANK), SH4OP(STCMRBANK), + SH4OP(ROTL), SH4OP(NOP), SH4OP(ROTCL), SH4OP(NOP), SH4OP(ROTL), SH4OP(NOP), SH4OP(ROTCL), SH4OP(NOP), + SH4OP(ROTL), SH4OP(NOP), SH4OP(ROTCL), SH4OP(NOP), SH4OP(ROTL), SH4OP(NOP), SH4OP(ROTCL), SH4OP(NOP), + SH4OP(ROTR), SH4OP(CMPPL), SH4OP(ROTCR), SH4OP(NOP), SH4OP(ROTR), SH4OP(CMPPL), SH4OP(ROTCR), SH4OP(NOP), + SH4OP(ROTR), SH4OP(CMPPL), SH4OP(ROTCR), SH4OP(NOP), SH4OP(ROTR), SH4OP(CMPPL), SH4OP(ROTCR), SH4OP(NOP), + SH4OP(LDSMMACH), SH4OP(LDSMMACL), SH4OP(LDSMPR), SH4OP(NOP), SH4OP(NOP), SH4OP(LDSMFPUL), SH4OP(LDSMFPSCR), SH4OP(NOP), + SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(LDCMDBR), + SH4OP(LDCMSR), SH4OP(LDCMGBR), SH4OP(LDCMVBR), SH4OP(LDCMSSR), SH4OP(LDCMSPC), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), + SH4OP(LDCMRBANK), SH4OP(LDCMRBANK), SH4OP(LDCMRBANK), SH4OP(LDCMRBANK), SH4OP(LDCMRBANK), SH4OP(LDCMRBANK), SH4OP(LDCMRBANK), SH4OP(LDCMRBANK), + SH4OP(SHLL2), SH4OP(SHLL8), SH4OP(SHLL16), SH4OP(NOP), SH4OP(SHLL2), SH4OP(SHLL8), SH4OP(SHLL16), SH4OP(NOP), + SH4OP(SHLL2), SH4OP(SHLL8), SH4OP(SHLL16), SH4OP(NOP), SH4OP(SHLL2), SH4OP(SHLL8), SH4OP(SHLL16), SH4OP(NOP), + SH4OP(SHLR2), SH4OP(SHLR8), SH4OP(SHLR16), SH4OP(NOP), SH4OP(SHLR2), SH4OP(SHLR8), SH4OP(SHLR16), SH4OP(NOP), + SH4OP(SHLR2), SH4OP(SHLR8), SH4OP(SHLR16), SH4OP(NOP), SH4OP(SHLR2), SH4OP(SHLR8), SH4OP(SHLR16), SH4OP(NOP), + SH4OP(LDSMACH), SH4OP(LDSMACL), SH4OP(LDSPR), SH4OP(NOP), SH4OP(NOP), SH4OP(LDSFPUL), SH4OP(LDSFPSCR), SH4OP(NOP), + SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), SH4OP(LDCDBR), + SH4OP(JSR), SH4OP(TAS), SH4OP(JMP), SH4OP(NOP), SH4OP(JSR), SH4OP(TAS), SH4OP(JMP), SH4OP(NOP), + SH4OP(JSR), SH4OP(TAS), SH4OP(JMP), SH4OP(NOP), SH4OP(JSR), SH4OP(TAS), SH4OP(JMP), SH4OP(NOP), + SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), + SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), SH4OP(SHAD), + SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), + SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), SH4OP(SHLD), + SH4OP(LDCSR), SH4OP(LDCGBR), SH4OP(LDCVBR), SH4OP(LDCSSR), SH4OP(LDCSPC), SH4OP(NOP), SH4OP(NOP), SH4OP(NOP), + SH4OP(LDCRBANK), SH4OP(LDCRBANK), SH4OP(LDCRBANK), SH4OP(LDCRBANK), SH4OP(LDCRBANK), SH4OP(LDCRBANK), SH4OP(LDCRBANK), SH4OP(LDCRBANK), + SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), + SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W), SH4OP(MAC_W) }; -sh4ophandler upper4bits[] = +const sh34_base_device::sh4ophandler sh34_base_device::s_upper4bits[256] = { - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* j = 0x0000 - uses op0000_handlers*/ - MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, MOVLS4, /* j = 0x1000 */ - MOVBS, MOVWS, MOVLS, NOP, MOVBM, MOVWM, MOVLM, DIV0S, TST, AND, XOR, OR, CMPSTR, XTRCT, MULU, MULS, /* j = 0x2000 */ - CMPEQ, NOP, CMPHS, CMPGE, DIV1, DMULU, CMPHI, CMPGT, SUB, NOP, SUBC, SUBV, ADD, DMULS, ADDC, ADDV, /* j = 0x3000 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* j = 0x4000 - uses op0100_handlers*/ - MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, MOVLL4, /* j = 0x5000 */ - MOVBL, MOVWL, MOVLL, MOV, MOVBP, MOVWP, MOVLP, NOT, SWAPB, SWAPW, NEGC, NEG, EXTUB, EXTUW, EXTSB, EXTSW, /* j = 0x6000 */ - ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, ADDI, /* j = 0x7000 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* j = 0x8000 - uses op1000_handlers */ - MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, MOVWI, /* j = 0x9000 */ - BRA, BRA, BRA, BRA, BRA, BRA, BRA, BRA, BRA, BRA, BRA, BRA, BRA, BRA, BRA, BRA, /* j = 0xa000 */ - BSR, BSR, BSR, BSR, BSR, BSR, BSR, BSR, BSR, BSR, BSR, BSR, BSR, BSR, BSR, BSR, /* j = 0xb000 */ - 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, /* j = 0xc000 - uses op1100_handlers */ - MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, MOVLI, /* j = 0xd000 */ - MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, MOVI, /* j = 0xe000 */ - FADD, FSUB, FMUL, FDIV, FCMP_EQ, FCMP_GT, FMOVS0FR, FMOVFRS0, FMOVMRFR, FMOVMRIFR, FMOVFRMR, FMOVFRMDR, FMOVFR, op1111_0x13,FMAC, dbreak /* j = 0xf000 */ + /* j = 0x0000 - uses op0000_handlers*/ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + /* j = 0x1000 */ + SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), + SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), SH4OP(MOVLS4), + /* j = 0x2000 */ + SH4OP(MOVBS), SH4OP(MOVWS), SH4OP(MOVLS), SH4OP(NOP), SH4OP(MOVBM), SH4OP(MOVWM), SH4OP(MOVLM), SH4OP(DIV0S), + SH4OP(TST), SH4OP(AND), SH4OP(XOR), SH4OP(OR), SH4OP(CMPSTR), SH4OP(XTRCT), SH4OP(MULU), SH4OP(MULS), + /* j = 0x3000 */ + SH4OP(CMPEQ), SH4OP(NOP), SH4OP(CMPHS), SH4OP(CMPGE), SH4OP(DIV1), SH4OP(DMULU), SH4OP(CMPHI), SH4OP(CMPGT), + SH4OP(SUB), SH4OP(NOP), SH4OP(SUBC), SH4OP(SUBV), SH4OP(ADD), SH4OP(DMULS), SH4OP(ADDC), SH4OP(ADDV), + /* j = 0x4000 - uses op0100_handlers*/ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + /* j = 0x5000 */ + SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), + SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), SH4OP(MOVLL4), + /* j = 0x6000 */ + SH4OP(MOVBL), SH4OP(MOVWL), SH4OP(MOVLL), SH4OP(MOV), SH4OP(MOVBP), SH4OP(MOVWP), SH4OP(MOVLP), SH4OP(NOT), + SH4OP(SWAPB), SH4OP(SWAPW), SH4OP(NEGC), SH4OP(NEG), SH4OP(EXTUB), SH4OP(EXTUW), SH4OP(EXTSB), SH4OP(EXTSW), + /* j = 0x7000 */ + SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), + SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), SH4OP(ADDI), + /* j = 0x8000 - uses op1000_handlers */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + /* j = 0x9000 */ + SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), + SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), SH4OP(MOVWI), + /* j = 0xa000 */ + SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), + SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), SH4OP(BRA), + /* j = 0xb000 */ + SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), + SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), SH4OP(BSR), + /* j = 0xc000 - uses op1100_handlers */ + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, + /* j = 0xd000 */ + SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), + SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), SH4OP(MOVLI), + /* j = 0xe000 */ + SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), + SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), SH4OP(MOVI), + /* j = 0xf000 */ + SH4OP(FADD), SH4OP(FSUB), SH4OP(FMUL), SH4OP(FDIV), SH4OP(FCMP_EQ), SH4OP(FCMP_GT), SH4OP(FMOVS0FR), SH4OP(FMOVFRS0), + SH4OP(FMOVMRFR), SH4OP(FMOVMRIFR), SH4OP(FMOVFRMR), SH4OP(FMOVFRMDR), SH4OP(FMOVFR), SH4OP(op1111_0x13),SH4OP(FMAC), SH4OP(dbreak) }; -void sh4_build_optable(sh4_state *sh4) +void sh34_base_device::sh4_build_optable() { int j,y,x,z; @@ -3035,7 +3226,7 @@ void sh4_build_optable(sh4_state *sh4) { for (z=0;z<0x10;z++) { - master_ophandler_table[j+y+x+z] = upper4bits[(((j+z)&0xf000)>>8) + (z & 0xf)]; + s_master_ophandler_table[j+y+x+z] = s_upper4bits[(((j+z)&0xf000)>>8) + (z & 0xf)]; } } } @@ -3050,7 +3241,7 @@ void sh4_build_optable(sh4_state *sh4) { for (z=0;z<0x10;z++) { - master_ophandler_table[j+y+x+z] = op0000_handlers[((((j+y+x+z)&0xf0)>>4)) | ((((j+y+x+z)&0xf)<<4))]; + s_master_ophandler_table[j+y+x+z] = s_op0000_handlers[((((j+y+x+z)&0xf0)>>4)) | ((((j+y+x+z)&0xf)<<4))]; } } } @@ -3065,7 +3256,7 @@ void sh4_build_optable(sh4_state *sh4) { for (z=0;z<0x10;z++) { - master_ophandler_table[j+y+x+z] = op0100_handlers[((((j+y+x+z)&0xf0)>>4)) | ((((j+y+x+z)&0xf)<<4))]; + s_master_ophandler_table[j+y+x+z] = s_op0100_handlers[((((j+y+x+z)&0xf0)>>4)) | ((((j+y+x+z)&0xf)<<4))]; } } } @@ -3081,7 +3272,7 @@ void sh4_build_optable(sh4_state *sh4) { for (z=0;z<0x10;z++) { - master_ophandler_table[j+y+x+z] = op1000_handler[((((j+y+x+z)&0xf00)>>8))]; + s_master_ophandler_table[j+y+x+z] = s_op1000_handler[((((j+y+x+z)&0xf00)>>8))]; } } } @@ -3096,7 +3287,7 @@ void sh4_build_optable(sh4_state *sh4) { for (z=0;z<0x10;z++) { - master_ophandler_table[j+y+x+z] = op1100_handler[((((j+y+x+z)&0xf00)>>8))]; + s_master_ophandler_table[j+y+x+z] = s_op1100_handler[((((j+y+x+z)&0xf00)>>8))]; } } } @@ -3107,685 +3298,674 @@ void sh4_build_optable(sh4_state *sh4) /* Execute cycles - returns number of cycles actually run */ -static CPU_EXECUTE( sh4 ) +void sh34_base_device::execute_run() { - sh4_state *sh4 = get_safe_token(device); - - if (sh4->cpu_off) + if (m_cpu_off) { - sh4->sh4_icount = 0; + m_sh4_icount = 0; return; } do { - if (sh4->delay) + if (m_delay) { - const UINT16 opcode = sh4->direct->read_decrypted_word((UINT32)(sh4->delay & AM), WORD2_XOR_LE(0)); + const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_delay & AM), WORD2_XOR_LE(0)); - debugger_instruction_hook(device, (sh4->pc-2) & AM); + debugger_instruction_hook(this, (m_pc-2) & AM); - sh4->delay = 0; - sh4->ppc = sh4->pc; + m_delay = 0; + m_ppc = m_pc; - master_ophandler_table[opcode](sh4, opcode); + (this->*s_master_ophandler_table[opcode])(opcode); - if (sh4->test_irq && !sh4->delay) + if (m_test_irq && !m_delay) { - sh4_check_pending_irq(sh4, "mame_sh4_execute"); + sh4_check_pending_irq("mame_sh4_execute"); } } else { - const UINT16 opcode = sh4->direct->read_decrypted_word((UINT32)(sh4->pc & AM), WORD2_XOR_LE(0)); + const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_pc & AM), WORD2_XOR_LE(0)); - debugger_instruction_hook(device, sh4->pc & AM); + debugger_instruction_hook(this, m_pc & AM); - sh4->pc += 2; - sh4->ppc = sh4->pc; + m_pc += 2; + m_ppc = m_pc; - master_ophandler_table[opcode](sh4, opcode); + (this->*s_master_ophandler_table[opcode])(opcode); - if (sh4->test_irq && !sh4->delay) + if (m_test_irq && !m_delay) { - sh4_check_pending_irq(sh4, "mame_sh4_execute"); + sh4_check_pending_irq("mame_sh4_execute"); } } - sh4->sh4_icount--; - } while( sh4->sh4_icount > 0 ); + m_sh4_icount--; + } while( m_sh4_icount > 0 ); } -static CPU_EXECUTE( sh4be ) +void sh3be_device::execute_run() { - sh4_state *sh4 = get_safe_token(device); - - if (sh4->cpu_off) + if (m_cpu_off) { - sh4->sh4_icount = 0; + m_sh4_icount = 0; return; } do { - if (sh4->delay) + if (m_delay) { - const UINT16 opcode = sh4->direct->read_decrypted_word((UINT32)(sh4->delay & AM), WORD_XOR_LE(6)); + const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_delay & AM), WORD_XOR_LE(6)); - debugger_instruction_hook(device, sh4->delay & AM); + debugger_instruction_hook(this, m_delay & AM); - sh4->delay = 0; - sh4->ppc = sh4->pc; + m_delay = 0; + m_ppc = m_pc; - master_ophandler_table[opcode](sh4, opcode); + (this->*s_master_ophandler_table[opcode])(opcode); - if (sh4->test_irq && !sh4->delay) + if (m_test_irq && !m_delay) { - sh4_check_pending_irq(sh4, "mame_sh4_execute"); + sh4_check_pending_irq("mame_sh4_execute"); } } else { - const UINT16 opcode = sh4->direct->read_decrypted_word((UINT32)(sh4->pc & AM), WORD_XOR_LE(6)); + const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_pc & AM), WORD_XOR_LE(6)); - debugger_instruction_hook(device, sh4->pc & AM); + debugger_instruction_hook(this, m_pc & AM); - sh4->pc += 2; - sh4->ppc = sh4->pc; + m_pc += 2; + m_ppc = m_pc; - master_ophandler_table[opcode](sh4, opcode); + (this->*s_master_ophandler_table[opcode])(opcode); - if (sh4->test_irq && !sh4->delay) + if (m_test_irq && !m_delay) { - sh4_check_pending_irq(sh4, "mame_sh4_execute"); + sh4_check_pending_irq("mame_sh4_execute"); } } - sh4->sh4_icount--; - } while( sh4->sh4_icount > 0 ); + m_sh4_icount--; + } while( m_sh4_icount > 0 ); } -static CPU_INIT( sh4 ) +void sh4be_device::execute_run() { - const struct sh4_config *conf = (const struct sh4_config *)device->static_config(); - sh4_state *sh4 = get_safe_token(device); - - sh4_common_init(device); - - sh4_parse_configuration(sh4, conf); - - sh4->irq_callback = irqcallback; - sh4->device = device; - sh4->internal = &device->space(AS_PROGRAM); - sh4->program = &device->space(AS_PROGRAM); - sh4->io = &device->space(AS_IO); - sh4_default_exception_priorities(sh4); - sh4->irln = 15; - sh4->test_irq = 0; - - device->save_item(NAME(sh4->pc)); - device->save_item(NAME(sh4->r[15])); - device->save_item(NAME(sh4->sr)); - device->save_item(NAME(sh4->pr)); - device->save_item(NAME(sh4->gbr)); - device->save_item(NAME(sh4->vbr)); - device->save_item(NAME(sh4->mach)); - device->save_item(NAME(sh4->macl)); - device->save_item(NAME(sh4->spc)); - device->save_item(NAME(sh4->ssr)); - device->save_item(NAME(sh4->sgr)); - device->save_item(NAME(sh4->fpscr)); - device->save_item(NAME(sh4->r[ 0])); - device->save_item(NAME(sh4->r[ 1])); - device->save_item(NAME(sh4->r[ 2])); - device->save_item(NAME(sh4->r[ 3])); - device->save_item(NAME(sh4->r[ 4])); - device->save_item(NAME(sh4->r[ 5])); - device->save_item(NAME(sh4->r[ 6])); - device->save_item(NAME(sh4->r[ 7])); - device->save_item(NAME(sh4->r[ 8])); - device->save_item(NAME(sh4->r[ 9])); - device->save_item(NAME(sh4->r[10])); - device->save_item(NAME(sh4->r[11])); - device->save_item(NAME(sh4->r[12])); - device->save_item(NAME(sh4->r[13])); - device->save_item(NAME(sh4->r[14])); - device->save_item(NAME(sh4->fr[ 0])); - device->save_item(NAME(sh4->fr[ 1])); - device->save_item(NAME(sh4->fr[ 2])); - device->save_item(NAME(sh4->fr[ 3])); - device->save_item(NAME(sh4->fr[ 4])); - device->save_item(NAME(sh4->fr[ 5])); - device->save_item(NAME(sh4->fr[ 6])); - device->save_item(NAME(sh4->fr[ 7])); - device->save_item(NAME(sh4->fr[ 8])); - device->save_item(NAME(sh4->fr[ 9])); - device->save_item(NAME(sh4->fr[10])); - device->save_item(NAME(sh4->fr[11])); - device->save_item(NAME(sh4->fr[12])); - device->save_item(NAME(sh4->fr[13])); - device->save_item(NAME(sh4->fr[14])); - device->save_item(NAME(sh4->fr[15])); - device->save_item(NAME(sh4->xf[ 0])); - device->save_item(NAME(sh4->xf[ 1])); - device->save_item(NAME(sh4->xf[ 2])); - device->save_item(NAME(sh4->xf[ 3])); - device->save_item(NAME(sh4->xf[ 4])); - device->save_item(NAME(sh4->xf[ 5])); - device->save_item(NAME(sh4->xf[ 6])); - device->save_item(NAME(sh4->xf[ 7])); - device->save_item(NAME(sh4->xf[ 8])); - device->save_item(NAME(sh4->xf[ 9])); - device->save_item(NAME(sh4->xf[10])); - device->save_item(NAME(sh4->xf[11])); - device->save_item(NAME(sh4->xf[12])); - device->save_item(NAME(sh4->xf[13])); - device->save_item(NAME(sh4->xf[14])); - device->save_item(NAME(sh4->xf[15])); - device->save_item(NAME(sh4->ea)); - device->save_item(NAME(sh4->fpul)); - device->save_item(NAME(sh4->dbr)); - device->save_item(NAME(sh4->exception_priority)); - device->save_item(NAME(sh4->exception_requesting)); - - device->save_item(NAME(sh4->SH4_TSTR)); - device->save_item(NAME(sh4->SH4_TCNT0)); - device->save_item(NAME(sh4->SH4_TCNT1)); - device->save_item(NAME(sh4->SH4_TCNT2)); - device->save_item(NAME(sh4->SH4_TCR0)); - device->save_item(NAME(sh4->SH4_TCR1)); - device->save_item(NAME(sh4->SH4_TCR2)); - device->save_item(NAME(sh4->SH4_TCOR0)); - device->save_item(NAME(sh4->SH4_TCOR1)); - device->save_item(NAME(sh4->SH4_TCOR2)); - device->save_item(NAME(sh4->SH4_TOCR)); - device->save_item(NAME(sh4->SH4_TCPR2)); - - device->save_item(NAME(sh4->SH4_IPRA)); - - device->save_item(NAME(sh4->SH4_IPRC)); - - - -} - -/************************************************************************** - * Generic set_info - **************************************************************************/ - -static CPU_SET_INFO( sh4 ) -{ - sh4_state *sh4 = get_safe_token(device); - - switch (state) + if (m_cpu_off) { - /* --- the following bits of info are set as 64-bit signed integers --- */ - case CPUINFO_INT_INPUT_STATE + SH4_IRL0: sh4_set_irq_line(sh4, SH4_IRL0, info->i); break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL1: sh4_set_irq_line(sh4, SH4_IRL1, info->i); break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL2: sh4_set_irq_line(sh4, SH4_IRL2, info->i); break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL3: sh4_set_irq_line(sh4, SH4_IRL3, info->i); break; - case CPUINFO_INT_INPUT_STATE + SH4_IRLn: sh4_set_irq_line(sh4, SH4_IRLn, info->i); break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: sh4_set_irq_line(sh4, INPUT_LINE_NMI, info->i); break; - - case CPUINFO_INT_REGISTER + SH4_PC: - case CPUINFO_INT_PC: sh4->pc = info->i; sh4->delay = 0; break; - case CPUINFO_INT_SP: sh4->r[15] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_PR: sh4->pr = info->i; break; - case CPUINFO_INT_REGISTER + SH4_SR: - sh4->sr = info->i; - sh4_exception_recompute(sh4); - sh4_check_pending_irq(sh4, "sh4_set_info"); - break; - case CPUINFO_INT_REGISTER + SH4_GBR: sh4->gbr = info->i; break; - case CPUINFO_INT_REGISTER + SH4_VBR: sh4->vbr = info->i; break; - case CPUINFO_INT_REGISTER + SH4_DBR: sh4->dbr = info->i; break; - case CPUINFO_INT_REGISTER + SH4_MACH: sh4->mach = info->i; break; - case CPUINFO_INT_REGISTER + SH4_MACL: sh4->macl = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R0: sh4->r[ 0] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R1: sh4->r[ 1] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R2: sh4->r[ 2] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R3: sh4->r[ 3] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R4: sh4->r[ 4] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R5: sh4->r[ 5] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R6: sh4->r[ 6] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R7: sh4->r[ 7] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R8: sh4->r[ 8] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R9: sh4->r[ 9] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R10: sh4->r[10] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R11: sh4->r[11] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R12: sh4->r[12] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R13: sh4->r[13] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R14: sh4->r[14] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_R15: sh4->r[15] = info->i; break; - case CPUINFO_INT_REGISTER + SH4_EA: sh4->ea = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R0_BK0: sh4->rbnk[0][0] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R1_BK0: sh4->rbnk[0][1] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R2_BK0: sh4->rbnk[0][2] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R3_BK0: sh4->rbnk[0][3] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R4_BK0: sh4->rbnk[0][4] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R5_BK0: sh4->rbnk[0][5] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R6_BK0: sh4->rbnk[0][6] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R7_BK0: sh4->rbnk[0][7] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R0_BK1: sh4->rbnk[1][0] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R1_BK1: sh4->rbnk[1][1] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R2_BK1: sh4->rbnk[1][2] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R3_BK1: sh4->rbnk[1][3] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R4_BK1: sh4->rbnk[1][4] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R5_BK1: sh4->rbnk[1][5] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R6_BK1: sh4->rbnk[1][6] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_R7_BK1: sh4->rbnk[1][7] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_SPC: sh4->spc = info->i; break; - case CPUINFO_STR_REGISTER + SH4_SSR: sh4->ssr = info->i; break; - case CPUINFO_STR_REGISTER + SH4_SGR: sh4->sgr = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FPSCR: sh4->fpscr = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FPUL: sh4->fpul = info->i; break; -#ifdef LSB_FIRST - case CPUINFO_STR_REGISTER + SH4_FR0: sh4->fr[ 0 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR1: sh4->fr[ 1 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR2: sh4->fr[ 2 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR3: sh4->fr[ 3 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR4: sh4->fr[ 4 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR5: sh4->fr[ 5 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR6: sh4->fr[ 6 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR7: sh4->fr[ 7 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR8: sh4->fr[ 8 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR9: sh4->fr[ 9 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR10: sh4->fr[10 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR11: sh4->fr[11 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR12: sh4->fr[12 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR13: sh4->fr[13 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR14: sh4->fr[14 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR15: sh4->fr[15 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF0: sh4->xf[ 0 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF1: sh4->xf[ 1 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF2: sh4->xf[ 2 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF3: sh4->xf[ 3 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF4: sh4->xf[ 4 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF5: sh4->xf[ 5 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF6: sh4->xf[ 6 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF7: sh4->xf[ 7 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF8: sh4->xf[ 8 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF9: sh4->xf[ 9 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF10: sh4->xf[10 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF11: sh4->xf[11 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF12: sh4->xf[12 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF13: sh4->xf[13 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF14: sh4->xf[14 ^ sh4->fpu_pr] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF15: sh4->xf[15 ^ sh4->fpu_pr] = info->i; break; -#else - case CPUINFO_STR_REGISTER + SH4_FR0: sh4->fr[ 0] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR1: sh4->fr[ 1] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR2: sh4->fr[ 2] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR3: sh4->fr[ 3] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR4: sh4->fr[ 4] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR5: sh4->fr[ 5] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR6: sh4->fr[ 6] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR7: sh4->fr[ 7] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR8: sh4->fr[ 8] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR9: sh4->fr[ 9] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR10: sh4->fr[10] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR11: sh4->fr[11] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR12: sh4->fr[12] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR13: sh4->fr[13] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR14: sh4->fr[14] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_FR15: sh4->fr[15] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF0: sh4->xf[ 0] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF1: sh4->xf[ 1] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF2: sh4->xf[ 2] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF3: sh4->xf[ 3] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF4: sh4->xf[ 4] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF5: sh4->xf[ 5] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF6: sh4->xf[ 6] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF7: sh4->xf[ 7] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF8: sh4->xf[ 8] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF9: sh4->xf[ 9] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF10: sh4->xf[10] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF11: sh4->xf[11] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF12: sh4->xf[12] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF13: sh4->xf[13] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF14: sh4->xf[14] = info->i; break; - case CPUINFO_STR_REGISTER + SH4_XF15: sh4->xf[15] = info->i; break; -#endif + m_sh4_icount = 0; + return; } + + do + { + if (m_delay) + { + const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_delay & AM), WORD_XOR_LE(6)); + + debugger_instruction_hook(this, m_delay & AM); + + m_delay = 0; + m_ppc = m_pc; + + (this->*s_master_ophandler_table[opcode])(opcode); + + + if (m_test_irq && !m_delay) + { + sh4_check_pending_irq("mame_sh4_execute"); + } + + + } + else + { + const UINT16 opcode = m_direct->read_decrypted_word((UINT32)(m_pc & AM), WORD_XOR_LE(6)); + + debugger_instruction_hook(this, m_pc & AM); + + m_pc += 2; + m_ppc = m_pc; + + (this->*s_master_ophandler_table[opcode])(opcode); + + if (m_test_irq && !m_delay) + { + sh4_check_pending_irq("mame_sh4_execute"); + } + } + + m_sh4_icount--; + } while( m_sh4_icount > 0 ); } -void sh4_set_ftcsr_callback(device_t *device, sh4_ftcsr_callback callback) +void sh34_base_device::device_start() { - sh4_state *sh4 = get_safe_token(device); - sh4->ftcsr_read_callback = callback; + for (int i=0; i<3; i++) + { + m_timer[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh34_base_device::sh4_timer_callback), this)); + m_timer[i]->adjust(attotime::never, i); + } + + for (int i=0; i<4; i++) + { + m_dma_timer[i] = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh34_base_device::sh4_dmac_callback), this)); + m_dma_timer[i]->adjust(attotime::never, i); + } + + m_refresh_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh34_base_device::sh4_refresh_timer_callback), this)); + m_refresh_timer->adjust(attotime::never); + m_refresh_timer_base = 0; + + m_rtc_timer = machine().scheduler().timer_alloc(timer_expired_delegate(FUNC(sh34_base_device::sh4_rtc_timer_callback), this)); + m_rtc_timer->adjust(attotime::never); + + sh4_parse_configuration(); + + m_internal = &space(AS_PROGRAM); + m_program = &space(AS_PROGRAM); + m_io = &space(AS_IO); + m_direct = &m_program->direct(); + sh4_default_exception_priorities(); + m_irln = 15; + m_test_irq = 0; + + save_item(NAME(m_pc)); + save_item(NAME(m_r[15])); + save_item(NAME(m_sr)); + save_item(NAME(m_pr)); + save_item(NAME(m_gbr)); + save_item(NAME(m_vbr)); + save_item(NAME(m_mach)); + save_item(NAME(m_macl)); + save_item(NAME(m_spc)); + save_item(NAME(m_ssr)); + save_item(NAME(m_sgr)); + save_item(NAME(m_fpscr)); + save_item(NAME(m_r[ 0])); + save_item(NAME(m_r[ 1])); + save_item(NAME(m_r[ 2])); + save_item(NAME(m_r[ 3])); + save_item(NAME(m_r[ 4])); + save_item(NAME(m_r[ 5])); + save_item(NAME(m_r[ 6])); + save_item(NAME(m_r[ 7])); + save_item(NAME(m_r[ 8])); + save_item(NAME(m_r[ 9])); + save_item(NAME(m_r[10])); + save_item(NAME(m_r[11])); + save_item(NAME(m_r[12])); + save_item(NAME(m_r[13])); + save_item(NAME(m_r[14])); + save_item(NAME(m_fr[ 0])); + save_item(NAME(m_fr[ 1])); + save_item(NAME(m_fr[ 2])); + save_item(NAME(m_fr[ 3])); + save_item(NAME(m_fr[ 4])); + save_item(NAME(m_fr[ 5])); + save_item(NAME(m_fr[ 6])); + save_item(NAME(m_fr[ 7])); + save_item(NAME(m_fr[ 8])); + save_item(NAME(m_fr[ 9])); + save_item(NAME(m_fr[10])); + save_item(NAME(m_fr[11])); + save_item(NAME(m_fr[12])); + save_item(NAME(m_fr[13])); + save_item(NAME(m_fr[14])); + save_item(NAME(m_fr[15])); + save_item(NAME(m_xf[ 0])); + save_item(NAME(m_xf[ 1])); + save_item(NAME(m_xf[ 2])); + save_item(NAME(m_xf[ 3])); + save_item(NAME(m_xf[ 4])); + save_item(NAME(m_xf[ 5])); + save_item(NAME(m_xf[ 6])); + save_item(NAME(m_xf[ 7])); + save_item(NAME(m_xf[ 8])); + save_item(NAME(m_xf[ 9])); + save_item(NAME(m_xf[10])); + save_item(NAME(m_xf[11])); + save_item(NAME(m_xf[12])); + save_item(NAME(m_xf[13])); + save_item(NAME(m_xf[14])); + save_item(NAME(m_xf[15])); + save_item(NAME(m_ea)); + save_item(NAME(m_fpul)); + save_item(NAME(m_dbr)); + save_item(NAME(m_exception_priority)); + save_item(NAME(m_exception_requesting)); + + save_item(NAME(m_SH4_TSTR)); + save_item(NAME(m_SH4_TCNT0)); + save_item(NAME(m_SH4_TCNT1)); + save_item(NAME(m_SH4_TCNT2)); + save_item(NAME(m_SH4_TCR0)); + save_item(NAME(m_SH4_TCR1)); + save_item(NAME(m_SH4_TCR2)); + save_item(NAME(m_SH4_TCOR0)); + save_item(NAME(m_SH4_TCOR1)); + save_item(NAME(m_SH4_TCOR2)); + save_item(NAME(m_SH4_TOCR)); + save_item(NAME(m_SH4_TCPR2)); + + save_item(NAME(m_SH4_IPRA)); + + save_item(NAME(m_SH4_IPRC)); + + // Debugger state + + state_add(SH4_PC, "PC", m_pc).formatstr("%08X").callimport(); + state_add(SH4_SR, "SR", m_sr).formatstr("%08X").callimport(); + state_add(SH4_PR, "PR", m_pr).formatstr("%08X"); + state_add(SH4_GBR, "GBR", m_gbr).formatstr("%08X"); + state_add(SH4_VBR, "VBR", m_vbr).formatstr("%08X"); + state_add(SH4_DBR, "DBR", m_dbr).formatstr("%08X"); + state_add(SH4_MACH, "MACH", m_mach).formatstr("%08X"); + state_add(SH4_MACL, "MACL", m_macl).formatstr("%08X"); + state_add(SH4_R0, "R0", m_r[ 0]).formatstr("%08X"); + state_add(SH4_R1, "R1", m_r[ 1]).formatstr("%08X"); + state_add(SH4_R2, "R2", m_r[ 2]).formatstr("%08X"); + state_add(SH4_R3, "R3", m_r[ 3]).formatstr("%08X"); + state_add(SH4_R4, "R4", m_r[ 4]).formatstr("%08X"); + state_add(SH4_R5, "R5", m_r[ 5]).formatstr("%08X"); + state_add(SH4_R6, "R6", m_r[ 6]).formatstr("%08X"); + state_add(SH4_R7, "R7", m_r[ 7]).formatstr("%08X"); + state_add(SH4_R8, "R8", m_r[ 8]).formatstr("%08X"); + state_add(SH4_R9, "R9", m_r[ 9]).formatstr("%08X"); + state_add(SH4_R10, "R10", m_r[10]).formatstr("%08X"); + state_add(SH4_R11, "R11", m_r[11]).formatstr("%08X"); + state_add(SH4_R12, "R12", m_r[12]).formatstr("%08X"); + state_add(SH4_R13, "R13", m_r[13]).formatstr("%08X"); + state_add(SH4_R14, "R14", m_r[14]).formatstr("%08X"); + state_add(SH4_R15, "R15", m_r[15]).formatstr("%08X"); + state_add(SH4_EA, "EA", m_ea).formatstr("%08X"); + state_add(SH4_R0_BK0, "R0 BK 0", m_rbnk[0][0]).formatstr("%08X"); + state_add(SH4_R1_BK0, "R1 BK 0", m_rbnk[0][1]).formatstr("%08X"); + state_add(SH4_R2_BK0, "R2 BK 0", m_rbnk[0][2]).formatstr("%08X"); + state_add(SH4_R3_BK0, "R3 BK 0", m_rbnk[0][3]).formatstr("%08X"); + state_add(SH4_R4_BK0, "R4 BK 0", m_rbnk[0][4]).formatstr("%08X"); + state_add(SH4_R5_BK0, "R5 BK 0", m_rbnk[0][5]).formatstr("%08X"); + state_add(SH4_R6_BK0, "R6 BK 0", m_rbnk[0][6]).formatstr("%08X"); + state_add(SH4_R7_BK0, "R7 BK 0", m_rbnk[0][7]).formatstr("%08X"); + state_add(SH4_R0_BK1, "R0 BK 1", m_rbnk[1][0]).formatstr("%08X"); + state_add(SH4_R1_BK1, "R1 BK 1", m_rbnk[1][1]).formatstr("%08X"); + state_add(SH4_R2_BK1, "R2 BK 1", m_rbnk[1][2]).formatstr("%08X"); + state_add(SH4_R3_BK1, "R3 BK 1", m_rbnk[1][3]).formatstr("%08X"); + state_add(SH4_R4_BK1, "R4 BK 1", m_rbnk[1][4]).formatstr("%08X"); + state_add(SH4_R5_BK1, "R5 BK 1", m_rbnk[1][5]).formatstr("%08X"); + state_add(SH4_R6_BK1, "R6 BK 1", m_rbnk[1][6]).formatstr("%08X"); + state_add(SH4_R7_BK1, "R7 BK 1", m_rbnk[1][7]).formatstr("%08X"); + state_add(SH4_SPC, "SPC", m_spc).formatstr("%08X"); + state_add(SH4_SSR, "SSR", m_ssr).formatstr("%08X"); + state_add(SH4_SGR, "SGR", m_sgr).formatstr("%08X"); + state_add(SH4_FPSCR, "FPSCR", m_fpscr).formatstr("%08X"); + state_add(SH4_FPUL, "FPUL", m_fpul).formatstr("%08X"); + + state_add(SH4_FR0, "FR0", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR1, "FR1", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR2, "FR2", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR3, "FR3", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR4, "FR4", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR5, "FR5", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR6, "FR6", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR7, "FR7", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR8, "FR8", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR9, "FR9", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR10, "FR10", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR11, "FR11", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR12, "FR12", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR13, "FR13", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR14, "FR14", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_FR15, "FR15", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF0, "XF0", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF1, "XF1", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF2, "XF2", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF3, "XF3", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF4, "XF4", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF5, "XF5", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF6, "XF6", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF7, "XF7", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF8, "XF8", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF9, "XF9", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF10, "XF10", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF11, "XF11", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF12, "XF12", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF13, "XF13", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF14, "XF14", m_debugger_temp).callimport().formatstr("%25s"); + state_add(SH4_XF15, "XF15", m_debugger_temp).callimport().formatstr("%25s"); + + state_add(STATE_GENPC, "GENPC", m_debugger_temp).callimport().callexport().noshow(); + state_add(STATE_GENSP, "GENSP", m_r[15]).noshow(); + state_add(STATE_GENPCBASE, "GENPCBASE", m_ppc).noshow(); + state_add(STATE_GENFLAGS, "GENFLAGS", m_sr).formatstr("%20s").noshow(); + + m_icountptr = &m_sh4_icount; } - -#if 0 -/*When OC index mode is off (CCR.OIX = 0)*/ -static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64, sh4_device ) - AM_RANGE(0x1C000000, 0x1C000FFF) AM_RAM AM_MIRROR(0x03FFD000) - AM_RANGE(0x1C002000, 0x1C002FFF) AM_RAM AM_MIRROR(0x03FFD000) - AM_RANGE(0xE0000000, 0xE000003F) AM_RAM AM_MIRROR(0x03FFFFC0) -ADDRESS_MAP_END +void sh34_base_device::state_import(const device_state_entry &entry) +{ +#ifdef LSB_FIRST + UINT8 fpu_xor = m_fpu_pr; +#else + UINT8 fpu_xor = 0; #endif -/*When OC index mode is on (CCR.OIX = 1)*/ -static ADDRESS_MAP_START( sh4_internal_map, AS_PROGRAM, 64, sh4_device ) - AM_RANGE(0x1C000000, 0x1C000FFF) AM_RAM AM_MIRROR(0x01FFF000) - AM_RANGE(0x1E000000, 0x1E000FFF) AM_RAM AM_MIRROR(0x01FFF000) - AM_RANGE(0xE0000000, 0xE000003F) AM_RAM AM_MIRROR(0x03FFFFC0) // todo: store queues should be write only on DC's SH4, executing PREFM shouldn't cause an actual memory read access! - AM_RANGE(0xF6000000, 0xF7FFFFFF) AM_READWRITE(sh4_tlb_r,sh4_tlb_w) - AM_RANGE(0xFE000000, 0xFFFFFFFF) AM_READWRITE32(sh4_internal_r, sh4_internal_w, U64(0xffffffffffffffff)) -ADDRESS_MAP_END - -static ADDRESS_MAP_START( sh3_internal_map, AS_PROGRAM, 64, sh3_device ) - AM_RANGE(SH3_LOWER_REGBASE, SH3_LOWER_REGEND) AM_READWRITE32(sh3_internal_r, sh3_internal_w, U64(0xffffffffffffffff)) - AM_RANGE(SH3_UPPER_REGBASE, SH3_UPPER_REGEND) AM_READWRITE32(sh3_internal_high_r, sh3_internal_high_w, U64(0xffffffffffffffff)) -ADDRESS_MAP_END - - -/************************************************************************** - * Generic get_info - **************************************************************************/ - -CPU_GET_INFO( sh4 ) -{ - sh4_state *sh4 = (device != NULL && device->token() != NULL) ? get_safe_token(device) : NULL; - - switch (state) + switch (entry.index()) { - /* --- the following bits of info are returned as 64-bit signed integers --- */ - case CPUINFO_INT_CONTEXT_SIZE: info->i = sizeof(sh4_state); break; - case CPUINFO_INT_INPUT_LINES: info->i = 5; break; - case CPUINFO_INT_DEFAULT_IRQ_VECTOR: info->i = 0; break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_LITTLE; break; - case CPUINFO_INT_CLOCK_MULTIPLIER: info->i = 1; break; - case CPUINFO_INT_CLOCK_DIVIDER: info->i = 1; break; - case CPUINFO_INT_MIN_INSTRUCTION_BYTES: info->i = 2; break; - case CPUINFO_INT_MAX_INSTRUCTION_BYTES: info->i = 2; break; - case CPUINFO_INT_MIN_CYCLES: info->i = 1; break; - case CPUINFO_INT_MAX_CYCLES: info->i = 4; break; - - case CPUINFO_INT_DATABUS_WIDTH + AS_PROGRAM: info->i = 64; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_PROGRAM: info->i = 32; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_PROGRAM: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_DATA: info->i = 0; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_DATA: info->i = 0; break; - case CPUINFO_INT_DATABUS_WIDTH + AS_IO: info->i = 64; break; - case CPUINFO_INT_ADDRBUS_WIDTH + AS_IO: info->i = 8; break; - case CPUINFO_INT_ADDRBUS_SHIFT + AS_IO: info->i = 0; break; - - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map64 = ADDRESS_MAP_NAME(sh4_internal_map); break; - - case CPUINFO_INT_INPUT_STATE + SH4_IRL0: info->i = sh4->irq_line_state[SH4_IRL0]; break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL1: info->i = sh4->irq_line_state[SH4_IRL1]; break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL2: info->i = sh4->irq_line_state[SH4_IRL2]; break; - case CPUINFO_INT_INPUT_STATE + SH4_IRL3: info->i = sh4->irq_line_state[SH4_IRL3]; break; - case CPUINFO_INT_INPUT_STATE + INPUT_LINE_NMI: info->i = sh4->nmi_line_state; break; - - case CPUINFO_INT_PREVIOUSPC: info->i = sh4->ppc; break; - - case CPUINFO_INT_PC: - case CPUINFO_INT_REGISTER + SH4_PC: info->i = (sh4->delay) ? (sh4->delay & AM) : (sh4->pc & AM); break; - case CPUINFO_INT_SP: info->i = sh4->r[15]; break; - case CPUINFO_INT_REGISTER + SH4_PR: info->i = sh4->pr; break; - case CPUINFO_INT_REGISTER + SH4_SR: info->i = sh4->sr; break; - case CPUINFO_INT_REGISTER + SH4_GBR: info->i = sh4->gbr; break; - case CPUINFO_INT_REGISTER + SH4_VBR: info->i = sh4->vbr; break; - case CPUINFO_INT_REGISTER + SH4_DBR: info->i = sh4->dbr; break; - case CPUINFO_INT_REGISTER + SH4_MACH: info->i = sh4->mach; break; - case CPUINFO_INT_REGISTER + SH4_MACL: info->i = sh4->macl; break; - case CPUINFO_INT_REGISTER + SH4_R0: info->i = sh4->r[ 0]; break; - case CPUINFO_INT_REGISTER + SH4_R1: info->i = sh4->r[ 1]; break; - case CPUINFO_INT_REGISTER + SH4_R2: info->i = sh4->r[ 2]; break; - case CPUINFO_INT_REGISTER + SH4_R3: info->i = sh4->r[ 3]; break; - case CPUINFO_INT_REGISTER + SH4_R4: info->i = sh4->r[ 4]; break; - case CPUINFO_INT_REGISTER + SH4_R5: info->i = sh4->r[ 5]; break; - case CPUINFO_INT_REGISTER + SH4_R6: info->i = sh4->r[ 6]; break; - case CPUINFO_INT_REGISTER + SH4_R7: info->i = sh4->r[ 7]; break; - case CPUINFO_INT_REGISTER + SH4_R8: info->i = sh4->r[ 8]; break; - case CPUINFO_INT_REGISTER + SH4_R9: info->i = sh4->r[ 9]; break; - case CPUINFO_INT_REGISTER + SH4_R10: info->i = sh4->r[10]; break; - case CPUINFO_INT_REGISTER + SH4_R11: info->i = sh4->r[11]; break; - case CPUINFO_INT_REGISTER + SH4_R12: info->i = sh4->r[12]; break; - case CPUINFO_INT_REGISTER + SH4_R13: info->i = sh4->r[13]; break; - case CPUINFO_INT_REGISTER + SH4_R14: info->i = sh4->r[14]; break; - case CPUINFO_INT_REGISTER + SH4_R15: info->i = sh4->r[15]; break; - case CPUINFO_INT_REGISTER + SH4_EA: info->i = sh4->ea; break; - - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_SET_INFO: info->setinfo = CPU_SET_INFO_NAME(sh4); break; - case CPUINFO_FCT_INIT: info->init = CPU_INIT_NAME(sh4); break; - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sh4); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(sh4); break; - case CPUINFO_FCT_BURN: info->burn = NULL; break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sh4); break; - case CPUINFO_PTR_INSTRUCTION_COUNTER: info->icount = &sh4->sh4_icount; break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "SH-4 (little)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "sh4"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Hitachi SH7750"); break; - case CPUINFO_STR_VERSION: strcpy(info->s, "1.0"); break; - case CPUINFO_STR_SOURCE_FILE: strcpy(info->s, __FILE__); break; - case CPUINFO_STR_CREDITS: strcpy(info->s, "Copyright R. Belmont"); break; - - case CPUINFO_STR_FLAGS: - sprintf(info->s, "%s%s%s%s%c%c%d%c%c", - sh4->sr & MD ? "MD ":" ", - sh4->sr & sRB ? "RB ":" ", - sh4->sr & BL ? "BL ":" ", - sh4->sr & FD ? "FD ":" ", - sh4->sr & M ? 'M':'.', - sh4->sr & Q ? 'Q':'.', - (sh4->sr & I) >> 4, - sh4->sr & S ? 'S':'.', - sh4->sr & T ? 'T':'.'); + case STATE_GENPC: + m_pc = m_debugger_temp; + case SH4_PC: + m_delay = 0; break; - case CPUINFO_STR_REGISTER + SH4_PC: sprintf(info->s, "PC :%08X", sh4->pc); break; - case CPUINFO_STR_REGISTER + SH4_SR: sprintf(info->s, "SR :%08X", sh4->sr); break; - case CPUINFO_STR_REGISTER + SH4_PR: sprintf(info->s, "PR :%08X", sh4->pr); break; - case CPUINFO_STR_REGISTER + SH4_GBR: sprintf(info->s, "GBR :%08X", sh4->gbr); break; - case CPUINFO_STR_REGISTER + SH4_VBR: sprintf(info->s, "VBR :%08X", sh4->vbr); break; - case CPUINFO_STR_REGISTER + SH4_DBR: sprintf(info->s, "DBR :%08X", sh4->dbr); break; - case CPUINFO_STR_REGISTER + SH4_MACH: sprintf(info->s, "MACH:%08X", sh4->mach); break; - case CPUINFO_STR_REGISTER + SH4_MACL: sprintf(info->s, "MACL:%08X", sh4->macl); break; - case CPUINFO_STR_REGISTER + SH4_R0: sprintf(info->s, "R0 :%08X", sh4->r[ 0]); break; - case CPUINFO_STR_REGISTER + SH4_R1: sprintf(info->s, "R1 :%08X", sh4->r[ 1]); break; - case CPUINFO_STR_REGISTER + SH4_R2: sprintf(info->s, "R2 :%08X", sh4->r[ 2]); break; - case CPUINFO_STR_REGISTER + SH4_R3: sprintf(info->s, "R3 :%08X", sh4->r[ 3]); break; - case CPUINFO_STR_REGISTER + SH4_R4: sprintf(info->s, "R4 :%08X", sh4->r[ 4]); break; - case CPUINFO_STR_REGISTER + SH4_R5: sprintf(info->s, "R5 :%08X", sh4->r[ 5]); break; - case CPUINFO_STR_REGISTER + SH4_R6: sprintf(info->s, "R6 :%08X", sh4->r[ 6]); break; - case CPUINFO_STR_REGISTER + SH4_R7: sprintf(info->s, "R7 :%08X", sh4->r[ 7]); break; - case CPUINFO_STR_REGISTER + SH4_R8: sprintf(info->s, "R8 :%08X", sh4->r[ 8]); break; - case CPUINFO_STR_REGISTER + SH4_R9: sprintf(info->s, "R9 :%08X", sh4->r[ 9]); break; - case CPUINFO_STR_REGISTER + SH4_R10: sprintf(info->s, "R10 :%08X", sh4->r[10]); break; - case CPUINFO_STR_REGISTER + SH4_R11: sprintf(info->s, "R11 :%08X", sh4->r[11]); break; - case CPUINFO_STR_REGISTER + SH4_R12: sprintf(info->s, "R12 :%08X", sh4->r[12]); break; - case CPUINFO_STR_REGISTER + SH4_R13: sprintf(info->s, "R13 :%08X", sh4->r[13]); break; - case CPUINFO_STR_REGISTER + SH4_R14: sprintf(info->s, "R14 :%08X", sh4->r[14]); break; - case CPUINFO_STR_REGISTER + SH4_R15: sprintf(info->s, "R15 :%08X", sh4->r[15]); break; - case CPUINFO_STR_REGISTER + SH4_EA: sprintf(info->s, "EA :%08X", sh4->ea); break; - case CPUINFO_STR_REGISTER + SH4_R0_BK0: sprintf(info->s, "R0 BK 0 :%08X", sh4->rbnk[0][0]); break; - case CPUINFO_STR_REGISTER + SH4_R1_BK0: sprintf(info->s, "R1 BK 0 :%08X", sh4->rbnk[0][1]); break; - case CPUINFO_STR_REGISTER + SH4_R2_BK0: sprintf(info->s, "R2 BK 0 :%08X", sh4->rbnk[0][2]); break; - case CPUINFO_STR_REGISTER + SH4_R3_BK0: sprintf(info->s, "R3 BK 0 :%08X", sh4->rbnk[0][3]); break; - case CPUINFO_STR_REGISTER + SH4_R4_BK0: sprintf(info->s, "R4 BK 0 :%08X", sh4->rbnk[0][4]); break; - case CPUINFO_STR_REGISTER + SH4_R5_BK0: sprintf(info->s, "R5 BK 0 :%08X", sh4->rbnk[0][5]); break; - case CPUINFO_STR_REGISTER + SH4_R6_BK0: sprintf(info->s, "R6 BK 0 :%08X", sh4->rbnk[0][6]); break; - case CPUINFO_STR_REGISTER + SH4_R7_BK0: sprintf(info->s, "R7 BK 0 :%08X", sh4->rbnk[0][7]); break; - case CPUINFO_STR_REGISTER + SH4_R0_BK1: sprintf(info->s, "R0 BK 1 :%08X", sh4->rbnk[1][0]); break; - case CPUINFO_STR_REGISTER + SH4_R1_BK1: sprintf(info->s, "R1 BK 1 :%08X", sh4->rbnk[1][1]); break; - case CPUINFO_STR_REGISTER + SH4_R2_BK1: sprintf(info->s, "R2 BK 1 :%08X", sh4->rbnk[1][2]); break; - case CPUINFO_STR_REGISTER + SH4_R3_BK1: sprintf(info->s, "R3 BK 1 :%08X", sh4->rbnk[1][3]); break; - case CPUINFO_STR_REGISTER + SH4_R4_BK1: sprintf(info->s, "R4 BK 1 :%08X", sh4->rbnk[1][4]); break; - case CPUINFO_STR_REGISTER + SH4_R5_BK1: sprintf(info->s, "R5 BK 1 :%08X", sh4->rbnk[1][5]); break; - case CPUINFO_STR_REGISTER + SH4_R6_BK1: sprintf(info->s, "R6 BK 1 :%08X", sh4->rbnk[1][6]); break; - case CPUINFO_STR_REGISTER + SH4_R7_BK1: sprintf(info->s, "R7 BK 1 :%08X", sh4->rbnk[1][7]); break; - case CPUINFO_STR_REGISTER + SH4_SPC: sprintf(info->s, "SPC :%08X", sh4->spc); break; - case CPUINFO_STR_REGISTER + SH4_SSR: sprintf(info->s, "SSR :%08X", sh4->ssr); break; - case CPUINFO_STR_REGISTER + SH4_SGR: sprintf(info->s, "SGR :%08X", sh4->sgr); break; - case CPUINFO_STR_REGISTER + SH4_FPSCR: sprintf(info->s, "FPSCR :%08X", sh4->fpscr); break; - case CPUINFO_STR_REGISTER + SH4_FPUL: sprintf(info->s, "FPUL :%08X", sh4->fpul); break; + case SH4_SR: + sh4_exception_recompute(); + sh4_check_pending_irq("sh4_set_info"); + break; + + case SH4_FR0: + m_fr[0 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR1: + m_fr[1 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR2: + m_fr[2 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR3: + m_fr[3 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR4: + m_fr[4 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR5: + m_fr[5 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR6: + m_fr[6 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR7: + m_fr[7 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR8: + m_fr[8 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR9: + m_fr[9 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR10: + m_fr[10 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR11: + m_fr[11 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR12: + m_fr[12 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR13: + m_fr[13 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR14: + m_fr[14 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_FR15: + m_fr[15 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF0: + m_xf[0 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF1: + m_xf[1 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF2: + m_xf[2 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF3: + m_xf[3 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF4: + m_xf[4 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF5: + m_xf[5 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF6: + m_xf[6 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF7: + m_xf[7 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF8: + m_xf[8 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF9: + m_xf[9 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF10: + m_xf[10 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF11: + m_xf[11 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF12: + m_xf[12 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF13: + m_xf[13 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF14: + m_xf[14 ^ fpu_xor] = m_debugger_temp; + break; + + case SH4_XF15: + m_xf[15 ^ fpu_xor] = m_debugger_temp; + break; + } +} + +void sh34_base_device::state_export(const device_state_entry &entry) +{ + switch (entry.index()) + { + case STATE_GENPC: + m_debugger_temp = (m_delay) ? (m_delay & AM) : (m_pc & AM); + break; + } +} + +void sh34_base_device::state_string_export(const device_state_entry &entry, astring &string) +{ #ifdef LSB_FIRST - case CPUINFO_STR_REGISTER + SH4_FR0: sprintf(info->s, "FR0 :%08X %f", FP_RS2( 0),(double)FP_RFS2( 0)); break; - case CPUINFO_STR_REGISTER + SH4_FR1: sprintf(info->s, "FR1 :%08X %f", FP_RS2( 1),(double)FP_RFS2( 1)); break; - case CPUINFO_STR_REGISTER + SH4_FR2: sprintf(info->s, "FR2 :%08X %f", FP_RS2( 2),(double)FP_RFS2( 2)); break; - case CPUINFO_STR_REGISTER + SH4_FR3: sprintf(info->s, "FR3 :%08X %f", FP_RS2( 3),(double)FP_RFS2( 3)); break; - case CPUINFO_STR_REGISTER + SH4_FR4: sprintf(info->s, "FR4 :%08X %f", FP_RS2( 4),(double)FP_RFS2( 4)); break; - case CPUINFO_STR_REGISTER + SH4_FR5: sprintf(info->s, "FR5 :%08X %f", FP_RS2( 5),(double)FP_RFS2( 5)); break; - case CPUINFO_STR_REGISTER + SH4_FR6: sprintf(info->s, "FR6 :%08X %f", FP_RS2( 6),(double)FP_RFS2( 6)); break; - case CPUINFO_STR_REGISTER + SH4_FR7: sprintf(info->s, "FR7 :%08X %f", FP_RS2( 7),(double)FP_RFS2( 7)); break; - case CPUINFO_STR_REGISTER + SH4_FR8: sprintf(info->s, "FR8 :%08X %f", FP_RS2( 8),(double)FP_RFS2( 8)); break; - case CPUINFO_STR_REGISTER + SH4_FR9: sprintf(info->s, "FR9 :%08X %f", FP_RS2( 9),(double)FP_RFS2( 9)); break; - case CPUINFO_STR_REGISTER + SH4_FR10: sprintf(info->s, "FR10 :%08X %f", FP_RS2(10),(double)FP_RFS2(10)); break; - case CPUINFO_STR_REGISTER + SH4_FR11: sprintf(info->s, "FR11 :%08X %f", FP_RS2(11),(double)FP_RFS2(11)); break; - case CPUINFO_STR_REGISTER + SH4_FR12: sprintf(info->s, "FR12 :%08X %f", FP_RS2(12),(double)FP_RFS2(12)); break; - case CPUINFO_STR_REGISTER + SH4_FR13: sprintf(info->s, "FR13 :%08X %f", FP_RS2(13),(double)FP_RFS2(13)); break; - case CPUINFO_STR_REGISTER + SH4_FR14: sprintf(info->s, "FR14 :%08X %f", FP_RS2(14),(double)FP_RFS2(14)); break; - case CPUINFO_STR_REGISTER + SH4_FR15: sprintf(info->s, "FR15 :%08X %f", FP_RS2(15),(double)FP_RFS2(15)); break; - case CPUINFO_STR_REGISTER + SH4_XF0: sprintf(info->s, "XF0 :%08X %f", FP_XS2( 0),(double)FP_XFS2( 0)); break; - case CPUINFO_STR_REGISTER + SH4_XF1: sprintf(info->s, "XF1 :%08X %f", FP_XS2( 1),(double)FP_XFS2( 1)); break; - case CPUINFO_STR_REGISTER + SH4_XF2: sprintf(info->s, "XF2 :%08X %f", FP_XS2( 2),(double)FP_XFS2( 2)); break; - case CPUINFO_STR_REGISTER + SH4_XF3: sprintf(info->s, "XF3 :%08X %f", FP_XS2( 3),(double)FP_XFS2( 3)); break; - case CPUINFO_STR_REGISTER + SH4_XF4: sprintf(info->s, "XF4 :%08X %f", FP_XS2( 4),(double)FP_XFS2( 4)); break; - case CPUINFO_STR_REGISTER + SH4_XF5: sprintf(info->s, "XF5 :%08X %f", FP_XS2( 5),(double)FP_XFS2( 5)); break; - case CPUINFO_STR_REGISTER + SH4_XF6: sprintf(info->s, "XF6 :%08X %f", FP_XS2( 6),(double)FP_XFS2( 6)); break; - case CPUINFO_STR_REGISTER + SH4_XF7: sprintf(info->s, "XF7 :%08X %f", FP_XS2( 7),(double)FP_XFS2( 7)); break; - case CPUINFO_STR_REGISTER + SH4_XF8: sprintf(info->s, "XF8 :%08X %f", FP_XS2( 8),(double)FP_XFS2( 8)); break; - case CPUINFO_STR_REGISTER + SH4_XF9: sprintf(info->s, "XF9 :%08X %f", FP_XS2( 9),(double)FP_XFS2( 9)); break; - case CPUINFO_STR_REGISTER + SH4_XF10: sprintf(info->s, "XF10 :%08X %f", FP_XS2(10),(double)FP_XFS2(10)); break; - case CPUINFO_STR_REGISTER + SH4_XF11: sprintf(info->s, "XF11 :%08X %f", FP_XS2(11),(double)FP_XFS2(11)); break; - case CPUINFO_STR_REGISTER + SH4_XF12: sprintf(info->s, "XF12 :%08X %f", FP_XS2(12),(double)FP_XFS2(12)); break; - case CPUINFO_STR_REGISTER + SH4_XF13: sprintf(info->s, "XF13 :%08X %f", FP_XS2(13),(double)FP_XFS2(13)); break; - case CPUINFO_STR_REGISTER + SH4_XF14: sprintf(info->s, "XF14 :%08X %f", FP_XS2(14),(double)FP_XFS2(14)); break; - case CPUINFO_STR_REGISTER + SH4_XF15: sprintf(info->s, "XF15 :%08X %f", FP_XS2(15),(double)FP_XFS2(15)); break; + UINT8 fpu_xor = m_fpu_pr; #else - case CPUINFO_STR_REGISTER + SH4_FR0: sprintf(info->s, "FR0 :%08X %f", FP_RS( 0),(double)FP_RFS( 0)); break; - case CPUINFO_STR_REGISTER + SH4_FR1: sprintf(info->s, "FR1 :%08X %f", FP_RS( 1),(double)FP_RFS( 1)); break; - case CPUINFO_STR_REGISTER + SH4_FR2: sprintf(info->s, "FR2 :%08X %f", FP_RS( 2),(double)FP_RFS( 2)); break; - case CPUINFO_STR_REGISTER + SH4_FR3: sprintf(info->s, "FR3 :%08X %f", FP_RS( 3),(double)FP_RFS( 3)); break; - case CPUINFO_STR_REGISTER + SH4_FR4: sprintf(info->s, "FR4 :%08X %f", FP_RS( 4),(double)FP_RFS( 4)); break; - case CPUINFO_STR_REGISTER + SH4_FR5: sprintf(info->s, "FR5 :%08X %f", FP_RS( 5),(double)FP_RFS( 5)); break; - case CPUINFO_STR_REGISTER + SH4_FR6: sprintf(info->s, "FR6 :%08X %f", FP_RS( 6),(double)FP_RFS( 6)); break; - case CPUINFO_STR_REGISTER + SH4_FR7: sprintf(info->s, "FR7 :%08X %f", FP_RS( 7),(double)FP_RFS( 7)); break; - case CPUINFO_STR_REGISTER + SH4_FR8: sprintf(info->s, "FR8 :%08X %f", FP_RS( 8),(double)FP_RFS( 8)); break; - case CPUINFO_STR_REGISTER + SH4_FR9: sprintf(info->s, "FR9 :%08X %f", FP_RS( 9),(double)FP_RFS( 9)); break; - case CPUINFO_STR_REGISTER + SH4_FR10: sprintf(info->s, "FR10 :%08X %f", FP_RS(10),(double)FP_RFS(10)); break; - case CPUINFO_STR_REGISTER + SH4_FR11: sprintf(info->s, "FR11 :%08X %f", FP_RS(11),(double)FP_RFS(11)); break; - case CPUINFO_STR_REGISTER + SH4_FR12: sprintf(info->s, "FR12 :%08X %f", FP_RS(12),(double)FP_RFS(12)); break; - case CPUINFO_STR_REGISTER + SH4_FR13: sprintf(info->s, "FR13 :%08X %f", FP_RS(13),(double)FP_RFS(13)); break; - case CPUINFO_STR_REGISTER + SH4_FR14: sprintf(info->s, "FR14 :%08X %f", FP_RS(14),(double)FP_RFS(14)); break; - case CPUINFO_STR_REGISTER + SH4_FR15: sprintf(info->s, "FR15 :%08X %f", FP_RS(15),(double)FP_RFS(15)); break; - case CPUINFO_STR_REGISTER + SH4_XF0: sprintf(info->s, "XF0 :%08X %f", FP_XS( 0),(double)FP_XFS( 0)); break; - case CPUINFO_STR_REGISTER + SH4_XF1: sprintf(info->s, "XF1 :%08X %f", FP_XS( 1),(double)FP_XFS( 1)); break; - case CPUINFO_STR_REGISTER + SH4_XF2: sprintf(info->s, "XF2 :%08X %f", FP_XS( 2),(double)FP_XFS( 2)); break; - case CPUINFO_STR_REGISTER + SH4_XF3: sprintf(info->s, "XF3 :%08X %f", FP_XS( 3),(double)FP_XFS( 3)); break; - case CPUINFO_STR_REGISTER + SH4_XF4: sprintf(info->s, "XF4 :%08X %f", FP_XS( 4),(double)FP_XFS( 4)); break; - case CPUINFO_STR_REGISTER + SH4_XF5: sprintf(info->s, "XF5 :%08X %f", FP_XS( 5),(double)FP_XFS( 5)); break; - case CPUINFO_STR_REGISTER + SH4_XF6: sprintf(info->s, "XF6 :%08X %f", FP_XS( 6),(double)FP_XFS( 6)); break; - case CPUINFO_STR_REGISTER + SH4_XF7: sprintf(info->s, "XF7 :%08X %f", FP_XS( 7),(double)FP_XFS( 7)); break; - case CPUINFO_STR_REGISTER + SH4_XF8: sprintf(info->s, "XF8 :%08X %f", FP_XS( 8),(double)FP_XFS( 8)); break; - case CPUINFO_STR_REGISTER + SH4_XF9: sprintf(info->s, "XF9 :%08X %f", FP_XS( 9),(double)FP_XFS( 9)); break; - case CPUINFO_STR_REGISTER + SH4_XF10: sprintf(info->s, "XF10 :%08X %f", FP_XS(10),(double)FP_XFS(10)); break; - case CPUINFO_STR_REGISTER + SH4_XF11: sprintf(info->s, "XF11 :%08X %f", FP_XS(11),(double)FP_XFS(11)); break; - case CPUINFO_STR_REGISTER + SH4_XF12: sprintf(info->s, "XF12 :%08X %f", FP_XS(12),(double)FP_XFS(12)); break; - case CPUINFO_STR_REGISTER + SH4_XF13: sprintf(info->s, "XF13 :%08X %f", FP_XS(13),(double)FP_XFS(13)); break; - case CPUINFO_STR_REGISTER + SH4_XF14: sprintf(info->s, "XF14 :%08X %f", FP_XS(14),(double)FP_XFS(14)); break; - case CPUINFO_STR_REGISTER + SH4_XF15: sprintf(info->s, "XF15 :%08X %f", FP_XS(15),(double)FP_XFS(15)); break; //%01.2e + UINT8 fpu_xor = 0; #endif - } -} -CPU_GET_INFO( sh3 ) -{ - switch (state) + switch (entry.index()) { - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sh3); break; + case STATE_GENFLAGS: + string.printf("%s%s%s%s%c%c%d%c%c", + m_sr & MD ? "MD ":" ", + m_sr & sRB ? "RB ":" ", + m_sr & BL ? "BL ":" ", + m_sr & FD ? "FD ":" ", + m_sr & M ? 'M':'.', + m_sr & Q ? 'Q':'.', + (m_sr & I) >> 4, + m_sr & S ? 'S':'.', + m_sr & T ? 'T':'.'); + break; - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "SH-3 (little)"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Hitachi SH7700"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "sh3"); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map64 = ADDRESS_MAP_NAME(sh3_internal_map); break; + case SH4_FR0: + string.printf("%08X %f", m_fr[0 ^ fpu_xor], (double)FP_RFS(0 ^ fpu_xor)); + break; + + case SH4_FR1: + string.printf("%08X %f", m_fr[1 ^ fpu_xor], (double)FP_RFS(1 ^ fpu_xor)); + break; + + case SH4_FR2: + string.printf("%08X %f", m_fr[2 ^ fpu_xor], (double)FP_RFS(2 ^ fpu_xor)); + break; + + case SH4_FR3: + string.printf("%08X %f", m_fr[3 ^ fpu_xor], (double)FP_RFS(3 ^ fpu_xor)); + break; + + case SH4_FR4: + string.printf("%08X %f", m_fr[4 ^ fpu_xor], (double)FP_RFS(4 ^ fpu_xor)); + break; + + case SH4_FR5: + string.printf("%08X %f", m_fr[5 ^ fpu_xor], (double)FP_RFS(5 ^ fpu_xor)); + break; + + case SH4_FR6: + string.printf("%08X %f", m_fr[6 ^ fpu_xor], (double)FP_RFS(6 ^ fpu_xor)); + break; + + case SH4_FR7: + string.printf("%08X %f", m_fr[7 ^ fpu_xor], (double)FP_RFS(7 ^ fpu_xor)); + break; + + case SH4_FR8: + string.printf("%08X %f", m_fr[8 ^ fpu_xor], (double)FP_RFS(8 ^ fpu_xor)); + break; + + case SH4_FR9: + string.printf("%08X %f", m_fr[9 ^ fpu_xor], (double)FP_RFS(9 ^ fpu_xor)); + break; + + case SH4_FR10: + string.printf("%08X %f", m_fr[10 ^ fpu_xor], (double)FP_RFS(10 ^ fpu_xor)); + break; + + case SH4_FR11: + string.printf("%08X %f", m_fr[11 ^ fpu_xor], (double)FP_RFS(11 ^ fpu_xor)); + break; + + case SH4_FR12: + string.printf("%08X %f", m_fr[12 ^ fpu_xor], (double)FP_RFS(12 ^ fpu_xor)); + break; + + case SH4_FR13: + string.printf("%08X %f", m_fr[13 ^ fpu_xor], (double)FP_RFS(13 ^ fpu_xor)); + break; + + case SH4_FR14: + string.printf("%08X %f", m_fr[14 ^ fpu_xor], (double)FP_RFS(14 ^ fpu_xor)); + break; + + case SH4_FR15: + string.printf("%08X %f", m_fr[15 ^ fpu_xor], (double)FP_RFS(15 ^ fpu_xor)); + break; + + case SH4_XF0: + string.printf("%08X %f", m_xf[0 ^ fpu_xor], (double)FP_XFS(0 ^ fpu_xor)); + break; + + case SH4_XF1: + string.printf("%08X %f", m_xf[1 ^ fpu_xor], (double)FP_XFS(1 ^ fpu_xor)); + break; + + case SH4_XF2: + string.printf("%08X %f", m_xf[2 ^ fpu_xor], (double)FP_XFS(2 ^ fpu_xor)); + break; + + case SH4_XF3: + string.printf("%08X %f", m_xf[3 ^ fpu_xor], (double)FP_XFS(3 ^ fpu_xor)); + break; + + case SH4_XF4: + string.printf("%08X %f", m_xf[4 ^ fpu_xor], (double)FP_XFS(4 ^ fpu_xor)); + break; + + case SH4_XF5: + string.printf("%08X %f", m_xf[5 ^ fpu_xor], (double)FP_XFS(5 ^ fpu_xor)); + break; + + case SH4_XF6: + string.printf("%08X %f", m_xf[6 ^ fpu_xor], (double)FP_XFS(6 ^ fpu_xor)); + break; + + case SH4_XF7: + string.printf("%08X %f", m_xf[7 ^ fpu_xor], (double)FP_XFS(7 ^ fpu_xor)); + break; + + case SH4_XF8: + string.printf("%08X %f", m_xf[8 ^ fpu_xor], (double)FP_XFS(8 ^ fpu_xor)); + break; + + case SH4_XF9: + string.printf("%08X %f", m_xf[9 ^ fpu_xor], (double)FP_XFS(9 ^ fpu_xor)); + break; + + case SH4_XF10: + string.printf("%08X %f", m_xf[10 ^ fpu_xor], (double)FP_XFS(10 ^ fpu_xor)); + break; + + case SH4_XF11: + string.printf("%08X %f", m_xf[11 ^ fpu_xor], (double)FP_XFS(11 ^ fpu_xor)); + break; + + case SH4_XF12: + string.printf("%08X %f", m_xf[12 ^ fpu_xor], (double)FP_XFS(12 ^ fpu_xor)); + break; + + case SH4_XF13: + string.printf("%08X %f", m_xf[13 ^ fpu_xor], (double)FP_XFS(13 ^ fpu_xor)); + break; + + case SH4_XF14: + string.printf("%08X %f", m_xf[14 ^ fpu_xor], (double)FP_XFS(14 ^ fpu_xor)); + break; + + case SH4_XF15: + string.printf("%08X %f", m_xf[15 ^ fpu_xor], (double)FP_XFS(15 ^ fpu_xor)); + break; - default: CPU_GET_INFO_CALL(sh4); break; } } -CPU_GET_INFO( sh3be ) + +void sh34_base_device::sh4_set_ftcsr_callback(sh4_ftcsr_callback callback) { - switch (state) - { - /* --- the following bits of info are returned as pointers to data or functions --- */ - case CPUINFO_FCT_RESET: info->reset = CPU_RESET_NAME(sh3); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(sh4be); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sh4be); break; - - /* --- the following bits of info are returned as NULL-terminated strings --- */ - case CPUINFO_STR_NAME: strcpy(info->s, "SH-3 (big)"); break; - case CPUINFO_STR_FAMILY: strcpy(info->s, "Hitachi SH7700"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "sh3be"); break; - case CPUINFO_PTR_INTERNAL_MEMORY_MAP + AS_PROGRAM: info->internal_map64 = ADDRESS_MAP_NAME(sh3_internal_map); break; - - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - - default: CPU_GET_INFO_CALL(sh4); break; - } + m_ftcsr_read_callback = callback; } -CPU_GET_INFO( sh4be ) -{ - switch (state) - { - case CPUINFO_STR_NAME: strcpy(info->s, "SH-4 (big)"); break; - case CPUINFO_STR_SHORTNAME: strcpy(info->s, "sh4be"); break; - case CPUINFO_FCT_EXECUTE: info->execute = CPU_EXECUTE_NAME(sh4be); break; - case CPUINFO_FCT_DISASSEMBLE: info->disassemble = CPU_DISASSEMBLE_NAME(sh4be); break; - case CPUINFO_INT_ENDIANNESS: info->i = ENDIANNESS_BIG; break; - default: CPU_GET_INFO_CALL(sh4); break; - } -} - -sh3_device::sh3_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock) - : legacy_cpu_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(sh3)) -{ -} - -sh3_device::sh3_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info) - : legacy_cpu_device(mconfig, type, tag, owner, clock, info) -{ -} - -const device_type SH3LE = &legacy_device_creator; - -sh3be_device::sh3be_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock) - : sh3_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(sh3be)) -{ -} - -const device_type SH3BE = &legacy_device_creator; - -sh4_device::sh4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock) - : legacy_cpu_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(sh4)) -{ -} - -sh4_device::sh4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info) - : legacy_cpu_device(mconfig, type, tag, owner, clock, info) -{ -} - -const device_type SH4LE = &legacy_device_creator; - -sh4be_device::sh4be_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock) - : sh4_device(mconfig, type, tag, owner, clock, CPU_GET_INFO_NAME(sh4be)) -{ -} - -const device_type SH4BE = &legacy_device_creator; - -#endif // USE_SH4DRC diff --git a/src/emu/cpu/sh4/sh4.h b/src/emu/cpu/sh4/sh4.h index 9cd96b7af82..7afd5d26a72 100644 --- a/src/emu/cpu/sh4/sh4.h +++ b/src/emu/cpu/sh4/sh4.h @@ -111,20 +111,6 @@ enum SH4_IOPORT_SCIF=8*4 }; -struct sh4_config -{ - int md2; - int md1; - int md0; - int md6; - int md4; - int md3; - int md5; - int md7; - int md8; - int clock; -}; - struct sh4_device_dma { UINT32 length; @@ -147,69 +133,644 @@ struct sh4_ddt_dma typedef void (*sh4_ftcsr_callback)(UINT32); -CPU_GET_INFO( sh3 ); -class sh3_device : public legacy_cpu_device +#define MCFG_SH4_MD0(_md0) \ + sh34_base_device::set_md0(*device, _md0); + +#define MCFG_SH4_MD1(_md1) \ + sh34_base_device::set_md1(*device, _md1); + +#define MCFG_SH4_MD2(_md2) \ + sh34_base_device::set_md2(*device, _md2); + +#define MCFG_SH4_MD3(_md3) \ + sh34_base_device::set_md3(*device, _md3); + +#define MCFG_SH4_MD4(_md4) \ + sh34_base_device::set_md4(*device, _md4); + +#define MCFG_SH4_MD5(_md5) \ + sh34_base_device::set_md5(*device, _md5); + +#define MCFG_SH4_MD6(_md6) \ + sh34_base_device::set_md6(*device, _md6); + +#define MCFG_SH4_MD7(_md7) \ + sh34_base_device::set_md7(*device, _md7); + +#define MCFG_SH4_MD8(_md8) \ + sh34_base_device::set_md8(*device, _md8); + +#define MCFG_SH4_CLOCK(_clock) \ + sh34_base_device::set_sh4_clock(*device, _clock); + + +class sh34_base_device : public cpu_device { public: - sh3_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock); - sh3_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info); + // construction/destruction + sh34_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness, address_map_constructor internal); + + static void set_md0(device_t &device, int md0) { downcast(device).c_md0 = md0; } + static void set_md1(device_t &device, int md0) { downcast(device).c_md1 = md0; } + static void set_md2(device_t &device, int md0) { downcast(device).c_md2 = md0; } + static void set_md3(device_t &device, int md0) { downcast(device).c_md3 = md0; } + static void set_md4(device_t &device, int md0) { downcast(device).c_md4 = md0; } + static void set_md5(device_t &device, int md0) { downcast(device).c_md5 = md0; } + static void set_md6(device_t &device, int md0) { downcast(device).c_md6 = md0; } + static void set_md7(device_t &device, int md0) { downcast(device).c_md7 = md0; } + static void set_md8(device_t &device, int md0) { downcast(device).c_md8 = md0; } + static void set_sh4_clock(device_t &device, int clock) { downcast(device).c_clock = clock; } + + TIMER_CALLBACK_MEMBER( sh4_refresh_timer_callback ); + TIMER_CALLBACK_MEMBER( sh4_rtc_timer_callback ); + TIMER_CALLBACK_MEMBER( sh4_timer_callback ); + TIMER_CALLBACK_MEMBER( sh4_dmac_callback ); + + void sh4_set_frt_input(int state); + void sh4_set_irln_input(int value); + void sh4_set_ftcsr_callback(sh4_ftcsr_callback callback); + int sh4_dma_data(struct sh4_device_dma *s); + void sh4_dma_ddt(struct sh4_ddt_dma *s); + +protected: + // device-level overrides + virtual void device_start(); + virtual void device_reset(); + + // device_execute_interface overrides + virtual UINT32 execute_min_cycles() const { return 1; } + virtual UINT32 execute_max_cycles() const { return 4; } + virtual UINT32 execute_input_lines() const { return 5; } + virtual void execute_run(); + virtual void execute_set_input(int inputnum, int state); + + // device_memory_interface overrides + virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const { return (spacenum == AS_PROGRAM) ? &m_program_config : ((spacenum == AS_IO) ? &m_io_config : NULL); } + + // device_state_interface overrides + virtual void state_import(const device_state_entry &entry); + virtual void state_export(const device_state_entry &entry); + virtual void state_string_export(const device_state_entry &entry, astring &string); + + // device_disasm_interface overrides + virtual UINT32 disasm_min_opcode_bytes() const { return 2; } + virtual UINT32 disasm_max_opcode_bytes() const { return 2; } + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); + +protected: + address_space_config m_program_config; + address_space_config m_io_config; + + int c_md2; + int c_md1; + int c_md0; + int c_md6; + int c_md4; + int c_md3; + int c_md5; + int c_md7; + int c_md8; + int c_clock; + + UINT32 m_ppc; + UINT32 m_pc; + UINT32 m_spc; + UINT32 m_pr; + UINT32 m_sr; + UINT32 m_ssr; + UINT32 m_gbr; + UINT32 m_vbr; + UINT32 m_mach; + UINT32 m_macl; + UINT32 m_r[16]; + UINT32 m_rbnk[2][8]; + UINT32 m_sgr; + UINT32 m_fr[16]; + UINT32 m_xf[16]; + UINT32 m_ea; + UINT32 m_delay; + UINT32 m_cpu_off; + UINT32 m_pending_irq; + UINT32 m_test_irq; + UINT32 m_fpscr; + UINT32 m_fpul; + UINT32 m_dbr; + + UINT32 m_exception_priority[128]; + int m_exception_requesting[128]; + + INT8 m_irq_line_state[17]; + address_space *m_internal; + address_space *m_program; + direct_read_data *m_direct; + address_space *m_io; + + // sh4 internal + UINT32 m_m[16384]; + + // timer regs handled manually for reuse + UINT32 m_SH4_TSTR; + UINT32 m_SH4_TCNT0; + UINT32 m_SH4_TCNT1; + UINT32 m_SH4_TCNT2; + UINT32 m_SH4_TCR0; + UINT32 m_SH4_TCR1; + UINT32 m_SH4_TCR2; + UINT32 m_SH4_TCOR0; + UINT32 m_SH4_TCOR1; + UINT32 m_SH4_TCOR2; + UINT32 m_SH4_TOCR; + UINT32 m_SH4_TCPR2; + + // INTC regs + UINT32 m_SH4_IPRA; + + UINT32 m_SH4_IPRC; + + // DMAC regs + UINT32 m_SH4_SAR0; + UINT32 m_SH4_SAR1; + UINT32 m_SH4_SAR2; + UINT32 m_SH4_SAR3; + + UINT32 m_SH4_DAR0; + UINT32 m_SH4_DAR1; + UINT32 m_SH4_DAR2; + UINT32 m_SH4_DAR3; + + UINT32 m_SH4_CHCR0; + UINT32 m_SH4_CHCR1; + UINT32 m_SH4_CHCR2; + UINT32 m_SH4_CHCR3; + + UINT32 m_SH4_DMATCR0; + UINT32 m_SH4_DMATCR1; + UINT32 m_SH4_DMATCR2; + UINT32 m_SH4_DMATCR3; + + UINT32 m_SH4_DMAOR; + + INT8 m_nmi_line_state; + + UINT8 m_sleep_mode; + + int m_frt_input; + int m_irln; + int m_internal_irq_level; + int m_internal_irq_vector; + + emu_timer *m_dma_timer[4]; + emu_timer *m_refresh_timer; + emu_timer *m_rtc_timer; + emu_timer *m_timer[3]; + UINT32 m_refresh_timer_base; + int m_dma_timer_active[4]; + UINT32 m_dma_source[4]; + UINT32 m_dma_destination[4]; + UINT32 m_dma_count[4]; + int m_dma_wordsize[4]; + int m_dma_source_increment[4]; + int m_dma_destination_increment[4]; + int m_dma_mode[4]; + + int m_sh4_icount; + int m_is_slave; + int m_cpu_clock; + int m_bus_clock; + int m_pm_clock; + int m_fpu_sz; + int m_fpu_pr; + int m_ioport16_pullup; + int m_ioport16_direction; + int m_ioport4_pullup; + int m_ioport4_direction; + + void (*m_ftcsr_read_callback)(UINT32 data); + + /* This MMU simulation is good for the simple remap used on Naomi GD-ROM SQ access *ONLY* */ + UINT32 m_sh4_tlb_address[64]; + UINT32 m_sh4_tlb_data[64]; + UINT8 m_sh4_mmu_enabled; + + int m_cpu_type; + + // sh3 internal + UINT32 m_sh3internal_upper[0x3000/4]; + UINT32 m_sh3internal_lower[0x1000]; + + UINT64 m_debugger_temp; + + + typedef void (sh34_base_device::*sh4ophandler)(const UINT16); + + static sh4ophandler s_master_ophandler_table[0x10000]; + static const sh4ophandler s_op1111_0x13_handlers[16]; + static const sh4ophandler s_op1000_handler[16]; + static const sh4ophandler s_op1100_handler[16]; + static const sh4ophandler s_op0000_handlers[256]; + static const sh4ophandler s_op0100_handlers[256]; + static const sh4ophandler s_upper4bits[256]; + + + inline void sh4_check_pending_irq(const char *message) // look for highest priority active exception and handle it + { + int a,irq,z; + + irq = 0; + z = -1; + for (a=0;a <= SH4_INTC_ROVI;a++) + { + if (m_exception_requesting[a]) + { + if ((int)m_exception_priority[a] > z) + { + z = m_exception_priority[a]; + irq = a; + } + } + } + if (z >= 0) + { + sh4_exception(message, irq); + } + } + + void TODO(const UINT16 opcode); + void WB(offs_t A, UINT8 V); + void WW(offs_t A, UINT16 V); + void WL(offs_t A, UINT32 V); + void ADD(const UINT16 opcode); + void ADDI(const UINT16 opcode); + void ADDC(const UINT16 opcode); + void ADDV(const UINT16 opcode); + void AND(const UINT16 opcode); + void ANDI(const UINT16 opcode); + void ANDM(const UINT16 opcode); + void BF(const UINT16 opcode); + void BFS(const UINT16 opcode); + void BRA(const UINT16 opcode); + void BRAF(const UINT16 opcode); + void BSR(const UINT16 opcode); + void BSRF(const UINT16 opcode); + void BT(const UINT16 opcode); + void BTS(const UINT16 opcode); + void CLRMAC(const UINT16 opcode); + void CLRT(const UINT16 opcode); + void CMPEQ(const UINT16 opcode); + void CMPGE(const UINT16 opcode); + void CMPGT(const UINT16 opcode); + void CMPHI(const UINT16 opcode); + void CMPHS(const UINT16 opcode); + void CMPPL(const UINT16 opcode); + void CMPPZ(const UINT16 opcode); + void CMPSTR(const UINT16 opcode); + void CMPIM(const UINT16 opcode); + void DIV0S(const UINT16 opcode); + void DIV0U(const UINT16 opcode); + void DIV1(const UINT16 opcode); + void DMULS(const UINT16 opcode); + void DMULU(const UINT16 opcode); + void DT(const UINT16 opcode); + void EXTSB(const UINT16 opcode); + void EXTSW(const UINT16 opcode); + void EXTUB(const UINT16 opcode); + void EXTUW(const UINT16 opcode); + void JMP(const UINT16 opcode); + void JSR(const UINT16 opcode); + void LDCSR(const UINT16 opcode); + void LDCGBR(const UINT16 opcode); + void LDCVBR(const UINT16 opcode); + void LDCMSR(const UINT16 opcode); + void LDCMGBR(const UINT16 opcode); + void LDCMVBR(const UINT16 opcode); + void LDSMACH(const UINT16 opcode); + void LDSMACL(const UINT16 opcode); + void LDSPR(const UINT16 opcode); + void LDSMMACH(const UINT16 opcode); + void LDSMMACL(const UINT16 opcode); + void LDSMPR(const UINT16 opcode); + void MAC_L(const UINT16 opcode); + void MAC_W(const UINT16 opcode); + void MOV(const UINT16 opcode); + void MOVBS(const UINT16 opcode); + void MOVWS(const UINT16 opcode); + void MOVLS(const UINT16 opcode); + void MOVBL(const UINT16 opcode); + void MOVWL(const UINT16 opcode); + void MOVLL(const UINT16 opcode); + void MOVBM(const UINT16 opcode); + void MOVWM(const UINT16 opcode); + void MOVLM(const UINT16 opcode); + void MOVBP(const UINT16 opcode); + void MOVWP(const UINT16 opcode); + void MOVLP(const UINT16 opcode); + void MOVBS0(const UINT16 opcode); + void MOVWS0(const UINT16 opcode); + void MOVLS0(const UINT16 opcode); + void MOVBL0(const UINT16 opcode); + void MOVWL0(const UINT16 opcode); + void MOVLL0(const UINT16 opcode); + void MOVI(const UINT16 opcode); + void MOVWI(const UINT16 opcode); + void MOVLI(const UINT16 opcode); + void MOVBLG(const UINT16 opcode); + void MOVWLG(const UINT16 opcode); + void MOVLLG(const UINT16 opcode); + void MOVBSG(const UINT16 opcode); + void MOVWSG(const UINT16 opcode); + void MOVLSG(const UINT16 opcode); + void MOVBS4(const UINT16 opcode); + void MOVWS4(const UINT16 opcode); + void MOVLS4(const UINT16 opcode); + void MOVBL4(const UINT16 opcode); + void MOVWL4(const UINT16 opcode); + void MOVLL4(const UINT16 opcode); + void MOVA(const UINT16 opcode); + void MOVT(const UINT16 opcode); + void MULL(const UINT16 opcode); + void MULS(const UINT16 opcode); + void MULU(const UINT16 opcode); + void NEG(const UINT16 opcode); + void NEGC(const UINT16 opcode); + void NOP(const UINT16 opcode); + void NOT(const UINT16 opcode); + void OR(const UINT16 opcode); + void ORI(const UINT16 opcode); + void ORM(const UINT16 opcode); + void ROTCL(const UINT16 opcode); + void ROTCR(const UINT16 opcode); + void ROTL(const UINT16 opcode); + void ROTR(const UINT16 opcode); + void RTE(const UINT16 opcode); + void RTS(const UINT16 opcode); + void SETT(const UINT16 opcode); + void SHAL(const UINT16 opcode); + void SHAR(const UINT16 opcode); + void SHLL(const UINT16 opcode); + void SHLL2(const UINT16 opcode); + void SHLL8(const UINT16 opcode); + void SHLL16(const UINT16 opcode); + void SHLR(const UINT16 opcode); + void SHLR2(const UINT16 opcode); + void SHLR8(const UINT16 opcode); + void SHLR16(const UINT16 opcode); + void SLEEP(const UINT16 opcode); + void STCSR(const UINT16 opcode); + void STCGBR(const UINT16 opcode); + void STCVBR(const UINT16 opcode); + void STCMSR(const UINT16 opcode); + void STCMGBR(const UINT16 opcode); + void STCMVBR(const UINT16 opcode); + void STSMACH(const UINT16 opcode); + void STSMACL(const UINT16 opcode); + void STSPR(const UINT16 opcode); + void STSMMACH(const UINT16 opcode); + void STSMMACL(const UINT16 opcode); + void STSMPR(const UINT16 opcode); + void SUB(const UINT16 opcode); + void SUBC(const UINT16 opcode); + void SUBV(const UINT16 opcode); + void SWAPB(const UINT16 opcode); + void SWAPW(const UINT16 opcode); + void TAS(const UINT16 opcode); + void TRAPA(const UINT16 opcode); + void TST(const UINT16 opcode); + void TSTI(const UINT16 opcode); + void TSTM(const UINT16 opcode); + void XOR(const UINT16 opcode); + void XORI(const UINT16 opcode); + void XORM(const UINT16 opcode); + void XTRCT(const UINT16 opcode); + void STCSSR(const UINT16 opcode); + void STCSPC(const UINT16 opcode); + void STCSGR(const UINT16 opcode); + void STSFPUL(const UINT16 opcode); + void STSFPSCR(const UINT16 opcode); + void STCDBR(const UINT16 opcode); + void STCRBANK(const UINT16 opcode); + void STCMRBANK(const UINT16 opcode); + void MOVCAL(const UINT16 opcode); + void CLRS(const UINT16 opcode); + void SETS(const UINT16 opcode); + void STCMSGR(const UINT16 opcode); + void STSMFPUL(const UINT16 opcode); + void STSMFPSCR(const UINT16 opcode); + void STCMDBR(const UINT16 opcode); + void STCMSSR(const UINT16 opcode); + void STCMSPC(const UINT16 opcode); + void LDSMFPUL(const UINT16 opcode); + void LDSMFPSCR(const UINT16 opcode); + void LDCMDBR(const UINT16 opcode); + void LDCMRBANK(const UINT16 opcode); + void LDCMSSR(const UINT16 opcode); + void LDCMSPC(const UINT16 opcode); + void LDSFPUL(const UINT16 opcode); + void LDSFPSCR(const UINT16 opcode); + void LDCDBR(const UINT16 opcode); + void SHAD(const UINT16 opcode); + void SHLD(const UINT16 opcode); + void LDCRBANK(const UINT16 opcode); + void LDCSSR(const UINT16 opcode); + void LDCSPC(const UINT16 opcode); + void PREFM(const UINT16 opcode); + void FMOVMRIFR(const UINT16 opcode); + void FMOVFRMR(const UINT16 opcode); + void FMOVFRMDR(const UINT16 opcode); + void FMOVFRS0(const UINT16 opcode); + void FMOVS0FR(const UINT16 opcode); + void FMOVMRFR(const UINT16 opcode); + void FMOVFR(const UINT16 opcode); + void FLDI1(const UINT16 opcode); + void FLDI0(const UINT16 opcode); + void FLDS(const UINT16 opcode); + void FSTS(const UINT16 opcode); + void FRCHG(); + void FSCHG(); + void FTRC(const UINT16 opcode); + void FLOAT(const UINT16 opcode); + void FNEG(const UINT16 opcode); + void FABS(const UINT16 opcode); + void FCMP_EQ(const UINT16 opcode); + void FCMP_GT(const UINT16 opcode); + void FCNVDS(const UINT16 opcode); + void FCNVSD(const UINT16 opcode); + void FADD(const UINT16 opcode); + void FSUB(const UINT16 opcode); + void FMUL(const UINT16 opcode); + void FDIV(const UINT16 opcode); + void FMAC(const UINT16 opcode); + void FSQRT(const UINT16 opcode); + void FSRRA(const UINT16 opcode); + void FSSCA(const UINT16 opcode); + void FIPR(const UINT16 opcode); + void FTRV(const UINT16 opcode); + void op1111_0xf13(const UINT16 opcode); + void dbreak(const UINT16 opcode); + void op1111_0x13(UINT16 opcode); + UINT8 RB(offs_t A); + UINT16 RW(offs_t A); + UINT32 RL(offs_t A); + void sh4_change_register_bank(int to); + void sh4_swap_fp_registers(); + void sh4_swap_fp_couples(); + void sh4_syncronize_register_bank(int to); + void sh4_default_exception_priorities(); + void sh4_exception_recompute(); + void sh4_exception_request(int exception); + void sh4_exception_unrequest(int exception); + void sh4_exception_checkunrequest(int exception); + void sh4_exception(const char *message, int exception); + UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor); + void sh4_refresh_timer_recompute(); + void increment_rtc_time(int mode); + void sh4_dmac_nmi(); + void sh4_handler_ipra_w(UINT32 data, UINT32 mem_mask); + UINT32 sh4_getsqremap(UINT32 address); + void sh4_build_optable(); + void sh4_parse_configuration(); + void sh4_timer_recompute(int which); + UINT32 sh4_handle_tcnt0_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcnt1_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcnt2_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcor0_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcor1_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcor2_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcr0_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcr1_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcr2_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tstr_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tocr_addr_r(UINT32 mem_mask); + UINT32 sh4_handle_tcpr2_addr_r(UINT32 mem_mask); + void sh4_handle_tstr_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcr0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcr1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcr2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcor0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcor1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcor2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcnt0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcnt1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcnt2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tocr_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_tcpr2_addr_w(UINT32 data, UINT32 mem_mask); + int sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr); + int sh4_dma_transfer_device(int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr); + void sh4_dmac_check(int channel); + void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask); + void sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask); + UINT32 sh4_handle_sar0_addr_r(UINT32 mem_mask) { return m_SH4_SAR0; } + UINT32 sh4_handle_sar1_addr_r(UINT32 mem_mask) { return m_SH4_SAR1; } + UINT32 sh4_handle_sar2_addr_r(UINT32 mem_mask) { return m_SH4_SAR2; } + UINT32 sh4_handle_sar3_addr_r(UINT32 mem_mask) { return m_SH4_SAR3; } + UINT32 sh4_handle_dar0_addr_r(UINT32 mem_mask) { return m_SH4_DAR0; } + UINT32 sh4_handle_dar1_addr_r(UINT32 mem_mask) { return m_SH4_DAR1; } + UINT32 sh4_handle_dar2_addr_r(UINT32 mem_mask) { return m_SH4_DAR2; } + UINT32 sh4_handle_dar3_addr_r(UINT32 mem_mask) { return m_SH4_DAR3; } + UINT32 sh4_handle_dmatcr0_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR0; } + UINT32 sh4_handle_dmatcr1_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR1; } + UINT32 sh4_handle_dmatcr2_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR2; } + UINT32 sh4_handle_dmatcr3_addr_r(UINT32 mem_mask) { return m_SH4_DMATCR3; } + UINT32 sh4_handle_chcr0_addr_r(UINT32 mem_mask) { return m_SH4_CHCR0; } + UINT32 sh4_handle_chcr1_addr_r(UINT32 mem_mask) { return m_SH4_CHCR1; } + UINT32 sh4_handle_chcr2_addr_r(UINT32 mem_mask) { return m_SH4_CHCR2; } + UINT32 sh4_handle_chcr3_addr_r(UINT32 mem_mask) { return m_SH4_CHCR3; } + UINT32 sh4_handle_dmaor_addr_r(UINT32 mem_mask) { return m_SH4_DMAOR; } + +}; + + +class sh3_base_device : public sh34_base_device +{ +public: + // construction/destruction + sh3_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness); DECLARE_WRITE32_MEMBER( sh3_internal_w ); DECLARE_READ32_MEMBER( sh3_internal_r ); DECLARE_WRITE32_MEMBER( sh3_internal_high_w ); DECLARE_READ32_MEMBER( sh3_internal_high_r ); - + +protected: + virtual void device_reset(); }; -extern const device_type SH3LE; -CPU_GET_INFO( sh3be ); - -class sh3be_device : public sh3_device +class sh4_base_device : public sh34_base_device { public: - sh3be_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock); -}; + // construction/destruction + sh4_base_device(const machine_config &mconfig, device_type type, const char *name, const char *tag, device_t *owner, UINT32 clock, const char *shortname, endianness_t endianness); -extern const device_type SH3BE; - -CPU_GET_INFO( sh4 ); - -class sh4_device : public legacy_cpu_device -{ -public: - sh4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock); - sh4_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock, cpu_get_info_func info); - DECLARE_WRITE32_MEMBER( sh4_internal_w ); - DECLARE_READ32_MEMBER( sh4_internal_r ); - + DECLARE_READ32_MEMBER( sh4_internal_r ); + DECLARE_READ64_MEMBER( sh4_tlb_r ); DECLARE_WRITE64_MEMBER( sh4_tlb_w ); + +protected: + virtual void device_reset(); }; -extern const device_type SH4LE; -CPU_GET_INFO( sh4be ); - -class sh4be_device : public sh4_device +class sh3_device : public sh3_base_device { public: - sh4be_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, UINT32 clock); + sh3_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); }; + +class sh3be_device : public sh3_base_device +{ +public: + sh3be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + virtual void execute_run(); + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); +}; + + +class sh4_device : public sh4_base_device +{ +public: + sh4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); +}; + + +class sh4be_device : public sh4_base_device +{ +public: + sh4be_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock); + +protected: + virtual void execute_run(); + virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options); +}; + + +extern const device_type SH3LE; +extern const device_type SH3BE; +extern const device_type SH4LE; extern const device_type SH4BE; - -void sh4_set_frt_input(device_t *device, int state); -void sh4_set_irln_input(device_t *device, int value); -void sh4_set_ftcsr_callback(device_t *device, sh4_ftcsr_callback callback); -int sh4_dma_data(device_t *device, struct sh4_device_dma *s); -void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s); - /*************************************************************************** COMPILER-SPECIFIC OPTIONS ***************************************************************************/ diff --git a/src/emu/cpu/sh4/sh4comn.c b/src/emu/cpu/sh4/sh4comn.c index 673003da20f..4fd6b9808ef 100644 --- a/src/emu/cpu/sh4/sh4comn.c +++ b/src/emu/cpu/sh4/sh4comn.c @@ -233,174 +233,172 @@ static const int sh3_intevt2_exception_codes[] = -void sh4_change_register_bank(sh4_state *sh4, int to) +void sh34_base_device::sh4_change_register_bank(int to) { -int s; + int s; if (to) // 0 -> 1 { for (s = 0;s < 8;s++) { - sh4->rbnk[0][s] = sh4->r[s]; - sh4->r[s] = sh4->rbnk[1][s]; + m_rbnk[0][s] = m_r[s]; + m_r[s] = m_rbnk[1][s]; } } else // 1 -> 0 { for (s = 0;s < 8;s++) { - sh4->rbnk[1][s] = sh4->r[s]; - sh4->r[s] = sh4->rbnk[0][s]; + m_rbnk[1][s] = m_r[s]; + m_r[s] = m_rbnk[0][s]; } } } -void sh4_swap_fp_registers(sh4_state *sh4) +void sh34_base_device::sh4_swap_fp_registers() { -int s; -UINT32 z; + int s; + UINT32 z; for (s = 0;s <= 15;s++) { - z = sh4->fr[s]; - sh4->fr[s] = sh4->xf[s]; - sh4->xf[s] = z; + z = m_fr[s]; + m_fr[s] = m_xf[s]; + m_xf[s] = z; } } -#ifdef LSB_FIRST -void sh4_swap_fp_couples(sh4_state *sh4) +void sh34_base_device::sh4_swap_fp_couples() { -int s; -UINT32 z; + int s; + UINT32 z; for (s = 0;s <= 15;s = s+2) { - z = sh4->fr[s]; - sh4->fr[s] = sh4->fr[s + 1]; - sh4->fr[s + 1] = z; - z = sh4->xf[s]; - sh4->xf[s] = sh4->xf[s + 1]; - sh4->xf[s + 1] = z; + z = m_fr[s]; + m_fr[s] = m_fr[s + 1]; + m_fr[s + 1] = z; + z = m_xf[s]; + m_xf[s] = m_xf[s + 1]; + m_xf[s + 1] = z; } } -#endif -void sh4_syncronize_register_bank(sh4_state *sh4, int to) +void sh34_base_device::sh4_syncronize_register_bank(int to) { -int s; + int s; for (s = 0;s < 8;s++) { - sh4->rbnk[to][s] = sh4->r[s]; + m_rbnk[to][s] = m_r[s]; } } -void sh4_default_exception_priorities(sh4_state *sh4) // setup default priorities for exceptions +void sh34_base_device::sh4_default_exception_priorities() // setup default priorities for exceptions { -int a; + int a; for (a=0;a <= SH4_INTC_NMI;a++) - sh4->exception_priority[a] = exception_priority_default[a]; + m_exception_priority[a] = exception_priority_default[a]; for (a=SH4_INTC_IRLn0;a <= SH4_INTC_IRLnE;a++) - sh4->exception_priority[a] = INTPRI(15-(a-SH4_INTC_IRLn0), a); - sh4->exception_priority[SH4_INTC_IRL0] = INTPRI(13, SH4_INTC_IRL0); - sh4->exception_priority[SH4_INTC_IRL1] = INTPRI(10, SH4_INTC_IRL1); - sh4->exception_priority[SH4_INTC_IRL2] = INTPRI(7, SH4_INTC_IRL2); - sh4->exception_priority[SH4_INTC_IRL3] = INTPRI(4, SH4_INTC_IRL3); + m_exception_priority[a] = INTPRI(15-(a-SH4_INTC_IRLn0), a); + m_exception_priority[SH4_INTC_IRL0] = INTPRI(13, SH4_INTC_IRL0); + m_exception_priority[SH4_INTC_IRL1] = INTPRI(10, SH4_INTC_IRL1); + m_exception_priority[SH4_INTC_IRL2] = INTPRI(7, SH4_INTC_IRL2); + m_exception_priority[SH4_INTC_IRL3] = INTPRI(4, SH4_INTC_IRL3); for (a=SH4_INTC_HUDI;a <= SH4_INTC_ROVI;a++) - sh4->exception_priority[a] = INTPRI(0, a); + m_exception_priority[a] = INTPRI(0, a); } -void sh4_exception_recompute(sh4_state *sh4) // checks if there is any interrupt with high enough priority +void sh34_base_device::sh4_exception_recompute() // checks if there is any interrupt with high enough priority { int a,z; - sh4->test_irq = 0; - if ((!sh4->pending_irq) || ((sh4->sr & BL) && (sh4->exception_requesting[SH4_INTC_NMI] == 0))) + m_test_irq = 0; + if ((!m_pending_irq) || ((m_sr & BL) && (m_exception_requesting[SH4_INTC_NMI] == 0))) return; - z = (sh4->sr >> 4) & 15; + z = (m_sr >> 4) & 15; for (a=0;a <= SH4_INTC_ROVI;a++) { - if (sh4->exception_requesting[a]) + if (m_exception_requesting[a]) { - int pri = (((int)sh4->exception_priority[a] >> 8) & 255); + int pri = (((int)m_exception_priority[a] >> 8) & 255); //logerror("pri is %02x z is %02x\n",pri,z); if (pri > z) { //logerror("will test\n"); - sh4->test_irq = 1; // will check for exception at end of instructions + m_test_irq = 1; // will check for exception at end of instructions break; } } } } -void sh4_exception_request(sh4_state *sh4, int exception) // start requesting an exception +void sh34_base_device::sh4_exception_request(int exception) // start requesting an exception { //logerror("sh4_exception_request a\n"); - if (!sh4->exception_requesting[exception]) + if (!m_exception_requesting[exception]) { //logerror("sh4_exception_request b\n"); - sh4->exception_requesting[exception] = 1; - sh4->pending_irq++; - sh4_exception_recompute(sh4); + m_exception_requesting[exception] = 1; + m_pending_irq++; + sh4_exception_recompute(); } } -void sh4_exception_unrequest(sh4_state *sh4, int exception) // stop requesting an exception +void sh34_base_device::sh4_exception_unrequest(int exception) // stop requesting an exception { - if (sh4->exception_requesting[exception]) + if (m_exception_requesting[exception]) { - sh4->exception_requesting[exception] = 0; - sh4->pending_irq--; - sh4_exception_recompute(sh4); + m_exception_requesting[exception] = 0; + m_pending_irq--; + sh4_exception_recompute(); } } -void sh4_exception_checkunrequest(sh4_state *sh4, int exception) +void sh34_base_device::sh4_exception_checkunrequest(int exception) { if (exception == SH4_INTC_NMI) - sh4_exception_unrequest(sh4, exception); + sh4_exception_unrequest(exception); if ((exception == SH4_INTC_DMTE0) || (exception == SH4_INTC_DMTE1) || (exception == SH4_INTC_DMTE2) || (exception == SH4_INTC_DMTE3)) - sh4_exception_unrequest(sh4, exception); + sh4_exception_unrequest(exception); } -void sh4_exception(sh4_state *sh4, const char *message, int exception) // handle exception +void sh34_base_device::sh4_exception(const char *message, int exception) // handle exception { UINT32 vector; - if (sh4->cpu_type == CPU_TYPE_SH4) + if (m_cpu_type == CPU_TYPE_SH4) { if (exception < SH4_INTC_NMI) return; // Not yet supported if (exception == SH4_INTC_NMI) { - if ((sh4->sr & BL) && (!(sh4->m[ICR] & 0x200))) + if ((m_sr & BL) && (!(m_m[ICR] & 0x200))) return; - sh4->m[ICR] &= ~0x200; - sh4->m[INTEVT] = 0x1c0; + m_m[ICR] &= ~0x200; + m_m[INTEVT] = 0x1c0; vector = 0x600; - sh4->irq_callback(*sh4->device, INPUT_LINE_NMI); - LOG(("SH-4 '%s' nmi exception after [%s]\n", sh4->device->tag(), message)); + standard_irq_callback(INPUT_LINE_NMI); + LOG(("SH-4 '%s' nmi exception after [%s]\n", tag(), message)); } else { - // if ((sh4->m[ICR] & 0x4000) && (sh4->nmi_line_state == ASSERT_LINE)) + // if ((m_m[ICR] & 0x4000) && (m_nmi_line_state == ASSERT_LINE)) // return; - if (sh4->sr & BL) + if (m_sr & BL) return; - if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15)) + if (((m_exception_priority[exception] >> 8) & 255) <= ((m_sr >> 4) & 15)) return; - sh4->m[INTEVT] = exception_codes[exception]; + m_m[INTEVT] = exception_codes[exception]; vector = 0x600; if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3)) - sh4->irq_callback(*sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0); + standard_irq_callback(SH4_INTC_IRL0-exception+SH4_IRL0); else - sh4->irq_callback(*sh4->device, SH4_IRL3+1); - LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag(), exception, message)); + standard_irq_callback(SH4_IRL3+1); + LOG(("SH-4 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message)); } } else /* SH3 exceptions */ @@ -415,116 +413,114 @@ void sh4_exception(sh4_state *sh4, const char *message, int exception) // handle } else { - if (sh4->sr & BL) + if (m_sr & BL) return; - if (((sh4->exception_priority[exception] >> 8) & 255) <= ((sh4->sr >> 4) & 15)) + if (((m_exception_priority[exception] >> 8) & 255) <= ((m_sr >> 4) & 15)) return; vector = 0x600; if ((exception >= SH4_INTC_IRL0) && (exception <= SH4_INTC_IRL3)) - sh4->irq_callback(*sh4->device, SH4_INTC_IRL0-exception+SH4_IRL0); + standard_irq_callback(SH4_INTC_IRL0-exception+SH4_IRL0); else - sh4->irq_callback(*sh4->device, SH4_IRL3+1); + standard_irq_callback(SH4_IRL3+1); if (sh3_intevt2_exception_codes[exception]==-1) fatalerror("sh3_intevt2_exception_codes unpopulated for exception %02x\n", exception); - sh4->m_sh3internal_lower[INTEVT2] = sh3_intevt2_exception_codes[exception]; - sh4->m_sh3internal_upper[SH3_EXPEVT_ADDR] = exception_codes[exception]; + m_sh3internal_lower[INTEVT2] = sh3_intevt2_exception_codes[exception]; + m_sh3internal_upper[SH3_EXPEVT_ADDR] = exception_codes[exception]; - LOG(("SH-3 '%s' interrupt exception #%d after [%s]\n", sh4->device->tag(), exception, message)); + LOG(("SH-3 '%s' interrupt exception #%d after [%s]\n", tag(), exception, message)); } /***** END ASSUME THIS TO BE WRONG FOR NOW *****/ } - sh4_exception_checkunrequest(sh4, exception); + sh4_exception_checkunrequest(exception); - sh4->spc = sh4->pc; - sh4->ssr = sh4->sr; - sh4->sgr = sh4->r[15]; + m_spc = m_pc; + m_ssr = m_sr; + m_sgr = m_r[15]; - sh4->sr |= MD; - if ((sh4->device->machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) - sh4_syncronize_register_bank(sh4, (sh4->sr & sRB) >> 29); - if (!(sh4->sr & sRB)) - sh4_change_register_bank(sh4, 1); - sh4->sr |= sRB; - sh4->sr |= BL; - sh4_exception_recompute(sh4); + m_sr |= MD; + if ((machine().debug_flags & DEBUG_FLAG_ENABLED) != 0) + sh4_syncronize_register_bank((m_sr & sRB) >> 29); + if (!(m_sr & sRB)) + sh4_change_register_bank(1); + m_sr |= sRB; + m_sr |= BL; + sh4_exception_recompute(); /* fetch PC */ - sh4->pc = sh4->vbr + vector; + m_pc = m_vbr + vector; /* wake up if a sleep opcode is triggered */ - if(sh4->sleep_mode == 1) { sh4->sleep_mode = 2; } + if(m_sleep_mode == 1) { m_sleep_mode = 2; } } -static UINT32 compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor) +UINT32 sh34_base_device::compute_ticks_refresh_timer(emu_timer *timer, int hertz, int base, int divisor) { // elapsed:total = x : ticks - // x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] - // ticks/total=ticks / ((rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] / 100000000)=100000000/rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] + // x=elapsed*tics/total -> x=elapsed*(double)100000000/rtcnt_div[(m_m[RTCSR] >> 3) & 7] + // ticks/total=ticks / ((rtcnt_div[(m_m[RTCSR] >> 3) & 7] * ticks) / 100000000)=1/((rtcnt_div[(m_m[RTCSR] >> 3) & 7] / 100000000)=100000000/rtcnt_div[(m_m[RTCSR] >> 3) & 7] return base + (UINT32)((timer->elapsed().as_double() * (double)hertz) / (double)divisor); } -static void sh4_refresh_timer_recompute(sh4_state *sh4) +void sh34_base_device::sh4_refresh_timer_recompute() { -UINT32 ticks; + UINT32 ticks; - if (sh4->cpu_type != CPU_TYPE_SH4) - fatalerror("sh4_refresh_timer_recompute uses sh4->m[] with SH3\n"); + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_refresh_timer_recompute uses m_m[] with SH3\n"); //if rtcnt < rtcor then rtcor-rtcnt //if rtcnt >= rtcor then 256-rtcnt+rtcor=256+rtcor-rtcnt - ticks = sh4->m[RTCOR]-sh4->m[RTCNT]; + ticks = m_m[RTCOR]-m_m[RTCNT]; if (ticks <= 0) ticks = 256 + ticks; - sh4->refresh_timer->adjust(attotime::from_hz(sh4->bus_clock) * rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] * ticks); - sh4->refresh_timer_base = sh4->m[RTCNT]; + m_refresh_timer->adjust(attotime::from_hz(m_bus_clock) * rtcnt_div[(m_m[RTCSR] >> 3) & 7] * ticks); + m_refresh_timer_base = m_m[RTCNT]; } -static TIMER_CALLBACK( sh4_refresh_timer_callback ) +TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_refresh_timer_callback ) { - sh4_state *sh4 = (sh4_state *)ptr; + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_refresh_timer_callback uses m_m[] with SH3\n"); - if (sh4->cpu_type != CPU_TYPE_SH4) - fatalerror("sh4_refresh_timer_callback uses sh4->m[] with SH3\n"); - - sh4->m[RTCNT] = 0; - sh4_refresh_timer_recompute(sh4); - sh4->m[RTCSR] |= 128; - if ((sh4->m[MCR] & 4) && !(sh4->m[MCR] & 2)) + m_m[RTCNT] = 0; + sh4_refresh_timer_recompute(); + m_m[RTCSR] |= 128; + if ((m_m[MCR] & 4) && !(m_m[MCR] & 2)) { - sh4->m[RFCR] = (sh4->m[RFCR] + 1) & 1023; - if (((sh4->m[RTCSR] & 1) && (sh4->m[RFCR] == 512)) || (sh4->m[RFCR] == 0)) + m_m[RFCR] = (m_m[RFCR] + 1) & 1023; + if (((m_m[RTCSR] & 1) && (m_m[RFCR] == 512)) || (m_m[RFCR] == 0)) { - sh4->m[RFCR] = 0; - sh4->m[RTCSR] |= 4; + m_m[RFCR] = 0; + m_m[RTCSR] |= 4; } } } -static void increment_rtc_time(sh4_state *sh4, int mode) +void sh34_base_device::increment_rtc_time(int mode) { int carry, year, leap, days; - if (sh4->cpu_type != CPU_TYPE_SH4) - fatalerror("increment_rtc_time uses sh4->m[] with SH3\n"); + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("increment_rtc_time uses m_m[] with SH3\n"); if (mode == 0) { carry = 0; - sh4->m[RSECCNT] = sh4->m[RSECCNT] + 1; - if ((sh4->m[RSECCNT] & 0xf) == 0xa) - sh4->m[RSECCNT] = sh4->m[RSECCNT] + 6; - if (sh4->m[RSECCNT] == 0x60) + m_m[RSECCNT] = m_m[RSECCNT] + 1; + if ((m_m[RSECCNT] & 0xf) == 0xa) + m_m[RSECCNT] = m_m[RSECCNT] + 6; + if (m_m[RSECCNT] == 0x60) { - sh4->m[RSECCNT] = 0; + m_m[RSECCNT] = 0; carry=1; } else @@ -533,34 +529,34 @@ static void increment_rtc_time(sh4_state *sh4, int mode) else carry = 1; - sh4->m[RMINCNT] = sh4->m[RMINCNT] + carry; - if ((sh4->m[RMINCNT] & 0xf) == 0xa) - sh4->m[RMINCNT] = sh4->m[RMINCNT] + 6; + m_m[RMINCNT] = m_m[RMINCNT] + carry; + if ((m_m[RMINCNT] & 0xf) == 0xa) + m_m[RMINCNT] = m_m[RMINCNT] + 6; carry=0; - if (sh4->m[RMINCNT] == 0x60) + if (m_m[RMINCNT] == 0x60) { - sh4->m[RMINCNT] = 0; + m_m[RMINCNT] = 0; carry = 1; } - sh4->m[RHRCNT] = sh4->m[RHRCNT] + carry; - if ((sh4->m[RHRCNT] & 0xf) == 0xa) - sh4->m[RHRCNT] = sh4->m[RHRCNT] + 6; + m_m[RHRCNT] = m_m[RHRCNT] + carry; + if ((m_m[RHRCNT] & 0xf) == 0xa) + m_m[RHRCNT] = m_m[RHRCNT] + 6; carry = 0; - if (sh4->m[RHRCNT] == 0x24) + if (m_m[RHRCNT] == 0x24) { - sh4->m[RHRCNT] = 0; + m_m[RHRCNT] = 0; carry = 1; } - sh4->m[RWKCNT] = sh4->m[RWKCNT] + carry; - if (sh4->m[RWKCNT] == 0x7) + m_m[RWKCNT] = m_m[RWKCNT] + carry; + if (m_m[RWKCNT] == 0x7) { - sh4->m[RWKCNT] = 0; + m_m[RWKCNT] = 0; } days = 0; - year = (sh4->m[RYRCNT] & 0xf) + ((sh4->m[RYRCNT] & 0xf0) >> 4)*10 + ((sh4->m[RYRCNT] & 0xf00) >> 8)*100 + ((sh4->m[RYRCNT] & 0xf000) >> 12)*1000; + year = (m_m[RYRCNT] & 0xf) + ((m_m[RYRCNT] & 0xf0) >> 4)*10 + ((m_m[RYRCNT] & 0xf00) >> 8)*100 + ((m_m[RYRCNT] & 0xf000) >> 12)*1000; leap = 0; if (!(year%100)) { @@ -569,115 +565,112 @@ static void increment_rtc_time(sh4_state *sh4, int mode) } else if (!(year%4)) leap = 1; - if (sh4->m[RMONCNT] != 2) + if (m_m[RMONCNT] != 2) leap = 0; - if (sh4->m[RMONCNT]) - days = daysmonth[(sh4->m[RMONCNT] & 0xf) + ((sh4->m[RMONCNT] & 0xf0) >> 4)*10 - 1]; + if (m_m[RMONCNT]) + days = daysmonth[(m_m[RMONCNT] & 0xf) + ((m_m[RMONCNT] & 0xf0) >> 4)*10 - 1]; - sh4->m[RDAYCNT] = sh4->m[RDAYCNT] + carry; - if ((sh4->m[RDAYCNT] & 0xf) == 0xa) - sh4->m[RDAYCNT] = sh4->m[RDAYCNT] + 6; + m_m[RDAYCNT] = m_m[RDAYCNT] + carry; + if ((m_m[RDAYCNT] & 0xf) == 0xa) + m_m[RDAYCNT] = m_m[RDAYCNT] + 6; carry = 0; - if (sh4->m[RDAYCNT] > (days+leap)) + if (m_m[RDAYCNT] > (days+leap)) { - sh4->m[RDAYCNT] = 1; + m_m[RDAYCNT] = 1; carry = 1; } - sh4->m[RMONCNT] = sh4->m[RMONCNT] + carry; - if ((sh4->m[RMONCNT] & 0xf) == 0xa) - sh4->m[RMONCNT] = sh4->m[RMONCNT] + 6; + m_m[RMONCNT] = m_m[RMONCNT] + carry; + if ((m_m[RMONCNT] & 0xf) == 0xa) + m_m[RMONCNT] = m_m[RMONCNT] + 6; carry=0; - if (sh4->m[RMONCNT] == 0x13) + if (m_m[RMONCNT] == 0x13) { - sh4->m[RMONCNT] = 1; + m_m[RMONCNT] = 1; carry = 1; } - sh4->m[RYRCNT] = sh4->m[RYRCNT] + carry; - if ((sh4->m[RYRCNT] & 0xf) >= 0xa) - sh4->m[RYRCNT] = sh4->m[RYRCNT] + 6; - if ((sh4->m[RYRCNT] & 0xf0) >= 0xa0) - sh4->m[RYRCNT] = sh4->m[RYRCNT] + 0x60; - if ((sh4->m[RYRCNT] & 0xf00) >= 0xa00) - sh4->m[RYRCNT] = sh4->m[RYRCNT] + 0x600; - if ((sh4->m[RYRCNT] & 0xf000) >= 0xa000) - sh4->m[RYRCNT] = 0; + m_m[RYRCNT] = m_m[RYRCNT] + carry; + if ((m_m[RYRCNT] & 0xf) >= 0xa) + m_m[RYRCNT] = m_m[RYRCNT] + 6; + if ((m_m[RYRCNT] & 0xf0) >= 0xa0) + m_m[RYRCNT] = m_m[RYRCNT] + 0x60; + if ((m_m[RYRCNT] & 0xf00) >= 0xa00) + m_m[RYRCNT] = m_m[RYRCNT] + 0x600; + if ((m_m[RYRCNT] & 0xf000) >= 0xa000) + m_m[RYRCNT] = 0; } -static TIMER_CALLBACK( sh4_rtc_timer_callback ) +TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_rtc_timer_callback ) { - sh4_state *sh4 = (sh4_state *)ptr; - - if (sh4->cpu_type != CPU_TYPE_SH4) + if (m_cpu_type != CPU_TYPE_SH4) { - logerror("sh4_rtc_timer_callback uses sh4->m[] with SH3\n"); + logerror("sh4_rtc_timer_callback uses m_m[] with SH3\n"); return; } - sh4->rtc_timer->adjust(attotime::from_hz(128)); - sh4->m[R64CNT] = (sh4->m[R64CNT]+1) & 0x7f; - if (sh4->m[R64CNT] == 64) + m_rtc_timer->adjust(attotime::from_hz(128)); + m_m[R64CNT] = (m_m[R64CNT]+1) & 0x7f; + if (m_m[R64CNT] == 64) { - sh4->m[RCR1] |= 0x80; - increment_rtc_time(sh4, 0); - //sh4_exception_request(sh4, SH4_INTC_NMI); // TEST + m_m[RCR1] |= 0x80; + increment_rtc_time(0); + //sh4_exception_request(SH4_INTC_NMI); // TEST } } -static void sh4_dmac_nmi(sh4_state *sh4) // manage dma when nmi gets asserted +void sh34_base_device::sh4_dmac_nmi() // manage dma when nmi gets asserted { int s; - sh4->SH4_DMAOR |= DMAOR_NMIF; + m_SH4_DMAOR |= DMAOR_NMIF; for (s = 0;s < 4;s++) { - if (sh4->dma_timer_active[s]) + if (m_dma_timer_active[s]) { logerror("SH4: DMA %d cancelled due to NMI but all data transferred", s); - sh4->dma_timer[s]->adjust(attotime::never, s); - sh4->dma_timer_active[s] = 0; + m_dma_timer[s]->adjust(attotime::never, s); + m_dma_timer_active[s] = 0; } } } -void sh4_handler_ipra_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handler_ipra_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_IPRA); + COMBINE_DATA(&m_SH4_IPRA); /* 15 - 12 TMU0 */ /* 11 - 8 TMU1 */ /* 7 - 4 TMU2 */ /* 3 - 0 RTC */ - sh4->exception_priority[SH4_INTC_ATI] = INTPRI(sh4->SH4_IPRA & 0x000f, SH4_INTC_ATI); - sh4->exception_priority[SH4_INTC_PRI] = INTPRI(sh4->SH4_IPRA & 0x000f, SH4_INTC_PRI); - sh4->exception_priority[SH4_INTC_CUI] = INTPRI(sh4->SH4_IPRA & 0x000f, SH4_INTC_CUI); + m_exception_priority[SH4_INTC_ATI] = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_ATI); + m_exception_priority[SH4_INTC_PRI] = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_PRI); + m_exception_priority[SH4_INTC_CUI] = INTPRI(m_SH4_IPRA & 0x000f, SH4_INTC_CUI); - sh4->exception_priority[SH4_INTC_TUNI2] = INTPRI((sh4->SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TUNI2); - sh4->exception_priority[SH4_INTC_TICPI2] = INTPRI((sh4->SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TICPI2); + m_exception_priority[SH4_INTC_TUNI2] = INTPRI((m_SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TUNI2); + m_exception_priority[SH4_INTC_TICPI2] = INTPRI((m_SH4_IPRA & 0x00f0) >> 4, SH4_INTC_TICPI2); - sh4->exception_priority[SH4_INTC_TUNI1] = INTPRI((sh4->SH4_IPRA & 0x0f00) >> 8, SH4_INTC_TUNI1); + m_exception_priority[SH4_INTC_TUNI1] = INTPRI((m_SH4_IPRA & 0x0f00) >> 8, SH4_INTC_TUNI1); - sh4->exception_priority[SH4_INTC_TUNI0] = INTPRI((sh4->SH4_IPRA & 0xf000) >> 12, SH4_INTC_TUNI0); + m_exception_priority[SH4_INTC_TUNI0] = INTPRI((m_SH4_IPRA & 0xf000) >> 12, SH4_INTC_TUNI0); - logerror("setting priorities TMU0 %01x TMU1 %01x TMU2 %01x RTC %01x\n", (sh4->SH4_IPRA & 0xf000)>>12, (sh4->SH4_IPRA & 0x0f00)>>8, (sh4->SH4_IPRA & 0x00f0)>>4, (sh4->SH4_IPRA & 0x000f)>>0); + logerror("setting priorities TMU0 %01x TMU1 %01x TMU2 %01x RTC %01x\n", (m_SH4_IPRA & 0xf000)>>12, (m_SH4_IPRA & 0x0f00)>>8, (m_SH4_IPRA & 0x00f0)>>4, (m_SH4_IPRA & 0x000f)>>0); - sh4_exception_recompute(sh4); + sh4_exception_recompute(); } -WRITE32_MEMBER( sh4_device::sh4_internal_w ) +WRITE32_MEMBER( sh4_base_device::sh4_internal_w ) { - sh4_state *sh4 = get_safe_token(this); int a; UINT32 addr = (offset << 2) + 0xfe000000; offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11); - if (sh4->cpu_type != CPU_TYPE_SH4) - fatalerror("sh4_internal_w uses sh4->m[] with SH3\n"); + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_internal_w uses m_m[] with SH3\n"); - UINT32 old = sh4->m[offset]; - COMBINE_DATA(sh4->m+offset); + UINT32 old = m_m[offset]; + COMBINE_DATA(m_m+offset); // printf("sh4_internal_w: Write %08x (%x), %08x @ %08x\n", 0xfe000000+((offset & 0x3fc0) << 11)+((offset & 0x3f) << 2), offset, data, mem_mask); @@ -689,157 +682,157 @@ WRITE32_MEMBER( sh4_device::sh4_internal_w ) printf("SH4 MMU Enabled\n"); printf("If you're seeing this, but running something other than a Naomi GD-ROM game then chances are it won't work\n"); printf("The MMU emulation is a hack specific to that system\n"); - sh4->sh4_mmu_enabled = 1; + m_sh4_mmu_enabled = 1; // should be a different bit! { int i; for (i=0;i<64;i++) { - sh4->sh4_tlb_address[i] = 0; - sh4->sh4_tlb_data[i] = 0; + m_sh4_tlb_address[i] = 0; + m_sh4_tlb_data[i] = 0; } } } else { - sh4->sh4_mmu_enabled = 0; + m_sh4_mmu_enabled = 0; } break; // Memory refresh case RTCSR: - sh4->m[RTCSR] &= 255; + m_m[RTCSR] &= 255; if ((old >> 3) & 7) - sh4->m[RTCNT] = compute_ticks_refresh_timer(sh4->refresh_timer, sh4->bus_clock, sh4->refresh_timer_base, rtcnt_div[(old >> 3) & 7]) & 0xff; - if ((sh4->m[RTCSR] >> 3) & 7) + m_m[RTCNT] = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(old >> 3) & 7]) & 0xff; + if ((m_m[RTCSR] >> 3) & 7) { // activated - sh4_refresh_timer_recompute(sh4); + sh4_refresh_timer_recompute(); } else { - sh4->refresh_timer->adjust(attotime::never); + m_refresh_timer->adjust(attotime::never); } break; case RTCNT: - sh4->m[RTCNT] &= 255; - if ((sh4->m[RTCSR] >> 3) & 7) + m_m[RTCNT] &= 255; + if ((m_m[RTCSR] >> 3) & 7) { // active - sh4_refresh_timer_recompute(sh4); + sh4_refresh_timer_recompute(); } break; case RTCOR: - sh4->m[RTCOR] &= 255; - if ((sh4->m[RTCSR] >> 3) & 7) + m_m[RTCOR] &= 255; + if ((m_m[RTCSR] >> 3) & 7) { // active - sh4->m[RTCNT] = compute_ticks_refresh_timer(sh4->refresh_timer, sh4->bus_clock, sh4->refresh_timer_base, rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff; - sh4_refresh_timer_recompute(sh4); + m_m[RTCNT] = compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff; + sh4_refresh_timer_recompute(); } break; case RFCR: - sh4->m[RFCR] &= 1023; + m_m[RFCR] &= 1023; break; // RTC case RCR1: - if ((sh4->m[RCR1] & 8) && (~old & 8)) // 0 -> 1 - sh4->m[RCR1] ^= 1; + if ((m_m[RCR1] & 8) && (~old & 8)) // 0 -> 1 + m_m[RCR1] ^= 1; break; case RCR2: - if (sh4->m[RCR2] & 2) + if (m_m[RCR2] & 2) { - sh4->m[R64CNT] = 0; - sh4->m[RCR2] ^= 2; + m_m[R64CNT] = 0; + m_m[RCR2] ^= 2; } - if (sh4->m[RCR2] & 4) + if (m_m[RCR2] & 4) { - sh4->m[R64CNT] = 0; - if (sh4->m[RSECCNT] >= 30) - increment_rtc_time(sh4, 1); - sh4->m[RSECCNT] = 0; + m_m[R64CNT] = 0; + if (m_m[RSECCNT] >= 30) + increment_rtc_time(1); + m_m[RSECCNT] = 0; } - if ((sh4->m[RCR2] & 8) && (~old & 8)) + if ((m_m[RCR2] & 8) && (~old & 8)) { // 0 -> 1 - sh4->rtc_timer->adjust(attotime::from_hz(128)); + m_rtc_timer->adjust(attotime::from_hz(128)); } - else if (~(sh4->m[RCR2]) & 8) + else if (~(m_m[RCR2]) & 8) { // 0 - sh4->rtc_timer->adjust(attotime::never); + m_rtc_timer->adjust(attotime::never); } break; /********************************************************************************************************************* TMU (Timer Unit) *********************************************************************************************************************/ - case SH4_TSTR_ADDR: sh4_handle_tstr_addr_w(sh4,data,mem_mask); break; - case SH4_TCR0_ADDR: sh4_handle_tcr0_addr_w(sh4,data,mem_mask); break; - case SH4_TCR1_ADDR: sh4_handle_tcr1_addr_w(sh4,data,mem_mask); break; - case SH4_TCR2_ADDR: sh4_handle_tcr2_addr_w(sh4,data,mem_mask); break; - case SH4_TCOR0_ADDR: sh4_handle_tcor0_addr_w(sh4,data,mem_mask); break; - case SH4_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(sh4,data,mem_mask); break; - case SH4_TCOR1_ADDR: sh4_handle_tcor1_addr_w(sh4,data,mem_mask); break; - case SH4_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(sh4,data,mem_mask); break; - case SH4_TCOR2_ADDR: sh4_handle_tcor2_addr_w(sh4,data,mem_mask); break; - case SH4_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(sh4,data,mem_mask); break; - case SH4_TOCR_ADDR: sh4_handle_tocr_addr_w(sh4,data,mem_mask); break; // not supported - case SH4_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(sh4,data,mem_mask); break; // not supported + case SH4_TSTR_ADDR: sh4_handle_tstr_addr_w(data,mem_mask); break; + case SH4_TCR0_ADDR: sh4_handle_tcr0_addr_w(data,mem_mask); break; + case SH4_TCR1_ADDR: sh4_handle_tcr1_addr_w(data,mem_mask); break; + case SH4_TCR2_ADDR: sh4_handle_tcr2_addr_w(data,mem_mask); break; + case SH4_TCOR0_ADDR: sh4_handle_tcor0_addr_w(data,mem_mask); break; + case SH4_TCNT0_ADDR: sh4_handle_tcnt0_addr_w(data,mem_mask); break; + case SH4_TCOR1_ADDR: sh4_handle_tcor1_addr_w(data,mem_mask); break; + case SH4_TCNT1_ADDR: sh4_handle_tcnt1_addr_w(data,mem_mask); break; + case SH4_TCOR2_ADDR: sh4_handle_tcor2_addr_w(data,mem_mask); break; + case SH4_TCNT2_ADDR: sh4_handle_tcnt2_addr_w(data,mem_mask); break; + case SH4_TOCR_ADDR: sh4_handle_tocr_addr_w(data,mem_mask); break; // not supported + case SH4_TCPR2_ADDR: sh4_handle_tcpr2_addr_w(data,mem_mask); break; // not supported /********************************************************************************************************************* INTC (Interrupt Controller) *********************************************************************************************************************/ case ICR: - sh4->m[ICR] = (sh4->m[ICR] & 0x7fff) | (old & 0x8000); + m_m[ICR] = (m_m[ICR] & 0x7fff) | (old & 0x8000); break; - case IPRA: sh4_handler_ipra_w(sh4, data, mem_mask); break; + case IPRA: sh4_handler_ipra_w(data, mem_mask); break; case IPRB: - sh4->exception_priority[SH4_INTC_SCI1ERI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1ERI); - sh4->exception_priority[SH4_INTC_SCI1RXI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1RXI); - sh4->exception_priority[SH4_INTC_SCI1TXI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TXI); - sh4->exception_priority[SH4_INTC_SCI1TEI] = INTPRI((sh4->m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TEI); - sh4->exception_priority[SH4_INTC_RCMI] = INTPRI((sh4->m[IPRB] & 0x0f00) >> 8, SH4_INTC_RCMI); - sh4->exception_priority[SH4_INTC_ROVI] = INTPRI((sh4->m[IPRB] & 0x0f00) >> 8, SH4_INTC_ROVI); - sh4->exception_priority[SH4_INTC_ITI] = INTPRI((sh4->m[IPRB] & 0xf000) >> 12, SH4_INTC_ITI); - sh4_exception_recompute(sh4); + m_exception_priority[SH4_INTC_SCI1ERI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1ERI); + m_exception_priority[SH4_INTC_SCI1RXI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1RXI); + m_exception_priority[SH4_INTC_SCI1TXI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TXI); + m_exception_priority[SH4_INTC_SCI1TEI] = INTPRI((m_m[IPRB] & 0x00f0) >> 4, SH4_INTC_SCI1TEI); + m_exception_priority[SH4_INTC_RCMI] = INTPRI((m_m[IPRB] & 0x0f00) >> 8, SH4_INTC_RCMI); + m_exception_priority[SH4_INTC_ROVI] = INTPRI((m_m[IPRB] & 0x0f00) >> 8, SH4_INTC_ROVI); + m_exception_priority[SH4_INTC_ITI] = INTPRI((m_m[IPRB] & 0xf000) >> 12, SH4_INTC_ITI); + sh4_exception_recompute(); break; case IPRC: - sh4->exception_priority[SH4_INTC_HUDI] = INTPRI(sh4->m[IPRC] & 0x000f, SH4_INTC_HUDI); - sh4->exception_priority[SH4_INTC_SCIFERI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFERI); - sh4->exception_priority[SH4_INTC_SCIFRXI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFRXI); - sh4->exception_priority[SH4_INTC_SCIFBRI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFBRI); - sh4->exception_priority[SH4_INTC_SCIFTXI] = INTPRI((sh4->m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFTXI); - sh4->exception_priority[SH4_INTC_DMTE0] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE0); - sh4->exception_priority[SH4_INTC_DMTE1] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE1); - sh4->exception_priority[SH4_INTC_DMTE2] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE2); - sh4->exception_priority[SH4_INTC_DMTE3] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE3); - sh4->exception_priority[SH4_INTC_DMAE] = INTPRI((sh4->m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMAE); - sh4->exception_priority[SH4_INTC_GPOI] = INTPRI((sh4->m[IPRC] & 0xf000) >> 12, SH4_INTC_GPOI); - sh4_exception_recompute(sh4); + m_exception_priority[SH4_INTC_HUDI] = INTPRI(m_m[IPRC] & 0x000f, SH4_INTC_HUDI); + m_exception_priority[SH4_INTC_SCIFERI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFERI); + m_exception_priority[SH4_INTC_SCIFRXI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFRXI); + m_exception_priority[SH4_INTC_SCIFBRI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFBRI); + m_exception_priority[SH4_INTC_SCIFTXI] = INTPRI((m_m[IPRC] & 0x00f0) >> 4, SH4_INTC_SCIFTXI); + m_exception_priority[SH4_INTC_DMTE0] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE0); + m_exception_priority[SH4_INTC_DMTE1] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE1); + m_exception_priority[SH4_INTC_DMTE2] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE2); + m_exception_priority[SH4_INTC_DMTE3] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMTE3); + m_exception_priority[SH4_INTC_DMAE] = INTPRI((m_m[IPRC] & 0x0f00) >> 8, SH4_INTC_DMAE); + m_exception_priority[SH4_INTC_GPOI] = INTPRI((m_m[IPRC] & 0xf000) >> 12, SH4_INTC_GPOI); + sh4_exception_recompute(); break; /********************************************************************************************************************* DMAC (DMA Controller) *********************************************************************************************************************/ - case SH4_SAR0_ADDR: sh4_handle_sar0_addr_w(sh4,data,mem_mask); break; - case SH4_SAR1_ADDR: sh4_handle_sar1_addr_w(sh4,data,mem_mask); break; - case SH4_SAR2_ADDR: sh4_handle_sar2_addr_w(sh4,data,mem_mask); break; - case SH4_SAR3_ADDR: sh4_handle_sar3_addr_w(sh4,data,mem_mask); break; - case SH4_DAR0_ADDR: sh4_handle_dar0_addr_w(sh4,data,mem_mask); break; - case SH4_DAR1_ADDR: sh4_handle_dar1_addr_w(sh4,data,mem_mask); break; - case SH4_DAR2_ADDR: sh4_handle_dar2_addr_w(sh4,data,mem_mask); break; - case SH4_DAR3_ADDR: sh4_handle_dar3_addr_w(sh4,data,mem_mask); break; - case SH4_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(sh4,data,mem_mask); break; - case SH4_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(sh4,data,mem_mask); break; - case SH4_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(sh4,data,mem_mask); break; - case SH4_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(sh4,data,mem_mask); break; - case SH4_CHCR0_ADDR: sh4_handle_chcr0_addr_w(sh4,data,mem_mask); break; - case SH4_CHCR1_ADDR: sh4_handle_chcr1_addr_w(sh4,data,mem_mask); break; - case SH4_CHCR2_ADDR: sh4_handle_chcr2_addr_w(sh4,data,mem_mask); break; - case SH4_CHCR3_ADDR: sh4_handle_chcr3_addr_w(sh4,data,mem_mask); break; - case SH4_DMAOR_ADDR: sh4_handle_dmaor_addr_w(sh4,data,mem_mask); break; + case SH4_SAR0_ADDR: sh4_handle_sar0_addr_w(data,mem_mask); break; + case SH4_SAR1_ADDR: sh4_handle_sar1_addr_w(data,mem_mask); break; + case SH4_SAR2_ADDR: sh4_handle_sar2_addr_w(data,mem_mask); break; + case SH4_SAR3_ADDR: sh4_handle_sar3_addr_w(data,mem_mask); break; + case SH4_DAR0_ADDR: sh4_handle_dar0_addr_w(data,mem_mask); break; + case SH4_DAR1_ADDR: sh4_handle_dar1_addr_w(data,mem_mask); break; + case SH4_DAR2_ADDR: sh4_handle_dar2_addr_w(data,mem_mask); break; + case SH4_DAR3_ADDR: sh4_handle_dar3_addr_w(data,mem_mask); break; + case SH4_DMATCR0_ADDR: sh4_handle_dmatcr0_addr_w(data,mem_mask); break; + case SH4_DMATCR1_ADDR: sh4_handle_dmatcr1_addr_w(data,mem_mask); break; + case SH4_DMATCR2_ADDR: sh4_handle_dmatcr2_addr_w(data,mem_mask); break; + case SH4_DMATCR3_ADDR: sh4_handle_dmatcr3_addr_w(data,mem_mask); break; + case SH4_CHCR0_ADDR: sh4_handle_chcr0_addr_w(data,mem_mask); break; + case SH4_CHCR1_ADDR: sh4_handle_chcr1_addr_w(data,mem_mask); break; + case SH4_CHCR2_ADDR: sh4_handle_chcr2_addr_w(data,mem_mask); break; + case SH4_CHCR3_ADDR: sh4_handle_chcr3_addr_w(data,mem_mask); break; + case SH4_DMAOR_ADDR: sh4_handle_dmaor_addr_w(data,mem_mask); break; /********************************************************************************************************************* Store Queues *********************************************************************************************************************/ @@ -850,36 +843,36 @@ WRITE32_MEMBER( sh4_device::sh4_internal_w ) I/O *********************************************************************************************************************/ case PCTRA: - sh4->ioport16_pullup = 0; - sh4->ioport16_direction = 0; + m_ioport16_pullup = 0; + m_ioport16_direction = 0; for (a=0;a < 16;a++) { - sh4->ioport16_direction |= (sh4->m[PCTRA] & (1 << (a*2))) >> a; - sh4->ioport16_pullup |= (sh4->m[PCTRA] & (1 << (a*2+1))) >> (a+1); + m_ioport16_direction |= (m_m[PCTRA] & (1 << (a*2))) >> a; + m_ioport16_pullup |= (m_m[PCTRA] & (1 << (a*2+1))) >> (a+1); } - sh4->ioport16_direction &= 0xffff; - sh4->ioport16_pullup = (sh4->ioport16_pullup | sh4->ioport16_direction) ^ 0xffff; - if (sh4->m[BCR2] & 1) - sh4->io->write_dword(SH4_IOPORT_16, (UINT64)(sh4->m[PDTRA] & sh4->ioport16_direction) | ((UINT64)sh4->m[PCTRA] << 16)); + m_ioport16_direction &= 0xffff; + m_ioport16_pullup = (m_ioport16_pullup | m_ioport16_direction) ^ 0xffff; + if (m_m[BCR2] & 1) + m_io->write_dword(SH4_IOPORT_16, (UINT64)(m_m[PDTRA] & m_ioport16_direction) | ((UINT64)m_m[PCTRA] << 16)); break; case PDTRA: - if (sh4->m[BCR2] & 1) - sh4->io->write_dword(SH4_IOPORT_16, (UINT64)(sh4->m[PDTRA] & sh4->ioport16_direction) | ((UINT64)sh4->m[PCTRA] << 16)); + if (m_m[BCR2] & 1) + m_io->write_dword(SH4_IOPORT_16, (UINT64)(m_m[PDTRA] & m_ioport16_direction) | ((UINT64)m_m[PCTRA] << 16)); break; case PCTRB: - sh4->ioport4_pullup = 0; - sh4->ioport4_direction = 0; + m_ioport4_pullup = 0; + m_ioport4_direction = 0; for (a=0;a < 4;a++) { - sh4->ioport4_direction |= (sh4->m[PCTRB] & (1 << (a*2))) >> a; - sh4->ioport4_pullup |= (sh4->m[PCTRB] & (1 << (a*2+1))) >> (a+1); + m_ioport4_direction |= (m_m[PCTRB] & (1 << (a*2))) >> a; + m_ioport4_pullup |= (m_m[PCTRB] & (1 << (a*2+1))) >> (a+1); } - sh4->ioport4_direction &= 0xf; - sh4->ioport4_pullup = (sh4->ioport4_pullup | sh4->ioport4_direction) ^ 0xf; - if (sh4->m[BCR2] & 1) - sh4->io->write_dword(SH4_IOPORT_4, (sh4->m[PDTRB] & sh4->ioport4_direction) | (sh4->m[PCTRB] << 16)); + m_ioport4_direction &= 0xf; + m_ioport4_pullup = (m_ioport4_pullup | m_ioport4_direction) ^ 0xf; + if (m_m[BCR2] & 1) + m_io->write_dword(SH4_IOPORT_4, (m_m[PDTRB] & m_ioport4_direction) | (m_m[PCTRB] << 16)); break; case PDTRB: - if (sh4->m[BCR2] & 1) - sh4->io->write_dword(SH4_IOPORT_4, (sh4->m[PDTRB] & sh4->ioport4_direction) | (sh4->m[PCTRB] << 16)); + if (m_m[BCR2] & 1) + m_io->write_dword(SH4_IOPORT_4, (m_m[PDTRB] & m_ioport4_direction) | (m_m[PCTRB] << 16)); break; case SCBRR2: @@ -894,12 +887,10 @@ WRITE32_MEMBER( sh4_device::sh4_internal_w ) } } -READ32_MEMBER( sh4_device::sh4_internal_r ) +READ32_MEMBER( sh4_base_device::sh4_internal_r ) { - sh4_state *sh4 = get_safe_token(this); - - if (sh4->cpu_type != CPU_TYPE_SH4) - fatalerror("sh4_internal_r uses sh4->m[] with SH3\n"); + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_internal_r uses m_m[] with SH3\n"); UINT32 addr = (offset << 2) + 0xfe000000; offset = ((addr & 0xfc) >> 2) | ((addr & 0x1fe0000) >> 11); @@ -915,100 +906,98 @@ READ32_MEMBER( sh4_device::sh4_internal_r ) case IPRD: return 0x00000000; // SH7750 ignores writes here and always returns zero case RTCNT: - if ((sh4->m[RTCSR] >> 3) & 7) + if ((m_m[RTCSR] >> 3) & 7) { // activated - //((double)rtcnt_div[(sh4->m[RTCSR] >> 3) & 7] / (double)100000000) - //return (refresh_timer_base + (sh4->refresh_timer->elapsed() * (double)100000000) / (double)rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff; - return compute_ticks_refresh_timer(sh4->refresh_timer, sh4->bus_clock, sh4->refresh_timer_base, rtcnt_div[(sh4->m[RTCSR] >> 3) & 7]) & 0xff; + //((double)rtcnt_div[(m_m[RTCSR] >> 3) & 7] / (double)100000000) + //return (refresh_timer_base + (m_refresh_timer->elapsed() * (double)100000000) / (double)rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff; + return compute_ticks_refresh_timer(m_refresh_timer, m_bus_clock, m_refresh_timer_base, rtcnt_div[(m_m[RTCSR] >> 3) & 7]) & 0xff; } else - return sh4->m[RTCNT]; + return m_m[RTCNT]; /********************************************************************************************************************* INTC (Interrupt Controller) *********************************************************************************************************************/ case IPRA: - return sh4->SH4_IPRA; + return m_SH4_IPRA; /********************************************************************************************************************* TMU (Timer Unit) *********************************************************************************************************************/ - case SH4_TSTR_ADDR: return sh4_handle_tstr_addr_r(sh4, mem_mask); - case SH4_TCR0_ADDR: return sh4_handle_tcr0_addr_r(sh4, mem_mask); - case SH4_TCR1_ADDR: return sh4_handle_tcr1_addr_r(sh4, mem_mask); - case SH4_TCR2_ADDR: return sh4_handle_tcr2_addr_r(sh4, mem_mask); - case SH4_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(sh4, mem_mask); - case SH4_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(sh4, mem_mask); - case SH4_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(sh4, mem_mask); - case SH4_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(sh4, mem_mask); - case SH4_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(sh4, mem_mask); - case SH4_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(sh4, mem_mask); - case SH4_TOCR_ADDR: return sh4_handle_tocr_addr_r(sh4, mem_mask); // not supported - case SH4_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(sh4, mem_mask); // not supported + case SH4_TSTR_ADDR: return sh4_handle_tstr_addr_r(mem_mask); + case SH4_TCR0_ADDR: return sh4_handle_tcr0_addr_r(mem_mask); + case SH4_TCR1_ADDR: return sh4_handle_tcr1_addr_r(mem_mask); + case SH4_TCR2_ADDR: return sh4_handle_tcr2_addr_r(mem_mask); + case SH4_TCNT0_ADDR: return sh4_handle_tcnt0_addr_r(mem_mask); + case SH4_TCNT1_ADDR: return sh4_handle_tcnt1_addr_r(mem_mask); + case SH4_TCNT2_ADDR: return sh4_handle_tcnt2_addr_r(mem_mask); + case SH4_TCOR0_ADDR: return sh4_handle_tcor0_addr_r(mem_mask); + case SH4_TCOR1_ADDR: return sh4_handle_tcor1_addr_r(mem_mask); + case SH4_TCOR2_ADDR: return sh4_handle_tcor2_addr_r(mem_mask); + case SH4_TOCR_ADDR: return sh4_handle_tocr_addr_r(mem_mask); // not supported + case SH4_TCPR2_ADDR: return sh4_handle_tcpr2_addr_r(mem_mask); // not supported /********************************************************************************************************************* DMAC (DMA Controller) *********************************************************************************************************************/ - case SH4_SAR0_ADDR: return sh4_handle_sar0_addr_r(sh4,mem_mask); - case SH4_SAR1_ADDR: return sh4_handle_sar1_addr_r(sh4,mem_mask); - case SH4_SAR2_ADDR: return sh4_handle_sar2_addr_r(sh4,mem_mask); - case SH4_SAR3_ADDR: return sh4_handle_sar3_addr_r(sh4,mem_mask); - case SH4_DAR0_ADDR: return sh4_handle_dar0_addr_r(sh4,mem_mask); - case SH4_DAR1_ADDR: return sh4_handle_dar1_addr_r(sh4,mem_mask); - case SH4_DAR2_ADDR: return sh4_handle_dar2_addr_r(sh4,mem_mask); - case SH4_DAR3_ADDR: return sh4_handle_dar3_addr_r(sh4,mem_mask); - case SH4_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(sh4,mem_mask); - case SH4_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(sh4,mem_mask); - case SH4_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(sh4,mem_mask); - case SH4_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(sh4,mem_mask); - case SH4_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(sh4,mem_mask); - case SH4_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(sh4,mem_mask); - case SH4_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(sh4,mem_mask); - case SH4_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(sh4,mem_mask); - case SH4_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(sh4,mem_mask); + case SH4_SAR0_ADDR: return sh4_handle_sar0_addr_r(mem_mask); + case SH4_SAR1_ADDR: return sh4_handle_sar1_addr_r(mem_mask); + case SH4_SAR2_ADDR: return sh4_handle_sar2_addr_r(mem_mask); + case SH4_SAR3_ADDR: return sh4_handle_sar3_addr_r(mem_mask); + case SH4_DAR0_ADDR: return sh4_handle_dar0_addr_r(mem_mask); + case SH4_DAR1_ADDR: return sh4_handle_dar1_addr_r(mem_mask); + case SH4_DAR2_ADDR: return sh4_handle_dar2_addr_r(mem_mask); + case SH4_DAR3_ADDR: return sh4_handle_dar3_addr_r(mem_mask); + case SH4_DMATCR0_ADDR: return sh4_handle_dmatcr0_addr_r(mem_mask); + case SH4_DMATCR1_ADDR: return sh4_handle_dmatcr1_addr_r(mem_mask); + case SH4_DMATCR2_ADDR: return sh4_handle_dmatcr2_addr_r(mem_mask); + case SH4_DMATCR3_ADDR: return sh4_handle_dmatcr3_addr_r(mem_mask); + case SH4_CHCR0_ADDR: return sh4_handle_chcr0_addr_r(mem_mask); + case SH4_CHCR1_ADDR: return sh4_handle_chcr1_addr_r(mem_mask); + case SH4_CHCR2_ADDR: return sh4_handle_chcr2_addr_r(mem_mask); + case SH4_CHCR3_ADDR: return sh4_handle_chcr3_addr_r(mem_mask); + case SH4_DMAOR_ADDR: return sh4_handle_dmaor_addr_r(mem_mask); /********************************************************************************************************************* I/O Ports *********************************************************************************************************************/ case PDTRA: - if (sh4->m[BCR2] & 1) - return (sh4->io->read_dword(SH4_IOPORT_16) & ~sh4->ioport16_direction) | (sh4->m[PDTRA] & sh4->ioport16_direction); + if (m_m[BCR2] & 1) + return (m_io->read_dword(SH4_IOPORT_16) & ~m_ioport16_direction) | (m_m[PDTRA] & m_ioport16_direction); break; case PDTRB: - if (sh4->m[BCR2] & 1) - return (sh4->io->read_dword(SH4_IOPORT_4) & ~sh4->ioport4_direction) | (sh4->m[PDTRB] & sh4->ioport4_direction); + if (m_m[BCR2] & 1) + return (m_io->read_dword(SH4_IOPORT_4) & ~m_ioport4_direction) | (m_m[PDTRB] & m_ioport4_direction); break; // SCIF (UART with FIFO) case SCFSR2: return 0x60; //read-only status register } - return sh4->m[offset]; + return m_m[offset]; } -void sh4_set_frt_input(device_t *device, int state) +void sh34_base_device::sh4_set_frt_input(int state) { - sh4_state *sh4 = get_safe_token(device); - - if (sh4->cpu_type != CPU_TYPE_SH4) - fatalerror("sh4_set_frt_input uses sh4->m[] with SH3\n"); + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_set_frt_input uses m_m[] with SH3\n"); if(state == PULSE_LINE) { - sh4_set_frt_input(device, ASSERT_LINE); - sh4_set_frt_input(device, CLEAR_LINE); + sh4_set_frt_input(ASSERT_LINE); + sh4_set_frt_input(CLEAR_LINE); return; } - if(sh4->frt_input == state) { + if(m_frt_input == state) { return; } - sh4->frt_input = state; + m_frt_input = state; - if (sh4->cpu_type == CPU_TYPE_SH4) + if (m_cpu_type == CPU_TYPE_SH4) { - if(sh4->m[5] & 0x8000) { + if(m_m[5] & 0x8000) { if(state == CLEAR_LINE) { return; } @@ -1020,32 +1009,30 @@ void sh4_set_frt_input(device_t *device, int state) } else { - fatalerror("sh4_set_frt_input uses sh4->m[] with SH3\n"); + fatalerror("sh4_set_frt_input uses m_m[] with SH3\n"); } #if 0 sh4_timer_resync(); - sh4->icr = sh4->frc; - sh4->m[4] |= ICF; - logerror("SH4 '%s': ICF activated (%x)\n", sh4->device->tag(), sh4->pc & AM); + m_icr = m_frc; + m_m[4] |= ICF; + logerror("SH4 '%s': ICF activated (%x)\n", tag(), m_pc & AM); sh4_recalc_irq(); #endif } -void sh4_set_irln_input(device_t *device, int value) +void sh34_base_device::sh4_set_irln_input(int value) { - sh4_state *sh4 = get_safe_token(device); - - if (sh4->irln == value) + if (m_irln == value) return; - sh4->irln = value; - device->execute().set_input_line(SH4_IRLn, ASSERT_LINE); - device->execute().set_input_line(SH4_IRLn, CLEAR_LINE); + m_irln = value; + set_input_line(SH4_IRLn, ASSERT_LINE); + set_input_line(SH4_IRLn, CLEAR_LINE); } -void sh4_set_irq_line(sh4_state *sh4, int irqline, int state) // set state of external interrupt line +void sh34_base_device::execute_set_input(int irqline, int state) // set state of external interrupt line { - if (sh4->cpu_type == CPU_TYPE_SH3) + if (m_cpu_type == CPU_TYPE_SH3) { /***** ASSUME THIS TO BE WRONG FOR NOW *****/ @@ -1057,19 +1044,19 @@ void sh4_set_irq_line(sh4_state *sh4, int irqline, int state) // set state of ex { //if (irqline > SH4_IRL3) // return; - if (sh4->irq_line_state[irqline] == state) + if (m_irq_line_state[irqline] == state) return; - sh4->irq_line_state[irqline] = state; + m_irq_line_state[irqline] = state; if( state == CLEAR_LINE ) { - LOG(("SH-4 '%s' cleared external irq IRL%d\n", sh4->device->tag(), irqline)); - sh4_exception_unrequest(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0); + LOG(("SH-4 '%s' cleared external irq IRL%d\n", tag(), irqline)); + sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0); } else { - LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4->device->tag(), irqline)); - sh4_exception_request(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0); + LOG(("SH-4 '%s' assert external irq IRL%d\n", tag(), irqline)); + sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0); } } @@ -1082,147 +1069,122 @@ void sh4_set_irq_line(sh4_state *sh4, int irqline, int state) // set state of ex if (irqline == INPUT_LINE_NMI) { - if (sh4->nmi_line_state == state) + if (m_nmi_line_state == state) return; - if (sh4->m[ICR] & 0x100) + if (m_m[ICR] & 0x100) { - if ((state == CLEAR_LINE) && (sh4->nmi_line_state == ASSERT_LINE)) // rising + if ((state == CLEAR_LINE) && (m_nmi_line_state == ASSERT_LINE)) // rising { - LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag())); - sh4_exception_request(sh4, SH4_INTC_NMI); - sh4_dmac_nmi(sh4); + LOG(("SH-4 '%s' assert nmi\n", tag())); + sh4_exception_request(SH4_INTC_NMI); + sh4_dmac_nmi(); } } else { - if ((state == ASSERT_LINE) && (sh4->nmi_line_state == CLEAR_LINE)) // falling + if ((state == ASSERT_LINE) && (m_nmi_line_state == CLEAR_LINE)) // falling { - LOG(("SH-4 '%s' assert nmi\n", sh4->device->tag())); - sh4_exception_request(sh4, SH4_INTC_NMI); - sh4_dmac_nmi(sh4); + LOG(("SH-4 '%s' assert nmi\n", tag())); + sh4_exception_request(SH4_INTC_NMI); + sh4_dmac_nmi(); } } if (state == CLEAR_LINE) - sh4->m[ICR] ^= 0x8000; + m_m[ICR] ^= 0x8000; else - sh4->m[ICR] |= 0x8000; - sh4->nmi_line_state = state; + m_m[ICR] |= 0x8000; + m_nmi_line_state = state; } else { - if (sh4->m[ICR] & 0x80) // four independent external interrupt sources + if (m_m[ICR] & 0x80) // four independent external interrupt sources { if (irqline > SH4_IRL3) return; - if (sh4->irq_line_state[irqline] == state) + if (m_irq_line_state[irqline] == state) return; - sh4->irq_line_state[irqline] = state; + m_irq_line_state[irqline] = state; if( state == CLEAR_LINE ) { - LOG(("SH-4 '%s' cleared external irq IRL%d\n", sh4->device->tag(), irqline)); - sh4_exception_unrequest(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0); + LOG(("SH-4 '%s' cleared external irq IRL%d\n", tag(), irqline)); + sh4_exception_unrequest(SH4_INTC_IRL0+irqline-SH4_IRL0); } else { - LOG(("SH-4 '%s' assert external irq IRL%d\n", sh4->device->tag(), irqline)); - sh4_exception_request(sh4, SH4_INTC_IRL0+irqline-SH4_IRL0); + LOG(("SH-4 '%s' assert external irq IRL%d\n", tag(), irqline)); + sh4_exception_request(SH4_INTC_IRL0+irqline-SH4_IRL0); } } else // level-encoded interrupt { if (irqline != SH4_IRLn) return; - if ((sh4->irln > 15) || (sh4->irln < 0)) + if ((m_irln > 15) || (m_irln < 0)) return; for (s = 0; s < 15; s++) - sh4_exception_unrequest(sh4, SH4_INTC_IRLn0+s); - if (sh4->irln < 15) - sh4_exception_request(sh4, SH4_INTC_IRLn0+sh4->irln); - LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", sh4->device->tag(), sh4->irln)); + sh4_exception_unrequest(SH4_INTC_IRLn0+s); + if (m_irln < 15) + sh4_exception_request(SH4_INTC_IRLn0+m_irln); + LOG(("SH-4 '%s' IRLn0-IRLn3 level #%d\n", tag(), m_irln)); } } - if (sh4->test_irq && (!sh4->delay)) - sh4_check_pending_irq(sh4, "sh4_set_irq_line"); + if (m_test_irq && (!m_delay)) + sh4_check_pending_irq("sh4_set_irq_line"); } } -void sh4_parse_configuration(sh4_state *sh4, const struct sh4_config *conf) +void sh34_base_device::sh4_parse_configuration() { - if(conf) + if(c_clock > 0) { - switch((conf->md2 << 2) | (conf->md1 << 1) | (conf->md0)) + switch((c_md2 << 2) | (c_md1 << 1) | (c_md0)) { case 0: - sh4->cpu_clock = conf->clock; - sh4->bus_clock = conf->clock / 4; - sh4->pm_clock = conf->clock / 4; + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 4; + m_pm_clock = c_clock / 4; break; case 1: - sh4->cpu_clock = conf->clock; - sh4->bus_clock = conf->clock / 6; - sh4->pm_clock = conf->clock / 6; + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 6; + m_pm_clock = c_clock / 6; break; case 2: - sh4->cpu_clock = conf->clock; - sh4->bus_clock = conf->clock / 3; - sh4->pm_clock = conf->clock / 6; + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 3; + m_pm_clock = c_clock / 6; break; case 3: - sh4->cpu_clock = conf->clock; - sh4->bus_clock = conf->clock / 3; - sh4->pm_clock = conf->clock / 6; + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 3; + m_pm_clock = c_clock / 6; break; case 4: - sh4->cpu_clock = conf->clock; - sh4->bus_clock = conf->clock / 2; - sh4->pm_clock = conf->clock / 4; + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 2; + m_pm_clock = c_clock / 4; break; case 5: - sh4->cpu_clock = conf->clock; - sh4->bus_clock = conf->clock / 2; - sh4->pm_clock = conf->clock / 4; + m_cpu_clock = c_clock; + m_bus_clock = c_clock / 2; + m_pm_clock = c_clock / 4; break; } - sh4->is_slave = (~(conf->md7)) & 1; + m_is_slave = (~(c_md7)) & 1; } else { - sh4->cpu_clock = 200000000; - sh4->bus_clock = 100000000; - sh4->pm_clock = 50000000; - sh4->is_slave = 0; + m_cpu_clock = 200000000; + m_bus_clock = 100000000; + m_pm_clock = 50000000; + m_is_slave = 0; } } -void sh4_common_init(device_t *device) +UINT32 sh34_base_device::sh4_getsqremap(UINT32 address) { - sh4_state *sh4 = get_safe_token(device); - int i; - - for (i=0; i<3; i++) - { - sh4->timer[i] = device->machine().scheduler().timer_alloc(FUNC(sh4_timer_callback), sh4); - sh4->timer[i]->adjust(attotime::never, i); - } - - for (i=0; i<4; i++) - { - sh4->dma_timer[i] = device->machine().scheduler().timer_alloc(FUNC(sh4_dmac_callback), sh4); - sh4->dma_timer[i]->adjust(attotime::never, i); - } - - sh4->refresh_timer = device->machine().scheduler().timer_alloc(FUNC(sh4_refresh_timer_callback), sh4); - sh4->refresh_timer->adjust(attotime::never); - sh4->refresh_timer_base = 0; - - sh4->rtc_timer = device->machine().scheduler().timer_alloc(FUNC(sh4_rtc_timer_callback), sh4); - sh4->rtc_timer->adjust(attotime::never); -} - -UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address) -{ - if (!sh4->sh4_mmu_enabled) + if (!m_sh4_mmu_enabled) return address; else { @@ -1231,9 +1193,9 @@ UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address) for (i=0;i<64;i++) { - UINT32 topcmp = sh4->sh4_tlb_address[i]&0xfff00000; + UINT32 topcmp = m_sh4_tlb_address[i]&0xfff00000; if (topcmp==topaddr) - return (address&0x000fffff) | ((sh4->sh4_tlb_data[i])&0xfff00000); + return (address&0x000fffff) | ((m_sh4_tlb_data[i])&0xfff00000); } } @@ -1241,38 +1203,34 @@ UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address) return address; } -READ64_MEMBER( sh4_device::sh4_tlb_r ) +READ64_MEMBER( sh4_base_device::sh4_tlb_r ) { - sh4_state *sh4 = get_safe_token(this); - int offs = offset*8; if (offs >= 0x01000000) { UINT8 i = (offs>>8)&63; - return sh4->sh4_tlb_data[i]; + return m_sh4_tlb_data[i]; } else { UINT8 i = (offs>>8)&63; - return sh4->sh4_tlb_address[i]; + return m_sh4_tlb_address[i]; } } -WRITE64_MEMBER( sh4_device::sh4_tlb_w ) +WRITE64_MEMBER( sh4_base_device::sh4_tlb_w ) { - sh4_state *sh4 = get_safe_token(this); - int offs = offset*8; if (offs >= 0x01000000) { UINT8 i = (offs>>8)&63; - sh4->sh4_tlb_data[i] = data&0xffffffff; + m_sh4_tlb_data[i] = data&0xffffffff; } else { UINT8 i = (offs>>8)&63; - sh4->sh4_tlb_address[i] = data&0xffffffff; + m_sh4_tlb_address[i] = data&0xffffffff; } } diff --git a/src/emu/cpu/sh4/sh4comn.h b/src/emu/cpu/sh4/sh4comn.h index 61629077b13..5a04b37402f 100644 --- a/src/emu/cpu/sh4/sh4comn.h +++ b/src/emu/cpu/sh4/sh4comn.h @@ -35,141 +35,23 @@ class sh4_frontend; #define NMIPRI() EXPPRI(3,0,16,SH4_INTC_NMI) #define INTPRI(p,n) EXPPRI(4,2,p,n) -#define FP_RS(r) sh4->fr[(r)] // binary representation of single precision floating point register r -#define FP_RFS(r) *( (float *)(sh4->fr+(r)) ) // single precision floating point register r -#define FP_RFD(r) *( (double *)(sh4->fr+(r)) ) // double precision floating point register r -#define FP_XS(r) sh4->xf[(r)] // binary representation of extended single precision floating point register r -#define FP_XFS(r) *( (float *)(sh4->xf+(r)) ) // single precision extended floating point register r -#define FP_XFD(r) *( (double *)(sh4->xf+(r)) ) // double precision extended floating point register r +#define FP_RS(r) m_fr[(r)] // binary representation of single precision floating point register r +#define FP_RFS(r) *( (float *)(m_fr+(r)) ) // single precision floating point register r +#define FP_RFD(r) *( (double *)(m_fr+(r)) ) // double precision floating point register r +#define FP_XS(r) m_xf[(r)] // binary representation of extended single precision floating point register r +#define FP_XFS(r) *( (float *)(m_xf+(r)) ) // single precision extended floating point register r +#define FP_XFD(r) *( (double *)(m_xf+(r)) ) // double precision extended floating point register r #ifdef LSB_FIRST -#define FP_RS2(r) sh4->fr[(r) ^ sh4->fpu_pr] -#define FP_RFS2(r) *( (float *)(sh4->fr+((r) ^ sh4->fpu_pr)) ) -#define FP_XS2(r) sh4->xf[(r) ^ sh4->fpu_pr] -#define FP_XFS2(r) *( (float *)(sh4->xf+((r) ^ sh4->fpu_pr)) ) +#define FP_RS2(r) m_fr[(r) ^ m_fpu_pr] +#define FP_RFS2(r) *( (float *)(m_fr+((r) ^ m_fpu_pr)) ) +#define FP_XS2(r) m_xf[(r) ^ m_fpu_pr] +#define FP_XFS2(r) *( (float *)(m_xf+((r) ^ m_fpu_pr)) ) #endif +#ifdef USE_SH4DRC struct sh4_state { - UINT32 ppc; - UINT32 pc, spc; - UINT32 pr; - UINT32 sr, ssr; - UINT32 gbr, vbr; - UINT32 mach, macl; - UINT32 r[16], rbnk[2][8], sgr; - UINT32 fr[16], xf[16]; - UINT32 ea; - UINT32 delay; - UINT32 cpu_off; - UINT32 pending_irq; - UINT32 test_irq; - UINT32 fpscr; - UINT32 fpul; - UINT32 dbr; - - UINT32 exception_priority[128]; - int exception_requesting[128]; - - INT8 irq_line_state[17]; - device_irq_acknowledge_delegate irq_callback; - legacy_cpu_device *device; - address_space *internal; - address_space *program; - direct_read_data *direct; - address_space *io; - - // sh4 internal - UINT32 m[16384]; - - // timer regs handled manually for reuse - UINT32 SH4_TSTR; - UINT32 SH4_TCNT0; - UINT32 SH4_TCNT1; - UINT32 SH4_TCNT2; - UINT32 SH4_TCR0; - UINT32 SH4_TCR1; - UINT32 SH4_TCR2; - UINT32 SH4_TCOR0; - UINT32 SH4_TCOR1; - UINT32 SH4_TCOR2; - UINT32 SH4_TOCR; - UINT32 SH4_TCPR2; - - // INTC regs - UINT32 SH4_IPRA; - - UINT32 SH4_IPRC; - - // DMAC regs - UINT32 SH4_SAR0; - UINT32 SH4_SAR1; - UINT32 SH4_SAR2; - UINT32 SH4_SAR3; - - UINT32 SH4_DAR0; - UINT32 SH4_DAR1; - UINT32 SH4_DAR2; - UINT32 SH4_DAR3; - - UINT32 SH4_CHCR0; - UINT32 SH4_CHCR1; - UINT32 SH4_CHCR2; - UINT32 SH4_CHCR3; - - UINT32 SH4_DMATCR0; - UINT32 SH4_DMATCR1; - UINT32 SH4_DMATCR2; - UINT32 SH4_DMATCR3; - - UINT32 SH4_DMAOR; - - - INT8 nmi_line_state; - - UINT8 sleep_mode; - - int frt_input; - int irln; - int internal_irq_level; - int internal_irq_vector; - - emu_timer *dma_timer[4]; - emu_timer *refresh_timer; - emu_timer *rtc_timer; - emu_timer *timer[3]; - UINT32 refresh_timer_base; - int dma_timer_active[4]; - UINT32 dma_source[4]; - UINT32 dma_destination[4]; - UINT32 dma_count[4]; - int dma_wordsize[4]; - int dma_source_increment[4]; - int dma_destination_increment[4]; - int dma_mode[4]; - - int sh4_icount; - int is_slave; - int cpu_clock, bus_clock, pm_clock; - int fpu_sz, fpu_pr; - int ioport16_pullup, ioport16_direction; - int ioport4_pullup, ioport4_direction; - - void (*ftcsr_read_callback)(UINT32 data); - - - /* This MMU simulation is good for the simple remap used on Naomi GD-ROM SQ access *ONLY* */ - UINT32 sh4_tlb_address[64]; - UINT32 sh4_tlb_data[64]; - UINT8 sh4_mmu_enabled; - - int cpu_type; - - // sh3 internal - UINT32 m_sh3internal_upper[0x3000/4]; - UINT32 m_sh3internal_lower[0x1000]; - -#ifdef USE_SH4DRC int icount; int pcfsel; // last pcflush entry set @@ -207,8 +89,8 @@ struct sh4_state UINT32 prefadr; UINT32 target; -#endif }; +#endif #ifdef USE_SH4DRC class sh4_frontend : public drc_frontend @@ -231,22 +113,6 @@ private: sh4_state &m_context; }; - -INLINE sh4_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == SH3LE || device->type() == SH3BE || - device->type() == SH4LE || device->type() == SH4BE ); - return *(sh4_state **)downcast(device)->token(); -} -#else -INLINE sh4_state *get_safe_token(device_t *device) -{ - assert(device != NULL); - assert(device->type() == SH3LE || device->type() == SH3BE || - device->type() == SH4LE || device->type() == SH4BE ); - return (sh4_state *)downcast(device)->token(); -} #endif @@ -302,45 +168,5 @@ enum #define REGFLAG_SSR (1 << 10) #define REGFLAG_SPC (1 << 11) -void sh4_exception_recompute(sh4_state *sh4); // checks if there is any interrupt with high enough priority -void sh4_exception_request(sh4_state *sh4, int exception); // start requesting an exception -void sh4_exception_unrequest(sh4_state *sh4, int exception); // stop requesting an exception -void sh4_exception_checkunrequest(sh4_state *sh4, int exception); -void sh4_exception(sh4_state *sh4, const char *message, int exception); // handle exception -void sh4_change_register_bank(sh4_state *sh4, int to); -void sh4_syncronize_register_bank(sh4_state *sh4, int to); -void sh4_swap_fp_registers(sh4_state *sh4); -void sh4_default_exception_priorities(sh4_state *sh4); // setup default priorities for exceptions -void sh4_parse_configuration(sh4_state *sh4, const struct sh4_config *conf); -void sh4_set_irq_line(sh4_state *sh4, int irqline, int state); // set state of external interrupt line -#ifdef LSB_FIRST -void sh4_swap_fp_couples(sh4_state *sh4); -#endif -void sh4_common_init(device_t *device); -UINT32 sh4_getsqremap(sh4_state *sh4, UINT32 address); -void sh4_handler_ipra_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); - -INLINE void sh4_check_pending_irq(sh4_state *sh4, const char *message) // look for highest priority active exception and handle it -{ - int a,irq,z; - - irq = 0; - z = -1; - for (a=0;a <= SH4_INTC_ROVI;a++) - { - if (sh4->exception_requesting[a]) - { - if ((int)sh4->exception_priority[a] > z) - { - z = sh4->exception_priority[a]; - irq = a; - } - } - } - if (z >= 0) - { - sh4_exception(sh4, message, irq); - } -} #endif /* __SH4COMN_H__ */ diff --git a/src/emu/cpu/sh4/sh4dmac.c b/src/emu/cpu/sh4/sh4dmac.c index f53c8b5a922..af285d88e52 100644 --- a/src/emu/cpu/sh4/sh4dmac.c +++ b/src/emu/cpu/sh4/sh4dmac.c @@ -11,43 +11,42 @@ static const int dmasize[8] = { 8, 1, 2, 4, 32, 0, 0, 0 }; static const int sh3_dmasize[4] = { 1, 2, 4, 16 }; -TIMER_CALLBACK( sh4_dmac_callback ) +TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_dmac_callback ) { - sh4_state *sh4 = (sh4_state *)ptr; int channel = param; - LOG(("SH4 '%s': DMA %d complete\n", sh4->device->tag(), channel)); - sh4->dma_timer_active[channel] = 0; + LOG(("SH4 '%s': DMA %d complete\n", tag(), channel)); + m_dma_timer_active[channel] = 0; switch (channel) { case 0: - sh4->SH4_DMATCR0 = 0; - sh4->SH4_CHCR0 |= CHCR_TE; - if (sh4->SH4_CHCR0 & CHCR_IE) - sh4_exception_request(sh4, SH4_INTC_DMTE0); + m_SH4_DMATCR0 = 0; + m_SH4_CHCR0 |= CHCR_TE; + if (m_SH4_CHCR0 & CHCR_IE) + sh4_exception_request(SH4_INTC_DMTE0); break; case 1: - sh4->SH4_DMATCR1 = 0; - sh4->SH4_CHCR1 |= CHCR_TE; - if (sh4->SH4_CHCR1 & CHCR_IE) - sh4_exception_request(sh4, SH4_INTC_DMTE1); + m_SH4_DMATCR1 = 0; + m_SH4_CHCR1 |= CHCR_TE; + if (m_SH4_CHCR1 & CHCR_IE) + sh4_exception_request(SH4_INTC_DMTE1); break; case 2: - sh4->SH4_DMATCR2 = 0; - sh4->SH4_CHCR2 |= CHCR_TE; - if (sh4->SH4_CHCR2 & CHCR_IE) - sh4_exception_request(sh4, SH4_INTC_DMTE2); + m_SH4_DMATCR2 = 0; + m_SH4_CHCR2 |= CHCR_TE; + if (m_SH4_CHCR2 & CHCR_IE) + sh4_exception_request(SH4_INTC_DMTE2); break; case 3: - sh4->SH4_DMATCR3 = 0; - sh4->SH4_CHCR3 |= CHCR_TE; - if (sh4->SH4_CHCR3 & CHCR_IE) - sh4_exception_request(sh4, SH4_INTC_DMTE3); + m_SH4_DMATCR3 = 0; + m_SH4_CHCR3 |= CHCR_TE; + if (m_SH4_CHCR3 & CHCR_IE) + sh4_exception_request(SH4_INTC_DMTE3); break; } } -static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr) +int sh34_base_device::sh4_dma_transfer(int channel, int timermode, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr) { int incs, incd, size; UINT32 src, dst, count; @@ -55,7 +54,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c incd = (chcr & CHCR_DM) >> 14; incs = (chcr & CHCR_SM) >> 12; - if (sh4->cpu_type == CPU_TYPE_SH4) + if (m_cpu_type == CPU_TYPE_SH4) { size = dmasize[(chcr & CHCR_TS) >> 4]; } @@ -79,13 +78,13 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c if (timermode == 1) // timer actvated after a time based on the number of words to transfer { - sh4->dma_timer_active[channel] = 1; - sh4->dma_timer[channel]->adjust(sh4->device->cycles_to_attotime(2*count+1), channel); + m_dma_timer_active[channel] = 1; + m_dma_timer[channel]->adjust(cycles_to_attotime(2*count+1), channel); } else if (timermode == 2) // timer activated immediately { - sh4->dma_timer_active[channel] = 1; - sh4->dma_timer[channel]->adjust(attotime::zero, channel); + m_dma_timer_active[channel] = 1; + m_dma_timer[channel]->adjust(attotime::zero, channel); } src &= AM; @@ -100,7 +99,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c src --; if(incd == 2) dst --; - sh4->program->write_byte(dst, sh4->program->read_byte(src)); + m_program->write_byte(dst, m_program->read_byte(src)); if(incs == 1) src ++; if(incd == 1) @@ -116,7 +115,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c src -= 2; if(incd == 2) dst -= 2; - sh4->program->write_word(dst, sh4->program->read_word(src)); + m_program->write_word(dst, m_program->read_word(src)); if(incs == 1) src += 2; if(incd == 1) @@ -132,7 +131,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c src -= 8; if(incd == 2) dst -= 8; - sh4->program->write_qword(dst, sh4->program->read_qword(src)); + m_program->write_qword(dst, m_program->read_qword(src)); if(incs == 1) src += 8; if(incd == 1) @@ -149,7 +148,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c src -= 4; if(incd == 2) dst -= 4; - sh4->program->write_dword(dst, sh4->program->read_dword(src)); + m_program->write_dword(dst, m_program->read_dword(src)); if(incs == 1) src += 4; if(incd == 1) @@ -166,10 +165,10 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c src -= 32; if(incd == 2) dst -= 32; - sh4->program->write_qword(dst, sh4->program->read_qword(src)); - sh4->program->write_qword(dst+8, sh4->program->read_qword(src+8)); - sh4->program->write_qword(dst+16, sh4->program->read_qword(src+16)); - sh4->program->write_qword(dst+24, sh4->program->read_qword(src+24)); + m_program->write_qword(dst, m_program->read_qword(src)); + m_program->write_qword(dst+8, m_program->read_qword(src+8)); + m_program->write_qword(dst+16, m_program->read_qword(src+16)); + m_program->write_qword(dst+24, m_program->read_qword(src+24)); if(incs == 1) src += 32; if(incd == 1) @@ -183,7 +182,7 @@ static int sh4_dma_transfer(sh4_state *sh4, int channel, int timermode, UINT32 c return 1; } -static int sh4_dma_transfer_device(sh4_state *sh4, int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr) +int sh34_base_device::sh4_dma_transfer_device(int channel, UINT32 chcr, UINT32 *sar, UINT32 *dar, UINT32 *dmatcr) { int incs, incd, size, mod; UINT32 src, dst, count; @@ -192,7 +191,7 @@ static int sh4_dma_transfer_device(sh4_state *sh4, int channel, UINT32 chcr, UIN incs = (chcr & CHCR_SM) >> 12; - if (sh4->cpu_type == CPU_TYPE_SH4) + if (m_cpu_type == CPU_TYPE_SH4) { size = dmasize[(chcr & CHCR_TS) >> 4]; } @@ -215,207 +214,205 @@ static int sh4_dma_transfer_device(sh4_state *sh4, int channel, UINT32 chcr, UIN LOG(("SH4: DMA %d start device<->memory %x, %x, %x, %04x, %d, %d, %d\n", channel, src, dst, count, chcr, incs, incd, size)); - sh4->dma_timer_active[channel] = 1; + m_dma_timer_active[channel] = 1; src &= AM; dst &= AM; // remember parameters - sh4->dma_source[channel]=src; - sh4->dma_destination[channel]=dst; - sh4->dma_count[channel]=count; - sh4->dma_wordsize[channel]=size; - sh4->dma_source_increment[channel]=incs; - sh4->dma_destination_increment[channel]=incd; - sh4->dma_mode[channel]=mod; + m_dma_source[channel]=src; + m_dma_destination[channel]=dst; + m_dma_count[channel]=count; + m_dma_wordsize[channel]=size; + m_dma_source_increment[channel]=incs; + m_dma_destination_increment[channel]=incd; + m_dma_mode[channel]=mod; // inform device its ready to transfer - sh4->io->write_dword(SH4_IOPORT_DMA, channel | (mod << 16)); + m_io->write_dword(SH4_IOPORT_DMA, channel | (mod << 16)); return 1; } -static void sh4_dmac_check(sh4_state *sh4, int channel) +void sh34_base_device::sh4_dmac_check(int channel) { UINT32 dmatcr, chcr, sar, dar; switch (channel) { case 0: - sar = sh4->SH4_SAR0; - dar = sh4->SH4_DAR0; - chcr = sh4->SH4_CHCR0; - dmatcr = sh4->SH4_DMATCR0; + sar = m_SH4_SAR0; + dar = m_SH4_DAR0; + chcr = m_SH4_CHCR0; + dmatcr = m_SH4_DMATCR0; break; case 1: - sar = sh4->SH4_SAR1; - dar = sh4->SH4_DAR1; - chcr = sh4->SH4_CHCR1; - dmatcr = sh4->SH4_DMATCR1; + sar = m_SH4_SAR1; + dar = m_SH4_DAR1; + chcr = m_SH4_CHCR1; + dmatcr = m_SH4_DMATCR1; break; case 2: - sar = sh4->SH4_SAR2; - dar = sh4->SH4_DAR2; - chcr = sh4->SH4_CHCR2; - dmatcr = sh4->SH4_DMATCR2; + sar = m_SH4_SAR2; + dar = m_SH4_DAR2; + chcr = m_SH4_CHCR2; + dmatcr = m_SH4_DMATCR2; break; case 3: - sar = sh4->SH4_SAR3; - dar = sh4->SH4_DAR3; - chcr = sh4->SH4_CHCR3; - dmatcr = sh4->SH4_DMATCR3; + sar = m_SH4_SAR3; + dar = m_SH4_DAR3; + chcr = m_SH4_CHCR3; + dmatcr = m_SH4_DMATCR3; break; default: return; } - if (chcr & sh4->SH4_DMAOR & DMAOR_DME) + if (chcr & m_SH4_DMAOR & DMAOR_DME) { if ((((chcr & CHCR_RS) >> 8) < 2) || (((chcr & CHCR_RS) >> 8) > 6)) return; - if (!sh4->dma_timer_active[channel] && !(chcr & CHCR_TE) && !(sh4->SH4_DMAOR & (DMAOR_AE | DMAOR_NMIF))) + if (!m_dma_timer_active[channel] && !(chcr & CHCR_TE) && !(m_SH4_DMAOR & (DMAOR_AE | DMAOR_NMIF))) { if (((chcr & CHCR_RS) >> 8) > 3) - sh4_dma_transfer(sh4, channel, 1, chcr, &sar, &dar, &dmatcr); - else if ((sh4->SH4_DMAOR & DMAOR_DDT) == 0) - sh4_dma_transfer_device(sh4, channel, chcr, &sar, &dar, &dmatcr); // tell device we are ready to transfer + sh4_dma_transfer(channel, 1, chcr, &sar, &dar, &dmatcr); + else if ((m_SH4_DMAOR & DMAOR_DDT) == 0) + sh4_dma_transfer_device(channel, chcr, &sar, &dar, &dmatcr); // tell device we are ready to transfer } } else { - if (sh4->dma_timer_active[channel]) + if (m_dma_timer_active[channel]) { logerror("SH4: DMA %d cancelled in-flight but all data transferred", channel); - sh4->dma_timer[channel]->adjust(attotime::never, channel); - sh4->dma_timer_active[channel] = 0; + m_dma_timer[channel]->adjust(attotime::never, channel); + m_dma_timer_active[channel] = 0; } } } // called by drivers to transfer data in a cpu<->device dma. 'device' must be a SH4 cpu -int sh4_dma_data(device_t *device, struct sh4_device_dma *s) +int sh34_base_device::sh4_dma_data(struct sh4_device_dma *s) { UINT32 pos, len, siz; int channel = s->channel; void *data = s->buffer; - sh4_state *sh4 = get_safe_token(device); - - if (!sh4->dma_timer_active[channel]) + if (!m_dma_timer_active[channel]) return 0; - if (sh4->dma_mode[channel] == 2) + if (m_dma_mode[channel] == 2) { // device receives data - len = sh4->dma_count[channel]; + len = m_dma_count[channel]; if (s->length < len) len = s->length; - siz = sh4->dma_wordsize[channel]; + siz = m_dma_wordsize[channel]; for (pos = 0;pos < len;pos++) { switch (siz) { case 8: - if (sh4->dma_source_increment[channel] == 2) - sh4->dma_source[channel] -= 8; - *(UINT64 *)data = sh4->program->read_qword(sh4->dma_source[channel] & ~7); - if (sh4->dma_source_increment[channel] == 1) - sh4->dma_source[channel] += 8; + if (m_dma_source_increment[channel] == 2) + m_dma_source[channel] -= 8; + *(UINT64 *)data = m_program->read_qword(m_dma_source[channel] & ~7); + if (m_dma_source_increment[channel] == 1) + m_dma_source[channel] += 8; break; case 1: - if (sh4->dma_source_increment[channel] == 2) - sh4->dma_source[channel]--; - *(UINT8 *)data = sh4->program->read_byte(sh4->dma_source[channel]); - if (sh4->dma_source_increment[channel] == 1) - sh4->dma_source[channel]++; + if (m_dma_source_increment[channel] == 2) + m_dma_source[channel]--; + *(UINT8 *)data = m_program->read_byte(m_dma_source[channel]); + if (m_dma_source_increment[channel] == 1) + m_dma_source[channel]++; break; case 2: - if (sh4->dma_source_increment[channel] == 2) - sh4->dma_source[channel] -= 2; - *(UINT16 *)data = sh4->program->read_word(sh4->dma_source[channel] & ~1); - if (sh4->dma_source_increment[channel] == 1) - sh4->dma_source[channel] += 2; + if (m_dma_source_increment[channel] == 2) + m_dma_source[channel] -= 2; + *(UINT16 *)data = m_program->read_word(m_dma_source[channel] & ~1); + if (m_dma_source_increment[channel] == 1) + m_dma_source[channel] += 2; break; case 4: - if (sh4->dma_source_increment[channel] == 2) - sh4->dma_source[channel] -= 4; - *(UINT32 *)data = sh4->program->read_dword(sh4->dma_source[channel] & ~3); - if (sh4->dma_source_increment[channel] == 1) - sh4->dma_source[channel] += 4; + if (m_dma_source_increment[channel] == 2) + m_dma_source[channel] -= 4; + *(UINT32 *)data = m_program->read_dword(m_dma_source[channel] & ~3); + if (m_dma_source_increment[channel] == 1) + m_dma_source[channel] += 4; break; case 32: - if (sh4->dma_source_increment[channel] == 2) - sh4->dma_source[channel] -= 32; - *(UINT64 *)data = sh4->program->read_qword(sh4->dma_source[channel] & ~31); - *((UINT64 *)data+1) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+8); - *((UINT64 *)data+2) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+16); - *((UINT64 *)data+3) = sh4->program->read_qword((sh4->dma_source[channel] & ~31)+24); - if (sh4->dma_source_increment[channel] == 1) - sh4->dma_source[channel] += 32; + if (m_dma_source_increment[channel] == 2) + m_dma_source[channel] -= 32; + *(UINT64 *)data = m_program->read_qword(m_dma_source[channel] & ~31); + *((UINT64 *)data+1) = m_program->read_qword((m_dma_source[channel] & ~31)+8); + *((UINT64 *)data+2) = m_program->read_qword((m_dma_source[channel] & ~31)+16); + *((UINT64 *)data+3) = m_program->read_qword((m_dma_source[channel] & ~31)+24); + if (m_dma_source_increment[channel] == 1) + m_dma_source[channel] += 32; break; } - sh4->dma_count[channel]--; + m_dma_count[channel]--; } - if (sh4->dma_count[channel] == 0) // all data transferred ? + if (m_dma_count[channel] == 0) // all data transferred ? { - sh4->dma_timer[channel]->adjust(attotime::zero, channel); + m_dma_timer[channel]->adjust(attotime::zero, channel); return 2; } return 1; } - else if (sh4->dma_mode[channel] == 3) + else if (m_dma_mode[channel] == 3) { // device sends data - len = sh4->dma_count[channel]; + len = m_dma_count[channel]; if (s->length < len) len = s->length; - siz = sh4->dma_wordsize[channel]; + siz = m_dma_wordsize[channel]; for (pos = 0;pos < len;pos++) { switch (siz) { case 8: - if (sh4->dma_destination_increment[channel] == 2) - sh4->dma_destination[channel]-=8; - sh4->program->write_qword(sh4->dma_destination[channel] & ~7, *(UINT64 *)data); - if (sh4->dma_destination_increment[channel] == 1) - sh4->dma_destination[channel]+=8; + if (m_dma_destination_increment[channel] == 2) + m_dma_destination[channel]-=8; + m_program->write_qword(m_dma_destination[channel] & ~7, *(UINT64 *)data); + if (m_dma_destination_increment[channel] == 1) + m_dma_destination[channel]+=8; break; case 1: - if (sh4->dma_destination_increment[channel] == 2) - sh4->dma_destination[channel]--; - sh4->program->write_byte(sh4->dma_destination[channel], *(UINT8 *)data); - if (sh4->dma_destination_increment[channel] == 1) - sh4->dma_destination[channel]++; + if (m_dma_destination_increment[channel] == 2) + m_dma_destination[channel]--; + m_program->write_byte(m_dma_destination[channel], *(UINT8 *)data); + if (m_dma_destination_increment[channel] == 1) + m_dma_destination[channel]++; break; case 2: - if (sh4->dma_destination_increment[channel] == 2) - sh4->dma_destination[channel]-=2; - sh4->program->write_word(sh4->dma_destination[channel] & ~1, *(UINT16 *)data); - if (sh4->dma_destination_increment[channel] == 1) - sh4->dma_destination[channel]+=2; + if (m_dma_destination_increment[channel] == 2) + m_dma_destination[channel]-=2; + m_program->write_word(m_dma_destination[channel] & ~1, *(UINT16 *)data); + if (m_dma_destination_increment[channel] == 1) + m_dma_destination[channel]+=2; break; case 4: - if (sh4->dma_destination_increment[channel] == 2) - sh4->dma_destination[channel]-=4; - sh4->program->write_dword(sh4->dma_destination[channel] & ~3, *(UINT32 *)data); - if (sh4->dma_destination_increment[channel] == 1) - sh4->dma_destination[channel]+=4; + if (m_dma_destination_increment[channel] == 2) + m_dma_destination[channel]-=4; + m_program->write_dword(m_dma_destination[channel] & ~3, *(UINT32 *)data); + if (m_dma_destination_increment[channel] == 1) + m_dma_destination[channel]+=4; break; case 32: - if (sh4->dma_destination_increment[channel] == 2) - sh4->dma_destination[channel]-=32; - sh4->program->write_qword(sh4->dma_destination[channel] & ~31, *(UINT64 *)data); - sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+8, *((UINT64 *)data+1)); - sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+16, *((UINT64 *)data+2)); - sh4->program->write_qword((sh4->dma_destination[channel] & ~31)+24, *((UINT64 *)data+3)); - if (sh4->dma_destination_increment[channel] == 1) - sh4->dma_destination[channel]+=32; + if (m_dma_destination_increment[channel] == 2) + m_dma_destination[channel]-=32; + m_program->write_qword(m_dma_destination[channel] & ~31, *(UINT64 *)data); + m_program->write_qword((m_dma_destination[channel] & ~31)+8, *((UINT64 *)data+1)); + m_program->write_qword((m_dma_destination[channel] & ~31)+16, *((UINT64 *)data+2)); + m_program->write_qword((m_dma_destination[channel] & ~31)+24, *((UINT64 *)data+3)); + if (m_dma_destination_increment[channel] == 1) + m_dma_destination[channel]+=32; break; } - sh4->dma_count[channel]--; + m_dma_count[channel]--; } - if (sh4->dma_count[channel] == 0) // all data transferred ? + if (m_dma_count[channel] == 0) // all data transferred ? { - sh4->dma_timer[channel]->adjust(attotime::zero, channel); + m_dma_timer[channel]->adjust(attotime::zero, channel); return 2; } return 1; @@ -424,83 +421,82 @@ int sh4_dma_data(device_t *device, struct sh4_device_dma *s) return 0; } -// called by drivers to transfer data in a DDT dma. 'device' must be a SH4 cpu -void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s) +// called by drivers to transfer data in a DDT dma. +void sh34_base_device::sh4_dma_ddt(struct sh4_ddt_dma *s) { - sh4_state *sh4 = get_safe_token(device); UINT32 chcr; UINT32 *p32bits; UINT64 *p32bytes; UINT32 pos,len,siz; - if (sh4->cpu_type != CPU_TYPE_SH4) - fatalerror("sh4_dma_ddt uses sh4->m[] with SH3\n"); + if (m_cpu_type != CPU_TYPE_SH4) + fatalerror("sh4_dma_ddt uses m_m[] with SH3\n"); - if (sh4->dma_timer_active[s->channel]) + if (m_dma_timer_active[s->channel]) return; if (s->mode >= 0) { switch (s->channel) { case 0: if (s->mode & 1) - s->source = sh4->SH4_SAR0; + s->source = m_SH4_SAR0; if (s->mode & 2) - sh4->SH4_SAR0 = s->source; + m_SH4_SAR0 = s->source; if (s->mode & 4) - s->destination = sh4->SH4_DAR0; + s->destination = m_SH4_DAR0; if (s->mode & 8) - sh4->SH4_DAR0 = s->destination; + m_SH4_DAR0 = s->destination; break; case 1: if (s->mode & 1) - s->source = sh4->SH4_SAR1; + s->source = m_SH4_SAR1; if (s->mode & 2) - sh4->SH4_SAR1 = s->source; + m_SH4_SAR1 = s->source; if (s->mode & 4) - s->destination = sh4->SH4_DAR1; + s->destination = m_SH4_DAR1; if (s->mode & 8) - sh4->SH4_DAR1 = s->destination; + m_SH4_DAR1 = s->destination; break; case 2: if (s->mode & 1) - s->source = sh4->SH4_SAR2; + s->source = m_SH4_SAR2; if (s->mode & 2) - sh4->SH4_SAR2 = s->source; + m_SH4_SAR2 = s->source; if (s->mode & 4) - s->destination = sh4->SH4_DAR2; + s->destination = m_SH4_DAR2; if (s->mode & 8) - sh4->SH4_DAR2 = s->destination; + m_SH4_DAR2 = s->destination; break; case 3: default: if (s->mode & 1) - s->source = sh4->SH4_SAR3; + s->source = m_SH4_SAR3; if (s->mode & 2) - sh4->SH4_SAR3 = s->source; + m_SH4_SAR3 = s->source; if (s->mode & 4) - s->destination = sh4->SH4_DAR3; + s->destination = m_SH4_DAR3; if (s->mode & 8) - sh4->SH4_DAR3 = s->destination; + m_SH4_DAR3 = s->destination; break; } switch (s->channel) { case 0: - chcr = sh4->SH4_CHCR0; - len = sh4->SH4_DMATCR0; + chcr = m_SH4_CHCR0; + len = m_SH4_DMATCR0; break; case 1: - chcr = sh4->SH4_CHCR1; - len = sh4->SH4_DMATCR1; + chcr = m_SH4_CHCR1; + len = m_SH4_DMATCR1; break; case 2: - chcr = sh4->SH4_CHCR2; - len = sh4->SH4_DMATCR2; + chcr = m_SH4_CHCR2; + len = m_SH4_DMATCR2; break; case 3: default: - chcr = sh4->SH4_CHCR3; - len = sh4->SH4_DMATCR3; + chcr = m_SH4_CHCR3; + len = m_SH4_DMATCR3; break; } if ((s->direction) == 0) { @@ -510,7 +506,7 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s) } - if (sh4->cpu_type == CPU_TYPE_SH4) + if (m_cpu_type == CPU_TYPE_SH4) { //siz = dmasize[(chcr & CHCR_TS) >> 4]; siz = dmasize[(chcr >> 4) & 7]; @@ -524,14 +520,14 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s) if (siz && (s->size)) if ((len * siz) != (s->length * s->size)) return; - sh4_dma_transfer(sh4, s->channel, 0, chcr, &s->source, &s->destination, &len); + sh4_dma_transfer(s->channel, 0, chcr, &s->source, &s->destination, &len); } else { if (s->size == 4) { if ((s->direction) == 0) { len = s->length; p32bits = (UINT32 *)(s->buffer); for (pos = 0;pos < len;pos++) { - *p32bits = sh4->program->read_dword(s->source); + *p32bits = m_program->read_dword(s->source); p32bits++; s->source = s->source + 4; } @@ -539,7 +535,7 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s) len = s->length; p32bits = (UINT32 *)(s->buffer); for (pos = 0;pos < len;pos++) { - sh4->program->write_dword(s->destination, *p32bits); + m_program->write_dword(s->destination, *p32bits); p32bits++; s->destination = s->destination + 4; } @@ -550,7 +546,7 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s) len = s->length * 4; p32bytes = (UINT64 *)(s->buffer); for (pos = 0;pos < len;pos++) { - *p32bytes = sh4->program->read_qword(s->source); + *p32bytes = m_program->read_qword(s->source); p32bytes++; s->destination = s->destination + 8; } @@ -558,7 +554,7 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s) len = s->length * 4; p32bytes = (UINT64 *)(s->buffer); for (pos = 0;pos < len;pos++) { - sh4->program->write_qword(s->destination, *p32bytes); + m_program->write_qword(s->destination, *p32bytes); p32bytes++; s->destination = s->destination + 8; } @@ -568,119 +564,102 @@ void sh4_dma_ddt(device_t *device, struct sh4_ddt_dma *s) } - void sh4_handle_sar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_SAR0); + COMBINE_DATA(&m_SH4_SAR0); } - void sh4_handle_sar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_SAR1); + COMBINE_DATA(&m_SH4_SAR1); } - void sh4_handle_sar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_SAR2); + COMBINE_DATA(&m_SH4_SAR2); } - void sh4_handle_sar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_SAR3); + COMBINE_DATA(&m_SH4_SAR3); } - void sh4_handle_dar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_DAR0); + COMBINE_DATA(&m_SH4_DAR0); } - void sh4_handle_dar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_DAR1); + COMBINE_DATA(&m_SH4_DAR1); } - void sh4_handle_dar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_DAR2); + COMBINE_DATA(&m_SH4_DAR2); } - void sh4_handle_dar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_DAR3); + COMBINE_DATA(&m_SH4_DAR3); } - void sh4_handle_dmatcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_DMATCR0); + COMBINE_DATA(&m_SH4_DMATCR0); } - void sh4_handle_dmatcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_DMATCR1); + COMBINE_DATA(&m_SH4_DMATCR1); } - void sh4_handle_dmatcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_DMATCR2); + COMBINE_DATA(&m_SH4_DMATCR2); } - void sh4_handle_dmatcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_DMATCR3); + COMBINE_DATA(&m_SH4_DMATCR3); } - void sh4_handle_chcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_CHCR0); - sh4_dmac_check(sh4, 0); + COMBINE_DATA(&m_SH4_CHCR0); + sh4_dmac_check(0); } - void sh4_handle_chcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_CHCR1); - sh4_dmac_check(sh4, 1); + COMBINE_DATA(&m_SH4_CHCR1); + sh4_dmac_check(1); } - void sh4_handle_chcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_CHCR2); - sh4_dmac_check(sh4, 2); + COMBINE_DATA(&m_SH4_CHCR2); + sh4_dmac_check(2); } - void sh4_handle_chcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_CHCR3); - sh4_dmac_check(sh4, 3); + COMBINE_DATA(&m_SH4_CHCR3); + sh4_dmac_check(3); } - void sh4_handle_dmaor_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) + void sh34_base_device::sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask) { - UINT32 old = sh4->SH4_DMAOR; - COMBINE_DATA(&sh4->SH4_DMAOR); + UINT32 old = m_SH4_DMAOR; + COMBINE_DATA(&m_SH4_DMAOR); - if ((sh4->SH4_DMAOR & DMAOR_AE) && (~old & DMAOR_AE)) - sh4->SH4_DMAOR &= ~DMAOR_AE; - if ((sh4->SH4_DMAOR & DMAOR_NMIF) && (~old & DMAOR_NMIF)) - sh4->SH4_DMAOR &= ~DMAOR_NMIF; - sh4_dmac_check(sh4, 0); - sh4_dmac_check(sh4, 1); - sh4_dmac_check(sh4, 2); - sh4_dmac_check(sh4, 3); + if ((m_SH4_DMAOR & DMAOR_AE) && (~old & DMAOR_AE)) + m_SH4_DMAOR &= ~DMAOR_AE; + if ((m_SH4_DMAOR & DMAOR_NMIF) && (~old & DMAOR_NMIF)) + m_SH4_DMAOR &= ~DMAOR_NMIF; + sh4_dmac_check(0); + sh4_dmac_check(1); + sh4_dmac_check(2); + sh4_dmac_check(3); } - UINT32 sh4_handle_sar0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR0; } - UINT32 sh4_handle_sar1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR1; } - UINT32 sh4_handle_sar2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR2; } - UINT32 sh4_handle_sar3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_SAR3; } - UINT32 sh4_handle_dar0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR0; } - UINT32 sh4_handle_dar1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR1; } - UINT32 sh4_handle_dar2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR2; } - UINT32 sh4_handle_dar3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DAR3; } - UINT32 sh4_handle_dmatcr0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR0; } - UINT32 sh4_handle_dmatcr1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR1; } - UINT32 sh4_handle_dmatcr2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR2; } - UINT32 sh4_handle_dmatcr3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMATCR3; } - UINT32 sh4_handle_chcr0_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR0; } - UINT32 sh4_handle_chcr1_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR1; } - UINT32 sh4_handle_chcr2_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR2; } - UINT32 sh4_handle_chcr3_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_CHCR3; } - UINT32 sh4_handle_dmaor_addr_r(sh4_state *sh4, UINT32 mem_mask) { return sh4->SH4_DMAOR; } diff --git a/src/emu/cpu/sh4/sh4dmac.h b/src/emu/cpu/sh4/sh4dmac.h index 595f700a6be..cfabd19e658 100644 --- a/src/emu/cpu/sh4/sh4dmac.h +++ b/src/emu/cpu/sh4/sh4dmac.h @@ -27,37 +27,37 @@ TIMER_CALLBACK( sh4_dmac_callback ); -void sh4_handle_sar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_sar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_sar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_sar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_dar0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_dar1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_dar2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_dar3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_dmatcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_dmatcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_dmatcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_dmatcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_chcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_chcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_chcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_chcr3_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_dmaor_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -UINT32 sh4_handle_sar0_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_sar1_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_sar2_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_sar3_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_dar0_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_dar1_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_dar2_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_dar3_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_dmatcr0_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_dmatcr1_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_dmatcr2_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_dmatcr3_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_chcr0_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_chcr1_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_chcr2_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_chcr3_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_dmaor_addr_r(sh4_state *sh4, UINT32 mem_mask); +void sh4_handle_sar0_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_sar1_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_sar2_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_sar3_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_dar0_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_dar1_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_dar2_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_dar3_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_dmatcr0_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_dmatcr1_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_dmatcr2_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_dmatcr3_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_chcr0_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_chcr1_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_chcr2_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_chcr3_addr_w(UINT32 data, UINT32 mem_mask); +void sh4_handle_dmaor_addr_w(UINT32 data, UINT32 mem_mask); +UINT32 sh4_handle_sar0_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_sar1_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_sar2_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_sar3_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_dar0_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_dar1_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_dar2_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_dar3_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_dmatcr0_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_dmatcr1_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_dmatcr2_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_dmatcr3_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_chcr0_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_chcr1_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_chcr2_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_chcr3_addr_r(UINT32 mem_mask); +UINT32 sh4_handle_dmaor_addr_r(UINT32 mem_mask); diff --git a/src/emu/cpu/sh4/sh4tmu.c b/src/emu/cpu/sh4/sh4tmu.c index 7a9ebc71c05..6c906143e70 100644 --- a/src/emu/cpu/sh4/sh4tmu.c +++ b/src/emu/cpu/sh4/sh4tmu.c @@ -27,7 +27,7 @@ static UINT32 compute_ticks_timer(emu_timer *timer, int hertz, int divisor) return (UINT32)ret; } -static void sh4_timer_recompute(sh4_state *sh4, int which) +void sh34_base_device::sh4_timer_recompute(int which) { double ticks; @@ -36,61 +36,60 @@ static void sh4_timer_recompute(sh4_state *sh4, int which) switch (which) { case 0: - tcr = sh4->SH4_TCR0; - tcnt = sh4->SH4_TCNT0; + tcr = m_SH4_TCR0; + tcnt = m_SH4_TCNT0; break; case 1: - tcr = sh4->SH4_TCR1; - tcnt = sh4->SH4_TCNT1; + tcr = m_SH4_TCR1; + tcnt = m_SH4_TCNT1; break; case 2: - tcr = sh4->SH4_TCR2; - tcnt = sh4->SH4_TCNT2; + tcr = m_SH4_TCR2; + tcnt = m_SH4_TCNT2; break; } ticks = tcnt; - sh4->timer[which]->adjust(sh4_scale_up_mame_time(attotime::from_hz(sh4->pm_clock) * tcnt_div[tcr & 7], ticks), which); + m_timer[which]->adjust(sh4_scale_up_mame_time(attotime::from_hz(m_pm_clock) * tcnt_div[tcr & 7], ticks), which); } -TIMER_CALLBACK( sh4_timer_callback ) +TIMER_CALLBACK_MEMBER( sh34_base_device::sh4_timer_callback ) { - sh4_state *sh4 = (sh4_state *)ptr; int which = param; switch (which) { case 0: - sh4->SH4_TCNT0 = sh4->SH4_TCOR0; + m_SH4_TCNT0 = m_SH4_TCOR0; break; case 1: - sh4->SH4_TCNT1 = sh4->SH4_TCOR1; + m_SH4_TCNT1 = m_SH4_TCOR1; break; case 2: - sh4->SH4_TCNT2 = sh4->SH4_TCOR2; + m_SH4_TCNT2 = m_SH4_TCOR2; break; } - sh4_timer_recompute(sh4, which); + sh4_timer_recompute(which); switch (which) { case 0: - sh4->SH4_TCR0 |= 0x100; + m_SH4_TCR0 |= 0x100; break; case 1: - sh4->SH4_TCR1 |= 0x100; + m_SH4_TCR1 |= 0x100; break; case 2: - sh4->SH4_TCR2 |= 0x100; + m_SH4_TCR2 |= 0x100; break; } @@ -98,25 +97,25 @@ TIMER_CALLBACK( sh4_timer_callback ) switch (which) { case 0: - if (sh4->SH4_TCR0 & 0x20) + if (m_SH4_TCR0 & 0x20) { - sh4_exception_request(sh4, SH4_INTC_TUNI0); + sh4_exception_request(SH4_INTC_TUNI0); // logerror("SH4_INTC_TUNI0 requested\n"); } break; case 1: - if (sh4->SH4_TCR1 & 0x20) + if (m_SH4_TCR1 & 0x20) { - sh4_exception_request(sh4, SH4_INTC_TUNI1); + sh4_exception_request(SH4_INTC_TUNI1); // logerror("SH4_INTC_TUNI1 requested\n"); } break; case 2: - if (sh4->SH4_TCR2 & 0x20) + if (m_SH4_TCR2 & 0x20) { - sh4_exception_request(sh4, SH4_INTC_TUNI2); + sh4_exception_request(SH4_INTC_TUNI2); // logerror("SH4_INTC_TUNI2 requested\n"); } break; @@ -125,199 +124,199 @@ TIMER_CALLBACK( sh4_timer_callback ) } -UINT32 sh4_handle_tcnt0_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tcnt0_addr_r(UINT32 mem_mask) { - if (sh4->SH4_TSTR & 1) - return compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->SH4_TCR0 & 7]); + if (m_SH4_TSTR & 1) + return compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]); else - return sh4->SH4_TCNT0; + return m_SH4_TCNT0; } -UINT32 sh4_handle_tcnt1_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tcnt1_addr_r(UINT32 mem_mask) { - if (sh4->SH4_TSTR & 2) - return compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->SH4_TCR1 & 7]); + if (m_SH4_TSTR & 2) + return compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]); else - return sh4->SH4_TCNT1; + return m_SH4_TCNT1; } -UINT32 sh4_handle_tcnt2_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tcnt2_addr_r(UINT32 mem_mask) { - if (sh4->SH4_TSTR & 4) - return compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->SH4_TCR2 & 7]); + if (m_SH4_TSTR & 4) + return compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]); else - return sh4->SH4_TCNT2; + return m_SH4_TCNT2; } -UINT32 sh4_handle_tcor0_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tcor0_addr_r(UINT32 mem_mask) { - return sh4->SH4_TCOR0; + return m_SH4_TCOR0; } -UINT32 sh4_handle_tcor1_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tcor1_addr_r(UINT32 mem_mask) { - return sh4->SH4_TCOR1; + return m_SH4_TCOR1; } -UINT32 sh4_handle_tcor2_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tcor2_addr_r(UINT32 mem_mask) { - return sh4->SH4_TCOR2; + return m_SH4_TCOR2; } -UINT32 sh4_handle_tcr0_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tcr0_addr_r(UINT32 mem_mask) { - return sh4->SH4_TCR0; + return m_SH4_TCR0; } -UINT32 sh4_handle_tcr1_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tcr1_addr_r(UINT32 mem_mask) { - return sh4->SH4_TCR1; + return m_SH4_TCR1; } -UINT32 sh4_handle_tcr2_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tcr2_addr_r(UINT32 mem_mask) { - return sh4->SH4_TCR2; + return m_SH4_TCR2; } -UINT32 sh4_handle_tstr_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tstr_addr_r(UINT32 mem_mask) { - return sh4->SH4_TSTR; + return m_SH4_TSTR; } -UINT32 sh4_handle_tocr_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tocr_addr_r(UINT32 mem_mask) { - return sh4->SH4_TOCR; + return m_SH4_TOCR; } -UINT32 sh4_handle_tcpr2_addr_r(sh4_state *sh4, UINT32 mem_mask) +UINT32 sh34_base_device::sh4_handle_tcpr2_addr_r(UINT32 mem_mask) { - return sh4->SH4_TCPR2; + return m_SH4_TCPR2; } -void sh4_handle_tstr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tstr_addr_w(UINT32 data, UINT32 mem_mask) { - UINT32 old2 = sh4->SH4_TSTR; - COMBINE_DATA(&sh4->SH4_TSTR); + UINT32 old2 = m_SH4_TSTR; + COMBINE_DATA(&m_SH4_TSTR); if (old2 & 1) - sh4->SH4_TCNT0 = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->SH4_TCR0 & 7]); - if ((sh4->SH4_TSTR & 1) == 0) { - sh4->timer[0]->adjust(attotime::never); + m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]); + if ((m_SH4_TSTR & 1) == 0) { + m_timer[0]->adjust(attotime::never); } else - sh4_timer_recompute(sh4, 0); + sh4_timer_recompute(0); if (old2 & 2) - sh4->SH4_TCNT1 = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->SH4_TCR1 & 7]); - if ((sh4->SH4_TSTR & 2) == 0) { - sh4->timer[1]->adjust(attotime::never); + m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]); + if ((m_SH4_TSTR & 2) == 0) { + m_timer[1]->adjust(attotime::never); } else - sh4_timer_recompute(sh4, 1); + sh4_timer_recompute(1); if (old2 & 4) - sh4->SH4_TCNT2 = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->SH4_TCR2 & 7]); - if ((sh4->SH4_TSTR & 4) == 0) { - sh4->timer[2]->adjust(attotime::never); + m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]); + if ((m_SH4_TSTR & 4) == 0) { + m_timer[2]->adjust(attotime::never); } else - sh4_timer_recompute(sh4, 2); + sh4_timer_recompute(2); } -void sh4_handle_tcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tcr0_addr_w(UINT32 data, UINT32 mem_mask) { - UINT32 old2 = sh4->SH4_TCR0; - COMBINE_DATA(&sh4->SH4_TCR0); - if (sh4->SH4_TSTR & 1) + UINT32 old2 = m_SH4_TCR0; + COMBINE_DATA(&m_SH4_TCR0); + if (m_SH4_TSTR & 1) { - sh4->SH4_TCNT0 = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[old2 & 7]); - sh4_timer_recompute(sh4, 0); + m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[old2 & 7]); + sh4_timer_recompute(0); } - if (!(sh4->SH4_TCR0 & 0x20) || !(sh4->SH4_TCR0 & 0x100)) - sh4_exception_unrequest(sh4, SH4_INTC_TUNI0); + if (!(m_SH4_TCR0 & 0x20) || !(m_SH4_TCR0 & 0x100)) + sh4_exception_unrequest(SH4_INTC_TUNI0); } -void sh4_handle_tcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tcr1_addr_w(UINT32 data, UINT32 mem_mask) { - UINT32 old2 = sh4->SH4_TCR1; - COMBINE_DATA(&sh4->SH4_TCR1); - if (sh4->SH4_TSTR & 2) + UINT32 old2 = m_SH4_TCR1; + COMBINE_DATA(&m_SH4_TCR1); + if (m_SH4_TSTR & 2) { - sh4->SH4_TCNT1 = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[old2 & 7]); - sh4_timer_recompute(sh4, 1); + m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[old2 & 7]); + sh4_timer_recompute(1); } - if (!(sh4->SH4_TCR1 & 0x20) || !(sh4->SH4_TCR1 & 0x100)) - sh4_exception_unrequest(sh4, SH4_INTC_TUNI1); + if (!(m_SH4_TCR1 & 0x20) || !(m_SH4_TCR1 & 0x100)) + sh4_exception_unrequest(SH4_INTC_TUNI1); } -void sh4_handle_tcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tcr2_addr_w(UINT32 data, UINT32 mem_mask) { - UINT32 old2 = sh4->SH4_TCR2; - COMBINE_DATA(&sh4->SH4_TCR2); - if (sh4->SH4_TSTR & 4) + UINT32 old2 = m_SH4_TCR2; + COMBINE_DATA(&m_SH4_TCR2); + if (m_SH4_TSTR & 4) { - sh4->SH4_TCNT2 = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[old2 & 7]); - sh4_timer_recompute(sh4, 2); + m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[old2 & 7]); + sh4_timer_recompute(2); } - if (!(sh4->SH4_TCR2 & 0x20) || !(sh4->SH4_TCR2 & 0x100)) - sh4_exception_unrequest(sh4, SH4_INTC_TUNI2); + if (!(m_SH4_TCR2 & 0x20) || !(m_SH4_TCR2 & 0x100)) + sh4_exception_unrequest(SH4_INTC_TUNI2); } -void sh4_handle_tcor0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tcor0_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_TCOR0); - if (sh4->SH4_TSTR & 1) + COMBINE_DATA(&m_SH4_TCOR0); + if (m_SH4_TSTR & 1) { - sh4->SH4_TCNT0 = compute_ticks_timer(sh4->timer[0], sh4->pm_clock, tcnt_div[sh4->SH4_TCR0 & 7]); - sh4_timer_recompute(sh4, 0); + m_SH4_TCNT0 = compute_ticks_timer(m_timer[0], m_pm_clock, tcnt_div[m_SH4_TCR0 & 7]); + sh4_timer_recompute(0); } } -void sh4_handle_tcor1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tcor1_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_TCOR1); - if (sh4->SH4_TSTR & 2) + COMBINE_DATA(&m_SH4_TCOR1); + if (m_SH4_TSTR & 2) { - sh4->SH4_TCNT1 = compute_ticks_timer(sh4->timer[1], sh4->pm_clock, tcnt_div[sh4->SH4_TCR1 & 7]); - sh4_timer_recompute(sh4, 1); + m_SH4_TCNT1 = compute_ticks_timer(m_timer[1], m_pm_clock, tcnt_div[m_SH4_TCR1 & 7]); + sh4_timer_recompute(1); } } -void sh4_handle_tcor2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tcor2_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_TCOR2); - if (sh4->SH4_TSTR & 4) + COMBINE_DATA(&m_SH4_TCOR2); + if (m_SH4_TSTR & 4) { - sh4->SH4_TCNT2 = compute_ticks_timer(sh4->timer[2], sh4->pm_clock, tcnt_div[sh4->SH4_TCR2 & 7]); - sh4_timer_recompute(sh4, 2); + m_SH4_TCNT2 = compute_ticks_timer(m_timer[2], m_pm_clock, tcnt_div[m_SH4_TCR2 & 7]); + sh4_timer_recompute(2); } } -void sh4_handle_tcnt0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tcnt0_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_TCNT0); - if (sh4->SH4_TSTR & 1) - sh4_timer_recompute(sh4, 0); + COMBINE_DATA(&m_SH4_TCNT0); + if (m_SH4_TSTR & 1) + sh4_timer_recompute(0); } -void sh4_handle_tcnt1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tcnt1_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_TCNT1); - if (sh4->SH4_TSTR & 2) - sh4_timer_recompute(sh4, 1); + COMBINE_DATA(&m_SH4_TCNT1); + if (m_SH4_TSTR & 2) + sh4_timer_recompute(1); } -void sh4_handle_tcnt2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tcnt2_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_TCNT2); - if (sh4->SH4_TSTR & 4) - sh4_timer_recompute(sh4, 2); + COMBINE_DATA(&m_SH4_TCNT2); + if (m_SH4_TSTR & 4) + sh4_timer_recompute(2); } -void sh4_handle_tocr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tocr_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_TOCR); + COMBINE_DATA(&m_SH4_TOCR); } -void sh4_handle_tcpr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask) +void sh34_base_device::sh4_handle_tcpr2_addr_w(UINT32 data, UINT32 mem_mask) { - COMBINE_DATA(&sh4->SH4_TCPR2); + COMBINE_DATA(&m_SH4_TCPR2); } diff --git a/src/emu/cpu/sh4/sh4tmu.h b/src/emu/cpu/sh4/sh4tmu.h index 8b782ebdb32..84840d24e4c 100644 --- a/src/emu/cpu/sh4/sh4tmu.h +++ b/src/emu/cpu/sh4/sh4tmu.h @@ -1,29 +1 @@ /* SH3/4 Timer Unit */ - -TIMER_CALLBACK( sh4_timer_callback ); - -UINT32 sh4_handle_tcnt0_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tcnt1_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tcnt2_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tcor0_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tcor1_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tcor2_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tcr0_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tcr1_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tcr2_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tstr_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tocr_addr_r(sh4_state *sh4, UINT32 mem_mask); -UINT32 sh4_handle_tcpr2_addr_r(sh4_state *sh4, UINT32 mem_mask); - -void sh4_handle_tstr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tcr0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tcr1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tcr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tcor0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tcor1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tcor2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tcnt0_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tcnt1_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tcnt2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tocr_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); -void sh4_handle_tcpr2_addr_w(sh4_state *sh4, UINT32 data, UINT32 mem_mask); diff --git a/src/mame/drivers/aristmk6.c b/src/mame/drivers/aristmk6.c index 8facc551244..d893a9b91dd 100644 --- a/src/mame/drivers/aristmk6.c +++ b/src/mame/drivers/aristmk6.c @@ -130,12 +130,20 @@ INPUT_PORTS_END // ? #define ARISTMK6_CPU_CLOCK XTAL_200MHz // ? -static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, ARISTMK6_CPU_CLOCK }; static MACHINE_CONFIG_START( aristmk6, aristmk6_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", SH4LE, ARISTMK6_CPU_CLOCK) - MCFG_CPU_CONFIG(sh4cpu_config) + MCFG_SH4_MD0(1) + MCFG_SH4_MD1(0) + MCFG_SH4_MD2(1) + MCFG_SH4_MD3(0) + MCFG_SH4_MD4(0) + MCFG_SH4_MD5(1) + MCFG_SH4_MD6(0) + MCFG_SH4_MD7(1) + MCFG_SH4_MD8(0) + MCFG_SH4_CLOCK(ARISTMK6_CPU_CLOCK) MCFG_CPU_PROGRAM_MAP(aristmk6_map) MCFG_CPU_IO_MAP(aristmk6_port) // MCFG_DEVICE_DISABLE() diff --git a/src/mame/drivers/atvtrack.c b/src/mame/drivers/atvtrack.c index 8866f74135d..be66f0d295a 100644 --- a/src/mame/drivers/atvtrack.c +++ b/src/mame/drivers/atvtrack.c @@ -387,17 +387,34 @@ INPUT_PORTS_END // ? #define ATV_CPU_CLOCK 200000000 // ? -static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, ATV_CPU_CLOCK }; static MACHINE_CONFIG_START( atvtrack, atvtrack_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", SH4LE, ATV_CPU_CLOCK) - MCFG_CPU_CONFIG(sh4cpu_config) + MCFG_SH4_MD0(1) + MCFG_SH4_MD1(0) + MCFG_SH4_MD2(1) + MCFG_SH4_MD3(0) + MCFG_SH4_MD4(0) + MCFG_SH4_MD5(1) + MCFG_SH4_MD6(0) + MCFG_SH4_MD7(1) + MCFG_SH4_MD8(0) + MCFG_SH4_CLOCK(ATV_CPU_CLOCK) MCFG_CPU_PROGRAM_MAP(atvtrack_main_map) MCFG_CPU_IO_MAP(atvtrack_main_port) MCFG_CPU_ADD("subcpu", SH4LE, ATV_CPU_CLOCK) - MCFG_CPU_CONFIG(sh4cpu_config) + MCFG_SH4_MD0(1) + MCFG_SH4_MD1(0) + MCFG_SH4_MD2(1) + MCFG_SH4_MD3(0) + MCFG_SH4_MD4(0) + MCFG_SH4_MD5(1) + MCFG_SH4_MD6(0) + MCFG_SH4_MD7(1) + MCFG_SH4_MD8(0) + MCFG_SH4_CLOCK(ATV_CPU_CLOCK) MCFG_CPU_PROGRAM_MAP(atvtrack_sub_map) MCFG_CPU_IO_MAP(atvtrack_sub_port) diff --git a/src/mame/drivers/cv1k.c b/src/mame/drivers/cv1k.c index 063b175cb48..4628edaa7d6 100644 --- a/src/mame/drivers/cv1k.c +++ b/src/mame/drivers/cv1k.c @@ -404,24 +404,6 @@ static INPUT_PORTS_START( cv1k ) INPUT_PORTS_END - -// none of this is verified -// (the sh3 is different to the sh4 anyway, should be changed) -static const struct sh4_config sh4cpu_config = { - 0, // md2 (clock divders) - 0, // md1 (clock divders) - 0, // md0 (clock divders) - 0, - 0, - 0, - 1, - 1, // md7 (master?) - 0, - CPU_CLOCK // influences music sequencing in ddpdfk at least -}; - - - INTERRUPT_GEN_MEMBER(cv1k_state::cv1k_interrupt) { m_maincpu->set_input_line(2, HOLD_LINE); @@ -439,7 +421,16 @@ MACHINE_RESET_MEMBER( cv1k_state, cv1k ) static MACHINE_CONFIG_START( cv1k, cv1k_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", SH3BE, CPU_CLOCK) - MCFG_CPU_CONFIG(sh4cpu_config) + MCFG_SH4_MD0(0) // none of this is verified + MCFG_SH4_MD1(0) // (the sh3 is different to the sh4 anyway, should be changed) + MCFG_SH4_MD2(0) + MCFG_SH4_MD3(0) + MCFG_SH4_MD4(0) + MCFG_SH4_MD5(1) + MCFG_SH4_MD6(0) + MCFG_SH4_MD7(1) + MCFG_SH4_MD8(0) + MCFG_SH4_CLOCK(CPU_CLOCK) MCFG_CPU_PROGRAM_MAP(cv1k_map) MCFG_CPU_IO_MAP(cv1k_port) MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cv1k_state, cv1k_interrupt) @@ -473,7 +464,16 @@ static MACHINE_CONFIG_DERIVED( cv1k_d, cv1k ) MCFG_DEVICE_REMOVE("maincpu") MCFG_CPU_ADD("maincpu", SH3BE, CPU_CLOCK) - MCFG_CPU_CONFIG(sh4cpu_config) + MCFG_SH4_MD0(0) // none of this is verified + MCFG_SH4_MD1(0) // (the sh3 is different to the sh4 anyway, should be changed) + MCFG_SH4_MD2(0) + MCFG_SH4_MD3(0) + MCFG_SH4_MD4(0) + MCFG_SH4_MD5(1) + MCFG_SH4_MD6(0) + MCFG_SH4_MD7(1) + MCFG_SH4_MD8(0) + MCFG_SH4_CLOCK(CPU_CLOCK) MCFG_CPU_PROGRAM_MAP(cv1k_d_map) MCFG_CPU_IO_MAP(cv1k_port) MCFG_DEVICE_VBLANK_INT_DRIVER("screen", cv1k_state, cv1k_interrupt) diff --git a/src/mame/drivers/naomi.c b/src/mame/drivers/naomi.c index 55929b76a67..4851d9ccb31 100644 --- a/src/mame/drivers/naomi.c +++ b/src/mame/drivers/naomi.c @@ -1491,8 +1491,6 @@ Sushi Bar #include "includes/naomi.h" #define CPU_CLOCK (200000000) - /* MD2 MD1 MD0 MD6 MD4 MD3 MD5 MD7 MD8 */ -static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CPU_CLOCK }; READ64_MEMBER(naomi_state::naomi_arm_r ) { @@ -2547,7 +2545,16 @@ MACHINE_RESET_MEMBER(naomi_state,naomi) static MACHINE_CONFIG_START( naomi_aw_base, naomi_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", SH4LE, CPU_CLOCK) // SH4!!! - MCFG_CPU_CONFIG(sh4cpu_config) + MCFG_SH4_MD0(1) + MCFG_SH4_MD1(0) + MCFG_SH4_MD2(1) + MCFG_SH4_MD3(0) + MCFG_SH4_MD4(0) + MCFG_SH4_MD5(1) + MCFG_SH4_MD6(0) + MCFG_SH4_MD7(1) + MCFG_SH4_MD8(0) + MCFG_SH4_CLOCK(CPU_CLOCK) MCFG_CPU_PROGRAM_MAP(naomi_map) MCFG_CPU_IO_MAP(naomi_port) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1) diff --git a/src/mame/includes/dc.h b/src/mame/includes/dc.h index f11be2619f9..98c2d870783 100644 --- a/src/mame/includes/dc.h +++ b/src/mame/includes/dc.h @@ -77,7 +77,7 @@ class dc_state : public driver_device DECLARE_WRITE8_MEMBER( g1_irq ); DECLARE_WRITE8_MEMBER( pvr_irq ); - required_device m_maincpu; + required_device m_maincpu; required_device m_soundcpu; required_device m_powervr2; required_device m_maple; diff --git a/src/mame/machine/dc.c b/src/mame/machine/dc.c index 6fda3d8162f..63e30f0b747 100644 --- a/src/mame/machine/dc.c +++ b/src/mame/machine/dc.c @@ -88,7 +88,7 @@ void dc_state::generic_dma(UINT32 main_adr, void *dma_ptr, UINT32 length, UINT32 ddt.direction = to_mainram; ddt.channel = 0; ddt.mode = -1; - sh4_dma_ddt(m_maincpu, &ddt); + m_maincpu->sh4_dma_ddt(&ddt); } TIMER_CALLBACK_MEMBER(dc_state::aica_dma_irq) @@ -332,7 +332,7 @@ void dc_state::dc_update_interrupt_status() } level=dc_compute_interrupt_level(); - sh4_set_irln_input(m_maincpu, 15-level); + m_maincpu->sh4_set_irln_input(15-level); /* Wave DMA HW trigger */ if(m_wave_dma.flag && ((m_wave_dma.sel & 2) == 2)) @@ -407,7 +407,7 @@ WRITE64_MEMBER(dc_state::dc_sysctrl_w ) ddtdata.direction=0; ddtdata.channel=2; ddtdata.mode=25; //011001 - sh4_dma_ddt(m_maincpu,&ddtdata); + m_maincpu->sh4_dma_ddt(&ddtdata); #if DEBUG_SYSCTRL if ((address >= 0x11000000) && (address <= 0x11FFFFFF)) if (dc_sysctrl_regs[SB_LMMODE0]) diff --git a/src/mame/machine/maple-dc.c b/src/mame/machine/maple-dc.c index a3e05c80e41..f608d54331e 100644 --- a/src/mame/machine/maple-dc.c +++ b/src/mame/machine/maple-dc.c @@ -120,7 +120,7 @@ void maple_dc_device::dma_step() ddtdata.direction = 0; // 0 source to buffer, 1 buffer to source ddtdata.channel = 0; ddtdata.mode = -1; // copy from/to buffer - sh4_dma_ddt(cpu, &ddtdata); + cpu->sh4_dma_ddt(&ddtdata); dma_adr += 8; dma_endflag = header[0] & 0x80000000; @@ -136,7 +136,7 @@ void maple_dc_device::dma_step() ddtdata.direction = 0; // 0 source to buffer, 1 buffer to source ddtdata.channel = 0; ddtdata.mode = -1; // copy from/to buffer - sh4_dma_ddt(cpu, &ddtdata); + cpu->sh4_dma_ddt(&ddtdata); dma_adr += length*4; switch(pattern) { @@ -191,7 +191,7 @@ void maple_dc_device::dma_step() ddtdata.direction = 1; // 0 source to buffer, 1 buffer to source ddtdata.channel = 0; ddtdata.mode = -1; // copy from/to buffer - sh4_dma_ddt(cpu, &ddtdata); + cpu->sh4_dma_ddt(&ddtdata); dma_state = dma_endflag ? DMA_DONE : DMA_SEND; break; } @@ -216,7 +216,7 @@ void maple_dc_device::dma_step() ddtdata.direction = 1; // 0 source to buffer, 1 buffer to source ddtdata.channel = 0; ddtdata.mode = -1; // copy from/to buffer - sh4_dma_ddt(cpu, &ddtdata); + cpu->sh4_dma_ddt(&ddtdata); dma_dest += length*4; } diff --git a/src/mess/drivers/dccons.c b/src/mess/drivers/dccons.c index 445cdf644fb..09f0469318c 100644 --- a/src/mess/drivers/dccons.c +++ b/src/mess/drivers/dccons.c @@ -595,8 +595,6 @@ WRITE_LINE_MEMBER(dc_cons_state::sh4_aica_irq) dc_update_interrupt_status(); } -static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, CPU_CLOCK }; - static MACHINE_CONFIG_FRAGMENT( gdrom_config ) MCFG_DEVICE_MODIFY("cdda") MCFG_SOUND_ROUTE(0, "^^^^lspeaker", 1.0) @@ -606,7 +604,16 @@ MACHINE_CONFIG_END static MACHINE_CONFIG_START( dc, dc_cons_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", SH4LE, CPU_CLOCK) - MCFG_CPU_CONFIG(sh4cpu_config) + MCFG_SH4_MD0(1) + MCFG_SH4_MD1(0) + MCFG_SH4_MD2(1) + MCFG_SH4_MD3(0) + MCFG_SH4_MD4(0) + MCFG_SH4_MD5(1) + MCFG_SH4_MD6(0) + MCFG_SH4_MD7(1) + MCFG_SH4_MD8(0) + MCFG_SH4_CLOCK(CPU_CLOCK) MCFG_CPU_PROGRAM_MAP(dc_map) MCFG_CPU_IO_MAP(dc_port) MCFG_TIMER_DRIVER_ADD_SCANLINE("scantimer", dc_state, dc_scanline, "screen", 0, 1) diff --git a/src/mess/drivers/sh4robot.c b/src/mess/drivers/sh4robot.c index 42e4b8e0bf4..9e8870144c5 100644 --- a/src/mess/drivers/sh4robot.c +++ b/src/mess/drivers/sh4robot.c @@ -54,12 +54,20 @@ ADDRESS_MAP_END static INPUT_PORTS_START( sh4robot ) INPUT_PORTS_END -static const struct sh4_config sh4cpu_config = { 1, 0, 1, 0, 0, 0, 1, 1, 0, 200000000 }; static MACHINE_CONFIG_START( sh4robot, sh4robot_state ) /* basic machine hardware */ MCFG_CPU_ADD("maincpu", SH4LE, 200000000) // SH7750 - MCFG_CPU_CONFIG(sh4cpu_config) + MCFG_SH4_MD0(1) + MCFG_SH4_MD1(0) + MCFG_SH4_MD2(1) + MCFG_SH4_MD3(0) + MCFG_SH4_MD4(0) + MCFG_SH4_MD5(1) + MCFG_SH4_MD6(0) + MCFG_SH4_MD7(1) + MCFG_SH4_MD8(0) + MCFG_SH4_CLOCK(200000000) MCFG_CPU_PROGRAM_MAP(sh4robot_mem) MCFG_CPU_IO_MAP(sh4robot_io) diff --git a/src/mess/machine/dccons.c b/src/mess/machine/dccons.c index 1e12552a2d6..d516fabda28 100644 --- a/src/mess/machine/dccons.c +++ b/src/mess/machine/dccons.c @@ -71,7 +71,7 @@ TIMER_CALLBACK_MEMBER(dc_cons_state::atapi_xfer_end ) ddtdata.channel= 0; ddtdata.mode= -1; // copy from/to buffer printf("ATAPI: DMA one sector to %x, %x remaining\n", atapi_xferbase, atapi_xferlen); - sh4_dma_ddt(m_maincpu, &ddtdata); + m_maincpu->sh4_dma_ddt(&ddtdata); atapi_xferbase += 2048; }