Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-22 08:22:15 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

upd7810: don't change carry flag with inr/dcr opcodes

Browse Source
This commit is contained in:
hap 2022-09-16 20:09:29 +02:00
parent 3a6ab235cb
commit b64b4ef8bb
4 changed files with 79 additions and 157 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

67
src/devices/cpu/upd7810/upd7810.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Juergen Buchmueller
/*****************************************************************************
*
* upd7810.c
* upd7810.cpp
* Portable uPD7810/11, 7810H/11H, 78C10/C11/C14 emulator V0.3
*
* This work is based on the
@ -12,20 +12,38 @@
* not to be confused with the later and incompatible 78K family, though
* its architectural influence is acknowledged.
*
* NS20030115:
* 2002-02-19 (PeT):
* - type selection/gamemaster support added
* - gamemaster init hack? added
* - ORAX added
* - jre negative fixed
* - prefixed opcodes skipping fixed
* - interrupts fixed and improved
* - sub(and related)/add/daa flags fixed
* - mvi ports,... fixed
* - rll, rlr, drll, drlr fixed
* - rets fixed
* - l0, l1 skipping fixed
* - calt fixed
*
* 2003-01-15 (NS):
* - fixed INRW_wa()
* - TODO: add 7807, differences are listed below.
* I only added support for these opcodes needed by homedata.c (yes, I am
* lazy):
* 4C CE (MOV A,PT)
* 48 AC (EXA)
* 48 AD (EXR)
* 48 AE (EXH)
* 48 AF (EXX)
* 50 xx (SKN bit)
* 58 xx (SETB)
* 5B xx (CLR)
* 5D xx (SK bit)
* I only added support for these opcodes needed by homedata.c (yes, I am lazy):
* - 4C CE (MOV A,PT)
* - 48 AC (EXA)
* - 48 AD (EXR)
* - 48 AE (EXH)
* - 48 AF (EXX)
* - 50 xx (SKN bit)
* - 58 xx (SETB)
* - 5B xx (CLR)
* - 5D xx (SK bit)
*
* 2004-05-23 (Hau):
* - gta, gti, dgt fixed
* - working reg opcodes fixed
* - sio input fixed
*
* 2008-02-24 (Wilbert Pol):
* - Added preliminary support for uPD7801
@ -38,32 +56,10 @@
* implementation has not been tested and is probably incorrect.
*
*****************************************************************************/
/* Hau around 23 May 2004
gta, gti, dgt fixed
working reg opcodes fixed
sio input fixed
--
PeT around 19 February 2002
type selection/gamemaster support added
gamemaster init hack? added
ORAX added
jre negativ fixed
prefixed opcodes skipping fixed
interrupts fixed and improved
sub(and related)/add/daa flags fixed
mvi ports,... fixed
rll, rlr, drll, drlr fixed
rets fixed
l0, l1 skipping fixed
calt fixed
*/
/*
7807 DESCRIPTION
PA0 1 64 Vcc
PA1 2 63 Vdd
PA2 3 62 PD7/AD7
@ -185,7 +181,6 @@ In asynchronous mode, you can
DIFFERENCES BETWEEN 7810 and 7807
--------------------------

8
src/devices/cpu/upd7810/upd7810.h
View File

@ -1333,14 +1333,6 @@ protected:
void STAX_H_xx();
void JR();
void CALT_7801();
void DCR_A_7801();
void DCR_B_7801();
void DCR_C_7801();
void DCRW_wa_7801();
void INR_A_7801();
void INR_B_7801();
void INR_C_7801();
void INRW_wa_7801();
void IN();
void OUT();
void MOV_A_S();

125
src/devices/cpu/upd7810/upd7810_opcodes.cpp
View File

@ -8126,14 +8126,13 @@ void upd7810_device::MOV_L_A()
void upd7810_device::INRW_wa()
{
PAIR ea = m_va;
uint8_t tmp, m;
RDOPARG( ea.b.l );
m = RM( ea.d );
tmp = m + 1;
ZHC_ADD( tmp, m, 0 );
WM( ea.d, tmp );
SKIP_CY;
uint8_t m = RM( ea.d ) + 1;
WM( ea.d, m );
if (m == 0)
PSW |= SK;
SET_Z(m);
}
/* 21: 0010 0001 */
@ -8232,14 +8231,13 @@ void upd7810_device::LDAX_Hm()
void upd7810_device::DCRW_wa()
{
PAIR ea = m_va;
uint8_t tmp, m;
RDOPARG( ea.b.l );
m = RM( ea.d );
tmp = m - 1;
ZHC_SUB( tmp, m, 0 );
WM( ea.d, tmp );
SKIP_CY;
uint8_t m = RM( ea.d ) - 1;
WM( ea.d, m );
if (m == 0xff)
PSW |= SK;
SET_Z(m);
}
/* 31: 0011 0001 */
@ -8368,28 +8366,25 @@ void upd7810_device::CALL_w()
/* 41: 0100 0001 */
void upd7810_device::INR_A()
{
uint8_t tmp = A + 1;
ZHC_ADD( tmp, A, 0 );
A = tmp;
SKIP_CY;
if (++A == 0)
PSW |= SK;
SET_Z(A);
}
/* 42: 0100 0010 */
void upd7810_device::INR_B()
{
uint8_t tmp = B + 1;
ZHC_ADD( tmp, B, 0 );
B = tmp;
SKIP_CY;
if (++B == 0)
PSW |= SK;
SET_Z(B);
}
/* 43: 0100 0011 */
void upd7810_device::INR_C()
{
uint8_t tmp = C + 1;
ZHC_ADD( tmp, C, 0 );
C = tmp;
SKIP_CY;
if (++C == 0)
PSW |= SK;
SET_Z(C);
}
/* 44: 0100 0100 llll llll hhhh hhhh */
@ -8490,28 +8485,25 @@ void upd7810_device::EXH()
/* 51: 0101 0001 */
void upd7810_device::DCR_A()
{
uint8_t tmp = A - 1;
ZHC_SUB( tmp, A, 0 );
A = tmp;
SKIP_CY;
if (--A == 0xff)
PSW |= SK;
SET_Z(A);
}
/* 52: 0101 0010 */
void upd7810_device::DCR_B()
{
uint8_t tmp = B - 1;
ZHC_SUB( tmp, B, 0 );
B = tmp;
SKIP_CY;
if (--B == 0xff)
PSW |= SK;
SET_Z(B);
}
/* 53: 0101 0011 */
void upd7810_device::DCR_C()
{
uint8_t tmp = C - 1;
ZHC_SUB( tmp, C, 0 );
C = tmp;
SKIP_CY;
if (--C == 0xff)
PSW |= SK;
SET_Z(C);
}
/* 54: 0101 0100 llll llll hhhh hhhh */
@ -9369,63 +9361,6 @@ void upd7810_device::CALT_7801()
PCH=RM(w.w.l+1);
}
/* DCR(W) and INR(W) instructions do not modify the CY register on at least 78c05 and 78c06 */
void upd7810_device::DCR_A_7801()
{
uint32_t old_CY = PSW & CY;
DCR_A();
PSW = ( PSW & ~CY ) | old_CY;
}
void upd7810_device::DCR_B_7801()
{
uint32_t old_CY = PSW & CY;
DCR_B();
PSW = ( PSW & ~CY ) | old_CY;
}
void upd7810_device::DCR_C_7801()
{
uint32_t old_CY = PSW & CY;
DCR_C();
PSW = ( PSW & ~CY ) | old_CY;
}
void upd7810_device::DCRW_wa_7801()
{
uint32_t old_CY = PSW & CY;
DCRW_wa();
PSW = ( PSW & ~CY ) | old_CY;
}
void upd7810_device::INR_A_7801()
{
uint32_t old_CY = PSW & CY;
INR_A();
PSW = ( PSW & ~CY ) | old_CY;
}
void upd7810_device::INR_B_7801()
{
uint32_t old_CY = PSW & CY;
INR_B();
PSW = ( PSW & ~CY ) | old_CY;
}
void upd7810_device::INR_C_7801()
{
uint32_t old_CY = PSW & CY;
INR_C();
PSW = ( PSW & ~CY ) | old_CY;
}
void upd7810_device::INRW_wa_7801()
{
uint32_t old_CY = PSW & CY;
INRW_wa();
PSW = ( PSW & ~CY ) | old_CY;
}
void upd7810_device::IN()
{
logerror("unimplemented instruction: IN\n");

36
src/devices/cpu/upd7810/upd7810_table.cpp
View File

@ -3617,7 +3617,7 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_7801[256] =
{&upd7810_device::MOV_H_A, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_L_A, 1, 4, 4,L0|L1},
/* 0x20 - 0x3F */
{&upd7810_device::INRW_wa_7801, 2,13,13,L0|L1}, {&upd7810_device::TABLE, 1,19,19,L0|L1},
{&upd7810_device::INRW_wa, 2,13,13,L0|L1}, {&upd7810_device::TABLE, 1,19,19,L0|L1},
{&upd7810_device::INX_DE, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_DE, 1, 7, 7,L0|L1},
{&upd7810_device::LXI_D_w, 3,10,10,L0|L1}, {&upd7810_device::GTIW_wa_xx, 3,13,13,L0|L1},
{&upd7810_device::ADINC_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::GTI_A_xx, 2, 7, 7,L0|L1},
@ -3626,7 +3626,7 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_7801[256] =
{&upd7810_device::LDAX_Dp, 1, 7, 7,L0|L1}, {&upd7810_device::LDAX_Hp, 1, 7, 7,L0|L1},
{&upd7810_device::LDAX_Dm, 1, 7, 7,L0|L1}, {&upd7810_device::LDAX_Hm, 1, 7, 7,L0|L1},
{&upd7810_device::DCRW_wa_7801, 2,13,13,L0|L1}, {&upd7810_device::BLOCK, 1,13,13,L0|L1},
{&upd7810_device::DCRW_wa, 2,13,13,L0|L1}, {&upd7810_device::BLOCK, 1,13,13,L0|L1},
{&upd7810_device::INX_HL, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_HL, 1, 7, 7,L0|L1},
{&upd7810_device::LXI_H_w, 3,10,10, L1}, {&upd7810_device::LTIW_wa_xx, 3,13,13,L0|L1},
{&upd7810_device::SUINB_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::LTI_A_xx, 2, 7, 7,L0|L1},
@ -3636,8 +3636,8 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_7801[256] =
{&upd7810_device::STAX_Dm, 1, 7, 7,L0|L1}, {&upd7810_device::STAX_Hm, 1, 7, 7,L0|L1},
/* 0x40 - 0x5F */
{&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::INR_A_7801, 1, 4, 4,L0|L1},
{&upd7810_device::INR_B_7801, 1, 4, 4,L0|L1}, {&upd7810_device::INR_C_7801, 1, 4, 4,L0|L1},
{&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::INR_A, 1, 4, 4,L0|L1},
{&upd7810_device::INR_B, 1, 4, 4,L0|L1}, {&upd7810_device::INR_C, 1, 4, 4,L0|L1},
{&upd7810_device::CALL_w, 3,16,16,L0|L1}, {&upd7810_device::ONIW_wa_xx, 3,13,13,L0|L1},
{&upd7810_device::ADI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::ONI_A_xx, 2, 7, 7,L0|L1},
{&upd7810_device::PRE_48, 1, 0, 0,L0|L1}, {&upd7810_device::MVIX_BC_xx, 2,10,10,L0|L1},
@ -3645,8 +3645,8 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_7801[256] =
{&upd7810_device::PRE_4C, 1, 0, 0,L0|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0|L1},
{&upd7810_device::JRE, 2,17,17,L0|L1}, {&upd7810_device::JRE, 2,17,17,L0|L1},
{&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_A_7801, 1, 4, 4,L0|L1},
{&upd7810_device::DCR_B_7801, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_C_7801, 1, 4, 4,L0|L1},
{&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_A, 1, 4, 4,L0|L1},
{&upd7810_device::DCR_B, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_C, 1, 4, 4,L0|L1},
{&upd7810_device::JMP_w, 3,10,10,L0|L1}, {&upd7810_device::OFFIW_wa_xx, 3,13,13,L0|L1},
{&upd7810_device::ACI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::OFFI_A_xx, 2, 7, 7,L0|L1},
{&upd7810_device::BIT_0_wa, 2,10,10,L0|L1}, {&upd7810_device::BIT_1_wa, 2,10,10,L0|L1},
@ -4867,7 +4867,7 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c05[256] =
{&upd7810_device::MOV_H_A, 1, 4, 4,L0|L1}, {&upd7810_device::MOV_L_A, 1, 4, 4,L0|L1},
/* 0x20 - 0x3F */
{&upd7810_device::INRW_wa_7801, 2,13,13,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1},
{&upd7810_device::INRW_wa, 2,13,13,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1},
{&upd7810_device::INX_DE, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_DE, 1, 7, 7,L0|L1},
{&upd7810_device::LXI_D_w, 3,10,10,L0|L1}, {&upd7810_device::GTIW_wa_xx, 3,13,13,L0|L1},
{&upd7810_device::ADINC_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::GTI_A_xx, 2, 7, 7,L0|L1},
@ -4876,7 +4876,7 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c05[256] =
{&upd7810_device::LDAX_Dp, 1, 7, 7,L0|L1}, {&upd7810_device::LDAX_Hp, 1, 7, 7,L0|L1},
{&upd7810_device::LDAX_Dm, 1, 7, 7,L0|L1}, {&upd7810_device::LDAX_Hm, 1, 7, 7,L0|L1},
{&upd7810_device::DCRW_wa_7801, 2,13,13,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1},
{&upd7810_device::DCRW_wa, 2,13,13,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1},
{&upd7810_device::INX_HL, 1, 7, 7,L0|L1}, {&upd7810_device::DCX_HL, 1, 7, 7,L0|L1},
{&upd7810_device::LXI_H_w, 3,10,10, L1}, {&upd7810_device::LTIW_wa_xx, 3,13,13,L0|L1},
{&upd7810_device::SUINB_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::LTI_A_xx, 2, 7, 7,L0|L1},
@ -4886,8 +4886,8 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c05[256] =
{&upd7810_device::STAX_Dm, 1, 7, 7,L0|L1}, {&upd7810_device::STAX_Hm, 1, 7, 7,L0|L1},
/* 0x40 - 0x5F */
{&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::INR_A_7801, 1, 4, 4,L0|L1},
{&upd7810_device::INR_B_7801, 1, 4, 4,L0|L1}, {&upd7810_device::INR_C_7801, 1, 4, 4,L0|L1},
{&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::INR_A, 1, 4, 4,L0|L1},
{&upd7810_device::INR_B, 1, 4, 4,L0|L1}, {&upd7810_device::INR_C, 1, 4, 4,L0|L1},
{&upd7810_device::CALL_w, 3,16,16,L0|L1}, {&upd7810_device::ONIW_wa_xx, 3,13,13,L0|L1},
{&upd7810_device::ADI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::ONI_A_xx, 2, 7, 7,L0|L1},
{&upd7810_device::PRE_48, 1, 0, 0,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1},
@ -4895,8 +4895,8 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c05[256] =
{&upd7810_device::PRE_4C, 1, 0, 0,L0|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0|L1},
{&upd7810_device::JRE, 2,13,13,L0|L1}, {&upd7810_device::JRE, 2,13,13,L0|L1},
{&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_A_7801, 1, 4, 4,L0|L1},
{&upd7810_device::DCR_B_7801, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_C_7801, 1, 4, 4,L0|L1},
{&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_A, 1, 4, 4,L0|L1},
{&upd7810_device::DCR_B, 1, 4, 4,L0|L1}, {&upd7810_device::DCR_C, 1, 4, 4,L0|L1},
{&upd7810_device::JMP_w, 3,10,10,L0|L1}, {&upd7810_device::OFFIW_wa_xx, 3,13,13,L0|L1},
{&upd7810_device::ACI_A_xx, 2, 7, 7,L0|L1}, {&upd7810_device::OFFI_A_xx, 2, 7, 7,L0|L1},
{&upd7810_device::illegal, 1, 4, 4,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1},
@ -6118,7 +6118,7 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c06[256] =
{&upd7810_device::MOV_H_A, 1, 6, 6,L0|L1}, {&upd7810_device::MOV_L_A, 1, 6, 6,L0|L1},
/* 0x20 - 0x3F */
{&upd7810_device::INRW_wa_7801, 2,17,17,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1},
{&upd7810_device::INRW_wa, 2,17,17,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1},
{&upd7810_device::INX_DE, 1, 9, 9,L0|L1}, {&upd7810_device::DCX_DE, 1, 9, 9,L0|L1},
{&upd7810_device::LXI_D_w, 3,16,16,L0|L1}, {&upd7810_device::GTIW_wa_xx, 3,19,19,L0|L1},
{&upd7810_device::ADINC_A_xx, 2,11,11,L0|L1}, {&upd7810_device::GTI_A_xx, 2,11,11,L0|L1},
@ -6127,7 +6127,7 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c06[256] =
{&upd7810_device::LDAX_Dp, 1, 9, 9,L0|L1}, {&upd7810_device::LDAX_Hp, 1, 9, 9,L0|L1},
{&upd7810_device::LDAX_Dm, 1, 9, 9,L0|L1}, {&upd7810_device::LDAX_Hm, 1, 9, 9,L0|L1},
{&upd7810_device::DCRW_wa_7801, 2,17,17,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1},
{&upd7810_device::DCRW_wa, 2,17,17,L0|L1}, {&upd7810_device::illegal, 1, 4, 4,L0|L1},
{&upd7810_device::INX_HL, 1, 9, 9,L0|L1}, {&upd7810_device::DCX_HL, 1, 9, 9,L0|L1},
{&upd7810_device::LXI_H_w, 3,16,16, L1}, {&upd7810_device::LTIW_wa_xx, 3,19,19,L0|L1},
{&upd7810_device::SUINB_A_xx, 2,11,11,L0|L1}, {&upd7810_device::LTI_A_xx, 2,11,11,L0|L1},
@ -6137,8 +6137,8 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c06[256] =
{&upd7810_device::STAX_Dm, 1, 9, 9,L0|L1}, {&upd7810_device::STAX_Hm, 1, 9, 9,L0|L1},
/* 0x40 - 0x5F */
{&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::INR_A_7801, 1, 6, 6,L0|L1},
{&upd7810_device::INR_B_7801, 1, 6, 6,L0|L1}, {&upd7810_device::INR_C_7801, 1, 6, 6,L0|L1},
{&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::INR_A, 1, 6, 6,L0|L1},
{&upd7810_device::INR_B, 1, 6, 6,L0|L1}, {&upd7810_device::INR_C, 1, 6, 6,L0|L1},
{&upd7810_device::CALL_w, 3,22,22,L0|L1}, {&upd7810_device::ONIW_wa_xx, 3,19,19,L0|L1},
{&upd7810_device::ADI_A_xx, 2,11,11,L0|L1}, {&upd7810_device::ONI_A_xx, 2,11,11,L0|L1},
{&upd7810_device::PRE_48, 1, 0, 0,L0|L1}, {&upd7810_device::illegal, 1, 6, 6,L0|L1},
@ -6146,8 +6146,8 @@ const struct upd7810_device::opcode_s upd7810_device::s_opXX_78c06[256] =
{&upd7810_device::PRE_4C, 1, 0, 0,L0|L1}, {&upd7810_device::PRE_4D, 1, 0, 0,L0|L1},
{&upd7810_device::JRE, 2,17,17,L0|L1}, {&upd7810_device::JRE, 2,17,17,L0|L1},
{&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::DCR_A_7801, 1, 6, 6,L0|L1},
{&upd7810_device::DCR_B_7801, 1, 6, 6,L0|L1}, {&upd7810_device::DCR_C_7801, 1, 6, 6,L0|L1},
{&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::DCR_A, 1, 6, 6,L0|L1},
{&upd7810_device::DCR_B, 1, 6, 6,L0|L1}, {&upd7810_device::DCR_C, 1, 6, 6,L0|L1},
{&upd7810_device::JMP_w, 3,16,16,L0|L1}, {&upd7810_device::OFFIW_wa_xx, 3,19,19,L0|L1},
{&upd7810_device::ACI_A_xx, 2,11,11,L0|L1}, {&upd7810_device::OFFI_A_xx, 2,11,11,L0|L1},
{&upd7810_device::illegal, 1, 6, 6,L0|L1}, {&upd7810_device::illegal, 1, 6, 6,L0|L1},