Rewrote Rockwell PPS-4 CPU core based on bitsavers.org documents
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@ -1,5 +1,5 @@
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// license:BSD-3-Clause
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// copyright-holders:Miodrag Milanovic
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// copyright-holders:Juergen Buchmueller <pullmoll@t-online.de>
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#ifndef __PPS4_H__
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#define __PPS4_H__
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@ -9,11 +9,20 @@
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***************************************************************************/
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enum
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{
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PPS4_PC,
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PPS4_A,PPS4_X,PPS4_SA,PPS4_SB,PPS4_B,
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PPS4_GENPC = STATE_GENPC,
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PPS4_GENSP = STATE_GENSP,
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PPS4_GENPCBASE = STATE_GENPCBASE
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PPS4_PC,
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PPS4_A,
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PPS4_X,
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PPS4_SA,
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PPS4_SB,
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PPS4_B,
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PPS4_SAG,
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PPS4_I2,
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PPS4_Ip,
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PPS4_GENPC = STATE_GENPC,
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PPS4_GENSP = STATE_GENSP,
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PPS4_GENPCBASE = STATE_GENPCBASE,
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PPS4_PORT_A = 256,
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PPS4_PORT_B = 257
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};
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/***************************************************************************
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@ -26,69 +35,130 @@ enum
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extern const device_type PPS4;
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class pps4_device : public cpu_device
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{
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public:
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// construction/destruction
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pps4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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// construction/destruction
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pps4_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock);
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protected:
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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// device-level overrides
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virtual void device_start();
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virtual void device_reset();
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const { return 1; }
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virtual UINT32 execute_max_cycles() const { return 2; }
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virtual UINT32 execute_input_lines() const { return 0; }
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virtual UINT32 execute_default_irq_vector() const { return 0; }
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virtual void execute_run();
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// device_execute_interface overrides
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virtual UINT32 execute_min_cycles() const { return 1; }
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virtual UINT32 execute_max_cycles() const { return 3; }
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virtual UINT32 execute_input_lines() const { return 0; }
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virtual UINT32 execute_default_irq_vector() const { return 0; }
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virtual void execute_run();
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
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{
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return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) );
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}
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// device_memory_interface overrides
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virtual const address_space_config *memory_space_config(address_spacenum spacenum = AS_0) const
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{
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return (spacenum == AS_PROGRAM) ? &m_program_config : ( (spacenum == AS_IO) ? &m_io_config : ( (spacenum == AS_DATA) ? &m_data_config : NULL ) );
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}
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// device_state_interface overrides
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void state_string_export(const device_state_entry &entry, astring &string);
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// device_state_interface overrides
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void state_string_export(const device_state_entry &entry, astring &string);
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
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virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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// device_disasm_interface overrides
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virtual UINT32 disasm_min_opcode_bytes() const { return 1; }
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virtual UINT32 disasm_max_opcode_bytes() const { return 2; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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private:
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address_space_config m_program_config;
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address_space_config m_data_config;
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address_space_config m_io_config;
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address_space_config m_program_config;
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address_space_config m_data_config;
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address_space_config m_io_config;
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UINT8 m_A; // Accumulator
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UINT8 m_X;
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address_space *m_program;
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direct_read_data *m_direct;
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address_space *m_data;
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address_space *m_io;
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int m_icount;
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PAIR m_P;
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PAIR m_SA;
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PAIR m_SB;
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PAIR m_B; // BU + BM + BL
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UINT8 m_A; //!< Accumulator A(4:1)
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UINT8 m_X; //!< X register X(4:1)
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UINT16 m_P; //!< program counter P(12:1)
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UINT16 m_SA; //!< Shift register SA(12:1)
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UINT16 m_SB; //!< Shift register SB(12:1)
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UINT16 m_SAG; //!< Special address generation mask
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UINT16 m_B; //!< B register B(12:1) (BL, BM and BH)
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UINT8 m_C; //!< Carry flip-flop
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UINT8 m_FF1; //!< Flip-flop 1
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UINT8 m_FF2; //!< Flip-flop 2
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UINT8 m_I; //!< Most recent instruction I(8:1)
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UINT8 m_I2; //!< Most recent parameter I2(8:1)
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UINT8 m_Ip; //!< Previous instruction I(8:1)
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UINT8 m_C; // Carry flag
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UINT8 m_FF1; // Flip-flop 1
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UINT8 m_FF2; // Flip-flop 2
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//! return the contents of B register (made of BU, BM and BL)
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inline UINT16 B() const;
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address_space *m_program;
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direct_read_data *m_direct;
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address_space *m_data;
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address_space *m_io;
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//! return memory at address B(12:1)
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inline UINT8 M();
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int m_icount;
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//! write to memory at address B(12:1)
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inline void W(UINT8 data);
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inline UINT8 ROP();
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inline UINT8 ARG();
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inline void DO_SKIP();
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void execute_one(int opcode);
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//! return the next opcode (also in m_I)
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inline UINT8 ROP();
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//! return the next argument (also in m_I2)
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inline UINT8 ARG();
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void iAD(); //!< Add
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void iADC(); //!< Add with carry-in
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void iADSK(); //!< Add and skip on carry-out
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void iADCSK(); //!< Add with carry-in and skip on carry-out
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void iADI(); //!< Add immediate
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void iDC(); //!< Decimal correction
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void iAND(); //!< Logical AND
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void iOR(); //!< Logical OR
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void iEOR(); //!< Logical Exclusive-OR
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void iCOMP(); //!< Complement
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void iSC(); //!< Set Carry flip-flop
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void iRC(); //!< Reset Carry flip-flop
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void iSF1(); //!< Set FF1
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void iRF1(); //!< Reset FF1
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void iSF2(); //!< Set FF2
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void iRF2(); //!< Reset FF2
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void iLD(); //!< Load accumulator from memory
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void iEX(); //!< Exchange accumulator and memory
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void iEXD(); //!< Exchange accumulator and memory and decrement BL
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void iLDI(); //!< Load accumulator immediate
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void iLAX(); //!< Load accumulator from X register
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void iLXA(); //!< Load X register from accumulator
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void iLABL(); //!< Load accumulator with BL
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void iLBMX(); //!< Load BM with X
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void iLBUA(); //!< Load BU with A
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void iXABL(); //!< Exchange accumulator and BL
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void iXBMX(); //!< Exchange BM and X registers
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void iXAX(); //!< Exchange accumulator and X
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void iXS(); //!< Eychange SA and SB registers
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void iCYS(); //!< Cycle SA register and accumulaor
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void iLB(); //!< Load B indirect
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void iLBL(); //!< Load B long
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void iINCB(); //!< Increment BL
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void iDECB(); //!< Decrement BL
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void iT(); //!< Transfer
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void iTM(); //!< Transfer and mark indirect
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void iTL(); //!< Transfer long
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void iTML(); //!< Transfer and mark long
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void iSKC(); //!< Skip on carry flip-flop
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void iSKZ(); //!< Skip on accumulator zero
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void iSKBI(); //!< Skip if BL equal to immediate
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void iSKF1(); //!< Skip if FF1 equals 1
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void iSKF2(); //!< Skip if FF2 equals 1
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void iRTN(); //!< Return
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void iRTNSK(); //!< Return and skip
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void iIOL(); //!< Input/Output long
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void iDIA(); //!< Discrete input group A
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void iDIB(); //!< Discrete input group B
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void iDOA(); //!< Discrete output group A
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void iSAG(); //!< Special address generation
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void execute_one(); //!< execute one instruction
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};
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#endif
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#endif // __PPS4_H__
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@ -1,135 +1,426 @@
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// license:BSD-3-Clause
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// copyright-holders:Miodrag Milanovic
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// copyright-holders:Juergen Buchmueller <pullmoll@t-online.de>
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/*****************************************************************************
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*
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* pps4dasm.c
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*
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* Rockwell PPS-4 CPU Disassembly
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*
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*
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* TODO: double verify all opcodes with t_Ixx flags
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*
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*****************************************************************************/
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#include "emu.h"
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#define OP(A) oprom[(A) - PC]
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#define ARG(A) opram[(A) - PC]
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typedef enum pps4_token_e {
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t_AD, t_ADC, t_ADSK, t_ADCSK, t_ADI,
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t_DC, t_AND, t_OR, t_EOR, t_COMP,
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t_SC, t_RC, t_SF1, t_RF1, t_SF2,
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t_RF2, t_LD, t_EX, t_EXD, t_LDI,
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t_LAX, t_LXA, t_LABL, t_LBMX, t_LBUA,
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t_XABL, t_XBMX, t_XAX, t_XS, t_CYS,
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t_LB, t_LBL, t_INCB, t_DECB, t_T,
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t_TM, t_TL, t_TML, t_SKC, t_SKZ,
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t_SKBI, t_SKF1, t_SKF2, t_RTN, t_RTNSK,
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t_IOL, t_DIA, t_DIB, t_DOA, t_SAG,
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t_COUNT,
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t_MASK = (1 << 6) - 1,
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t_I3c = 1 << 6, /* immediate 3 bit constant, complemented */
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t_I4 = 1 << 7, /* immediate 4 bit constant */
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t_I4c = 1 << 8, /* immediate 4 bit constant, complemented */
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t_I4p = 1 << 9, /* immediate 4 bit offset into page 3 */
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t_I6p = 1 << 10, /* immediate 6 bit constant; address in current page */
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t_I8 = 1 << 11, /* immediate 8 bit constant (I/O port number) */
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t_I8c = 1 << 12, /* immediate 8 bit constant inverted */
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} pps4_token_e;
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static const char *token_str[t_COUNT] = {
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"ad", /* add */
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"adc", /* add with carry-in */
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"adsk", /* add and skip on carry-out */
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"adcsk", /* add with carry-in and skip on carry-out */
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"adi", /* add immediate */
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"dc", /* decimal correction */
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"and", /* logical and */
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"or", /* logical or */
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"eor", /* logical exclusive-orf */
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"comp", /* complement */
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"sc", /* set C flip-flop */
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"rc", /* reset C flip-flop */
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"sf1", /* set FF1 flip-flop */
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"rf1", /* reset FF1 flip-flop */
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"sf2", /* set FF2 flip-flop */
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"rf2", /* reset FF2 flip-flop */
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"ld", /* load accumulator from memory */
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"ex", /* exchange accumulator and memory */
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"exd", /* exchange accumulator and memory and decrement BL */
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"ldi", /* load accumulator immediate */
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"lax", /* load accumulator from X register */
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"lxa", /* load X register from accumulator */
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"labl", /* load accumulator with BL */
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"lbmx", /* load BM with X */
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"lbua", /* load BU with A */
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"xabl", /* exchange accumulator and BL */
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"xbmx", /* exchange BM and X */
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"xax", /* exchange accumulator and X */
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"xs", /* exchange SA and SB */
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"cys", /* cycle SA register and accumulator */
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"lb", /* load B indirect */
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"lbl", /* load B long */
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"incb", /* increment BL */
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"decb", /* decrement BL */
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"t", /* transfer */
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"tm", /* transfer and mark indirect */
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"tl", /* transfer long */
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"tml", /* transfer and mark long */
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"skc", /* skip on C flip-flop equals 1 */
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"skz", /* skip on accumulator zero */
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"skbi", /* skip on BL equal to immediate */
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"skf1", /* skip on FF1 flip-flop equals 1 */
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"skf2", /* skip on FF2 flip-flop equals 1 */
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"rtn", /* return */
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"rtnsk", /* return and skip */
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"iol", /* input/output long */
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"dia", /* discrete input group A */
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"dib", /* discrete input group B */
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"doa", /* discrete output */
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"sag" /* special address generation */
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};
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static const UINT16 table[] = {
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t_LBL | t_I8c, /* 00 */
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t_TML | t_I4 | t_I8, /* 01 */
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t_TML | t_I4 | t_I8, /* 02 */
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t_TML | t_I4 | t_I8, /* 03 */
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t_LBUA, /* 04 */
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t_RTN, /* 05 */
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t_XS, /* 06 */
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t_RTNSK, /* 07 */
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t_ADCSK, /* 08 */
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t_ADSK, /* 09 */
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t_ADC, /* 0a */
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t_AD, /* 0b */
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t_EOR, /* 0c */
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t_AND, /* 0d */
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t_COMP, /* 0e */
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t_OR, /* 0f */
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t_LBMX, /* 10 */
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t_LABL, /* 11 */
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t_LAX, /* 12 */
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t_SAG, /* 13 */
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t_SKF2, /* 14 */
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t_SKC, /* 15 */
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t_SKF1, /* 16 */
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t_INCB, /* 17 */
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t_XBMX, /* 18 */
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t_XABL, /* 19 */
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t_XAX, /* 1a */
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t_LXA, /* 1b */
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t_IOL | t_I8, /* 1c */
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t_DOA, /* 1d */
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t_SKZ, /* 1e */
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t_DECB, /* 1f */
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t_SC, /* 20 */
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t_SF2, /* 21 */
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t_SF1, /* 22 */
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t_DIB, /* 23 */
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t_RC, /* 24 */
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t_RF2, /* 25 */
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t_RF1, /* 26 */
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t_DIA, /* 27 */
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t_EXD | t_I3c, /* 28 */
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t_EXD | t_I3c, /* 29 */
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t_EXD | t_I3c, /* 2a */
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t_EXD | t_I3c, /* 2b */
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t_EXD | t_I3c, /* 2c */
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t_EXD | t_I3c, /* 2d */
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t_EXD | t_I3c, /* 2e */
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t_EXD | t_I3c, /* 2f */
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t_LD | t_I3c, /* 30 */
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t_LD | t_I3c, /* 31 */
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t_LD | t_I3c, /* 32 */
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t_LD | t_I3c, /* 33 */
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t_LD | t_I3c, /* 34 */
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t_LD | t_I3c, /* 35 */
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t_LD | t_I3c, /* 36 */
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t_LD | t_I3c, /* 37 */
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t_EX | t_I3c, /* 38 */
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t_EX | t_I3c, /* 39 */
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t_EX | t_I3c, /* 3a */
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t_EX | t_I3c, /* 3b */
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t_EX | t_I3c, /* 3c */
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t_EX | t_I3c, /* 3d */
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t_EX | t_I3c, /* 3e */
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t_EX | t_I3c, /* 3f */
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t_SKBI | t_I4, /* 40 */
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t_SKBI | t_I4, /* 41 */
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t_SKBI | t_I4, /* 42 */
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t_SKBI | t_I4, /* 43 */
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t_SKBI | t_I4, /* 44 */
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t_SKBI | t_I4, /* 45 */
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t_SKBI | t_I4, /* 46 */
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t_SKBI | t_I4, /* 47 */
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t_SKBI | t_I4, /* 48 */
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t_SKBI | t_I4, /* 49 */
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t_SKBI | t_I4, /* 4a */
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t_SKBI | t_I4, /* 4b */
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t_SKBI | t_I4, /* 4c */
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t_SKBI | t_I4, /* 4d */
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t_SKBI | t_I4, /* 4e */
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t_SKBI | t_I4, /* 4f */
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t_TL | t_I4 | t_I8, /* 50 */
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t_TL | t_I4 | t_I8, /* 51 */
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t_TL | t_I4 | t_I8, /* 52 */
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t_TL | t_I4 | t_I8, /* 53 */
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t_TL | t_I4 | t_I8, /* 54 */
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t_TL | t_I4 | t_I8, /* 55 */
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t_TL | t_I4 | t_I8, /* 56 */
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t_TL | t_I4 | t_I8, /* 57 */
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t_TL | t_I4 | t_I8, /* 58 */
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t_TL | t_I4 | t_I8, /* 59 */
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t_TL | t_I4 | t_I8, /* 5a */
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t_TL | t_I4 | t_I8, /* 5b */
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t_TL | t_I4 | t_I8, /* 5c */
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t_TL | t_I4 | t_I8, /* 5d */
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t_TL | t_I4 | t_I8, /* 5e */
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t_TL | t_I4 | t_I8, /* 5f */
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t_ADI | t_I4c, /* 60 */
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t_ADI | t_I4c, /* 61 */
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t_ADI | t_I4c, /* 62 */
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t_ADI | t_I4c, /* 63 */
|
||||
t_ADI | t_I4c, /* 64 */
|
||||
t_DC, /* 65 */
|
||||
t_ADI | t_I4c, /* 66 */
|
||||
t_ADI | t_I4c, /* 67 */
|
||||
t_ADI | t_I4c, /* 68 */
|
||||
t_ADI | t_I4c, /* 69 */
|
||||
t_ADI | t_I4c, /* 6a */
|
||||
t_ADI | t_I4c, /* 6b */
|
||||
t_ADI | t_I4c, /* 6c */
|
||||
t_ADI | t_I4c, /* 6d */
|
||||
t_ADI | t_I4c, /* 6e */
|
||||
t_CYS, /* 6f */
|
||||
|
||||
t_LDI | t_I4c, /* 70 */
|
||||
t_LDI | t_I4c, /* 71 */
|
||||
t_LDI | t_I4c, /* 72 */
|
||||
t_LDI | t_I4c, /* 73 */
|
||||
t_LDI | t_I4c, /* 74 */
|
||||
t_LDI | t_I4c, /* 75 */
|
||||
t_LDI | t_I4c, /* 76 */
|
||||
t_LDI | t_I4c, /* 77 */
|
||||
t_LDI | t_I4c, /* 78 */
|
||||
t_LDI | t_I4c, /* 79 */
|
||||
t_LDI | t_I4c, /* 7a */
|
||||
t_LDI | t_I4c, /* 7b */
|
||||
t_LDI | t_I4c, /* 7c */
|
||||
t_LDI | t_I4c, /* 7d */
|
||||
t_LDI | t_I4c, /* 7e */
|
||||
t_LDI | t_I4c, /* 7f */
|
||||
|
||||
t_T | t_I6p, /* 80 */
|
||||
t_T | t_I6p, /* 81 */
|
||||
t_T | t_I6p, /* 82 */
|
||||
t_T | t_I6p, /* 83 */
|
||||
t_T | t_I6p, /* 84 */
|
||||
t_T | t_I6p, /* 85 */
|
||||
t_T | t_I6p, /* 86 */
|
||||
t_T | t_I6p, /* 87 */
|
||||
t_T | t_I6p, /* 88 */
|
||||
t_T | t_I6p, /* 89 */
|
||||
t_T | t_I6p, /* 8a */
|
||||
t_T | t_I6p, /* 8b */
|
||||
t_T | t_I6p, /* 8c */
|
||||
t_T | t_I6p, /* 8d */
|
||||
t_T | t_I6p, /* 8e */
|
||||
t_T | t_I6p, /* 8f */
|
||||
|
||||
t_T | t_I6p, /* 90 */
|
||||
t_T | t_I6p, /* 91 */
|
||||
t_T | t_I6p, /* 92 */
|
||||
t_T | t_I6p, /* 93 */
|
||||
t_T | t_I6p, /* 94 */
|
||||
t_T | t_I6p, /* 95 */
|
||||
t_T | t_I6p, /* 96 */
|
||||
t_T | t_I6p, /* 97 */
|
||||
t_T | t_I6p, /* 98 */
|
||||
t_T | t_I6p, /* 99 */
|
||||
t_T | t_I6p, /* 9a */
|
||||
t_T | t_I6p, /* 9b */
|
||||
t_T | t_I6p, /* 9c */
|
||||
t_T | t_I6p, /* 9d */
|
||||
t_T | t_I6p, /* 9e */
|
||||
t_T | t_I6p, /* 9f */
|
||||
|
||||
t_T | t_I6p, /* a0 */
|
||||
t_T | t_I6p, /* a1 */
|
||||
t_T | t_I6p, /* a2 */
|
||||
t_T | t_I6p, /* a3 */
|
||||
t_T | t_I6p, /* a4 */
|
||||
t_T | t_I6p, /* a5 */
|
||||
t_T | t_I6p, /* a6 */
|
||||
t_T | t_I6p, /* a7 */
|
||||
t_T | t_I6p, /* a8 */
|
||||
t_T | t_I6p, /* a9 */
|
||||
t_T | t_I6p, /* aa */
|
||||
t_T | t_I6p, /* ab */
|
||||
t_T | t_I6p, /* ac */
|
||||
t_T | t_I6p, /* ad */
|
||||
t_T | t_I6p, /* ae */
|
||||
t_T | t_I6p, /* af */
|
||||
|
||||
t_T | t_I6p, /* b0 */
|
||||
t_T | t_I6p, /* b1 */
|
||||
t_T | t_I6p, /* b2 */
|
||||
t_T | t_I6p, /* b3 */
|
||||
t_T | t_I6p, /* b4 */
|
||||
t_T | t_I6p, /* b5 */
|
||||
t_T | t_I6p, /* b6 */
|
||||
t_T | t_I6p, /* b7 */
|
||||
t_T | t_I6p, /* b8 */
|
||||
t_T | t_I6p, /* b9 */
|
||||
t_T | t_I6p, /* ba */
|
||||
t_T | t_I6p, /* bb */
|
||||
t_T | t_I6p, /* bc */
|
||||
t_T | t_I6p, /* bd */
|
||||
t_T | t_I6p, /* be */
|
||||
t_T | t_I6p, /* bf */
|
||||
|
||||
t_LB | t_I4p, /* c0 */
|
||||
t_LB | t_I4p, /* c1 */
|
||||
t_LB | t_I4p, /* c2 */
|
||||
t_LB | t_I4p, /* c3 */
|
||||
t_LB | t_I4p, /* c4 */
|
||||
t_LB | t_I4p, /* c5 */
|
||||
t_LB | t_I4p, /* c6 */
|
||||
t_LB | t_I4p, /* c7 */
|
||||
t_LB | t_I4p, /* c8 */
|
||||
t_LB | t_I4p, /* c9 */
|
||||
t_LB | t_I4p, /* ca */
|
||||
t_LB | t_I4p, /* cb */
|
||||
t_LB | t_I4p, /* cc */
|
||||
t_LB | t_I4p, /* cd */
|
||||
t_LB | t_I4p, /* ce */
|
||||
t_LB | t_I4p, /* cf */
|
||||
|
||||
t_TM | t_I6p, /* d0 */
|
||||
t_TM | t_I6p, /* d1 */
|
||||
t_TM | t_I6p, /* d2 */
|
||||
t_TM | t_I6p, /* d3 */
|
||||
t_TM | t_I6p, /* d4 */
|
||||
t_TM | t_I6p, /* d5 */
|
||||
t_TM | t_I6p, /* d6 */
|
||||
t_TM | t_I6p, /* d7 */
|
||||
t_TM | t_I6p, /* d8 */
|
||||
t_TM | t_I6p, /* d9 */
|
||||
t_TM | t_I6p, /* da */
|
||||
t_TM | t_I6p, /* db */
|
||||
t_TM | t_I6p, /* dc */
|
||||
t_TM | t_I6p, /* dd */
|
||||
t_TM | t_I6p, /* de */
|
||||
t_TM | t_I6p, /* df */
|
||||
|
||||
t_TM | t_I6p, /* e0 */
|
||||
t_TM | t_I6p, /* e1 */
|
||||
t_TM | t_I6p, /* e2 */
|
||||
t_TM | t_I6p, /* e3 */
|
||||
t_TM | t_I6p, /* e4 */
|
||||
t_TM | t_I6p, /* e5 */
|
||||
t_TM | t_I6p, /* e6 */
|
||||
t_TM | t_I6p, /* e7 */
|
||||
t_TM | t_I6p, /* e8 */
|
||||
t_TM | t_I6p, /* e9 */
|
||||
t_TM | t_I6p, /* ea */
|
||||
t_TM | t_I6p, /* eb */
|
||||
t_TM | t_I6p, /* ec */
|
||||
t_TM | t_I6p, /* ed */
|
||||
t_TM | t_I6p, /* ee */
|
||||
t_TM | t_I6p, /* ef */
|
||||
|
||||
t_TM | t_I6p, /* f0 */
|
||||
t_TM | t_I6p, /* f1 */
|
||||
t_TM | t_I6p, /* f2 */
|
||||
t_TM | t_I6p, /* f3 */
|
||||
t_TM | t_I6p, /* f4 */
|
||||
t_TM | t_I6p, /* f5 */
|
||||
t_TM | t_I6p, /* f6 */
|
||||
t_TM | t_I6p, /* f7 */
|
||||
t_TM | t_I6p, /* f8 */
|
||||
t_TM | t_I6p, /* f9 */
|
||||
t_TM | t_I6p, /* fa */
|
||||
t_TM | t_I6p, /* fb */
|
||||
t_TM | t_I6p, /* fc */
|
||||
t_TM | t_I6p, /* fd */
|
||||
t_TM | t_I6p, /* fe */
|
||||
t_TM | t_I6p, /* ff */
|
||||
};
|
||||
|
||||
CPU_DISASSEMBLE( pps4 )
|
||||
{
|
||||
UINT32 flags = 0;
|
||||
unsigned PC = pc;
|
||||
UINT8 op;
|
||||
switch (op = OP(pc++))
|
||||
{
|
||||
// Arithmetic instructions
|
||||
case 0x0b: sprintf (buffer,"ad"); break;
|
||||
case 0x0a: sprintf (buffer,"adc"); break;
|
||||
case 0x09: sprintf (buffer,"adsk"); break;
|
||||
case 0x08: sprintf (buffer,"adcsk"); break;
|
||||
case 0x60: case 0x61: case 0x62: case 0x63:
|
||||
case 0x64: case 0x66: case 0x67: case 0x68:
|
||||
case 0x69: case 0x6a: case 0x6b: case 0x6c:
|
||||
case 0x6d: case 0x6e:
|
||||
sprintf (buffer,"adi %01x",(op & 0x0f)); break;
|
||||
case 0x65: sprintf (buffer,"dc"); break;
|
||||
// Logical instructions
|
||||
case 0x0d: sprintf (buffer,"and"); break;
|
||||
case 0x0f: sprintf (buffer,"or"); break;
|
||||
case 0x0c: sprintf (buffer,"eor"); break;
|
||||
case 0x0e: sprintf (buffer,"comp"); break;
|
||||
// Data transfer instructions
|
||||
case 0x20: sprintf (buffer,"sc"); break;
|
||||
case 0x24: sprintf (buffer,"rc"); break;
|
||||
case 0x22: sprintf (buffer,"sf1"); break;
|
||||
case 0x26: sprintf (buffer,"rf1"); break;
|
||||
case 0x21: sprintf (buffer,"sf2"); break;
|
||||
case 0x25: sprintf (buffer,"rf2"); break;
|
||||
case 0x30: case 0x31: case 0x32: case 0x33:
|
||||
case 0x34: case 0x35: case 0x36: case 0x37:
|
||||
sprintf (buffer,"ld %01x",(op & 0x07)); break;
|
||||
case 0x38: case 0x39: case 0x3a: case 0x3b:
|
||||
case 0x3c: case 0x3d: case 0x3e: case 0x3f:
|
||||
sprintf (buffer,"ex %01x",(op & 0x07)); break;
|
||||
case 0x28: case 0x29: case 0x2a: case 0x2b:
|
||||
case 0x2c: case 0x2d: case 0x2e: case 0x2f:
|
||||
sprintf (buffer,"exd %01x",(op & 0x07)); break;
|
||||
case 0x70: case 0x71: case 0x72: case 0x73:
|
||||
case 0x74: case 0x75: case 0x76: case 0x77:
|
||||
sprintf (buffer,"ldi %01x",(op & 0x0f)); break;
|
||||
case 0x12: sprintf (buffer,"lax"); break;
|
||||
case 0x1b: sprintf (buffer,"lxa"); break;
|
||||
case 0x11: sprintf (buffer,"labl"); break;
|
||||
case 0x10: sprintf (buffer,"lbmx"); break;
|
||||
case 0x04: sprintf (buffer,"lbua"); break;
|
||||
case 0x19: sprintf (buffer,"xabl"); break;
|
||||
case 0x18: sprintf (buffer,"xbmx"); break;
|
||||
case 0x1a: sprintf (buffer,"xax"); break;
|
||||
case 0x06: sprintf (buffer,"xs"); break;
|
||||
case 0x6f: sprintf (buffer,"cys"); break;
|
||||
case 0xc0: case 0xc1: case 0xc2: case 0xc3:
|
||||
case 0xc4: case 0xc5: case 0xc6: case 0xc7:
|
||||
case 0xc8: case 0xc9: case 0xca: case 0xcb:
|
||||
case 0xcc: case 0xcd: case 0xce: case 0xcf:
|
||||
sprintf (buffer,"lb %02x",ARG(pc)); pc++; break;
|
||||
case 0x00: sprintf (buffer,"lbl %02x",ARG(pc)); pc++; break;
|
||||
case 0x17: sprintf (buffer,"incb"); break;
|
||||
case 0x1f: sprintf (buffer,"decb"); break;
|
||||
// Control transfer instructions
|
||||
case 0x80: case 0x81: case 0x82: case 0x83:
|
||||
case 0x84: case 0x85: case 0x86: case 0x87:
|
||||
case 0x88: case 0x89: case 0x8a: case 0x8b:
|
||||
case 0x8c: case 0x8d: case 0x8e: case 0x8f:
|
||||
case 0x90: case 0x91: case 0x92: case 0x93:
|
||||
case 0x94: case 0x95: case 0x96: case 0x97:
|
||||
case 0x98: case 0x99: case 0x9a: case 0x9b:
|
||||
case 0x9c: case 0x9d: case 0x9e: case 0x9f:
|
||||
case 0xa0: case 0xa1: case 0xa2: case 0xa3:
|
||||
case 0xa4: case 0xa5: case 0xa6: case 0xa7:
|
||||
case 0xa8: case 0xa9: case 0xaa: case 0xab:
|
||||
case 0xac: case 0xad: case 0xae: case 0xaf:
|
||||
case 0xb0: case 0xb1: case 0xb2: case 0xb3:
|
||||
case 0xb4: case 0xb5: case 0xb6: case 0xb7:
|
||||
case 0xb8: case 0xb9: case 0xba: case 0xbb:
|
||||
case 0xbc: case 0xbd: case 0xbe: case 0xbf:
|
||||
sprintf (buffer,"t %02x",(op & 0x3f)); break;
|
||||
case 0xd0: case 0xd1: case 0xd2: case 0xd3:
|
||||
case 0xd4: case 0xd5: case 0xd6: case 0xd7:
|
||||
case 0xd8: case 0xd9: case 0xda: case 0xdb:
|
||||
case 0xdc: case 0xdd: case 0xde: case 0xdf:
|
||||
case 0xe0: case 0xe1: case 0xe2: case 0xe3:
|
||||
case 0xe4: case 0xe5: case 0xe6: case 0xe7:
|
||||
case 0xe8: case 0xe9: case 0xea: case 0xeb:
|
||||
case 0xec: case 0xed: case 0xee: case 0xef:
|
||||
case 0xf0: case 0xf1: case 0xf2: case 0xf3:
|
||||
case 0xf4: case 0xf5: case 0xf6: case 0xf7:
|
||||
case 0xf8: case 0xf9: case 0xfa: case 0xfb:
|
||||
case 0xfc: case 0xfd: case 0xfe: case 0xff:
|
||||
sprintf (buffer,"tm %02x %02x",(op & 0x3f),ARG(pc)); pc++; break;
|
||||
case 0x50: case 0x51: case 0x52: case 0x53:
|
||||
case 0x54: case 0x55: case 0x56: case 0x57:
|
||||
case 0x58: case 0x59: case 0x5a: case 0x5b:
|
||||
case 0x5c: case 0x5d: case 0x5e: case 0x5f:
|
||||
sprintf (buffer,"tl %01x %02x",(op & 0x0f),ARG(pc)); pc++; break;
|
||||
case 0x01: case 0x02: case 0x03:
|
||||
sprintf (buffer,"tml %02x",ARG(pc)); pc++; break;
|
||||
case 0x15: sprintf (buffer,"skc"); break;
|
||||
case 0x1e: sprintf (buffer,"skz"); break;
|
||||
case 0x40: case 0x41: case 0x42: case 0x43:
|
||||
case 0x44: case 0x45: case 0x46: case 0x47:
|
||||
case 0x48: case 0x49: case 0x4a: case 0x4b:
|
||||
case 0x4c: case 0x4d: case 0x4e: case 0x4f:
|
||||
sprintf (buffer,"skbi %01x",(op & 0x0f)); break;
|
||||
case 0x16: sprintf (buffer,"skf1"); break;
|
||||
case 0x14: sprintf (buffer,"skf2"); break;
|
||||
case 0x05: sprintf (buffer,"rtn"); break;
|
||||
case 0x07: sprintf (buffer,"rtnsk"); break;
|
||||
// Input/Output instructions
|
||||
case 0x1c: sprintf (buffer,"iol %02x",ARG(pc)); pc++; break;
|
||||
case 0x27: sprintf (buffer,"dia"); break;
|
||||
case 0x23: sprintf (buffer,"dib"); break;
|
||||
case 0x1d: sprintf (buffer,"doa"); break;
|
||||
// Special instructions
|
||||
case 0x13: sprintf (buffer,"sag"); break;
|
||||
}
|
||||
UINT32 flags = 0;
|
||||
unsigned PC = pc;
|
||||
UINT8 op = OP(pc++);
|
||||
UINT32 tok = table[op];
|
||||
char *dst = 0;
|
||||
|
||||
return (pc - PC) | flags | DASMFLAG_SUPPORTED;
|
||||
if (0 == (tok & t_MASK))
|
||||
sprintf(buffer, "%s", token_str[tok & t_MASK]);
|
||||
else
|
||||
dst = buffer + sprintf(buffer, "%-7s", token_str[tok & t_MASK]);
|
||||
|
||||
if (tok & t_I3c) {
|
||||
// 3 bit immediate, complemented
|
||||
UINT8 i = ~op & 7;
|
||||
dst += sprintf(dst, "%x", i);
|
||||
}
|
||||
|
||||
if (tok & t_I4) {
|
||||
// 4 bit immediate
|
||||
UINT8 i = op & 15;
|
||||
dst += sprintf(dst, "%x", i);
|
||||
}
|
||||
|
||||
if (tok & t_I4c) {
|
||||
// 4 bit immediate, complemented
|
||||
UINT8 i = ~op & 15;
|
||||
dst += sprintf(dst, "%x", i);
|
||||
}
|
||||
|
||||
if (tok & t_I4p) {
|
||||
// 4 bit immediate offset into page 3
|
||||
UINT8 i = op & 15;
|
||||
dst += sprintf(dst, "[%x]", 0x0c0 | i);
|
||||
}
|
||||
|
||||
if (tok & t_I6p) {
|
||||
// 6 bit immediate offset into current page
|
||||
UINT8 i = op & 63;
|
||||
dst += sprintf(dst, "%x", (PC & ~63) | i);
|
||||
}
|
||||
|
||||
if (tok & t_I8) {
|
||||
// 8 bit immediate I/O port address
|
||||
UINT8 arg = ARG(pc++);
|
||||
dst += sprintf(dst, "%02x", arg);
|
||||
}
|
||||
|
||||
if (tok & t_I8c) {
|
||||
// 8 bit immediate offset into page
|
||||
UINT16 arg = ~ARG(pc++) & 255;
|
||||
dst += sprintf(dst, "%03x", arg);
|
||||
}
|
||||
|
||||
if (0x05 == op || 0x07 == op) // RTN or RTNSK
|
||||
flags |= DASMFLAG_STEP_OUT;
|
||||
|
||||
return (pc - PC) | flags | DASMFLAG_SUPPORTED;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user