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https://github.com/holub/mame
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Merge pull request #989 from MooglyGuy/master
Rewrite SPARC emulation based on detailed descriptions from SPARC manual [Ryan Holtz]
This commit is contained in:
Vas Crabb
GitHub
commit
b68b262e1b
File diff suppressed because it is too large
Load Diff
@ -16,7 +16,7 @@
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#define SPARC_INSTRUCTION_ACCESS_EXCEPTION 1
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#define SPARC_ILLEGAL_INSTRUCTION 2
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#define SPARC_PRIVILEGED_INSTRUCTION 3
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#define SPARC_FLOATING_POINT_DISABLED 4
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#define SPARC_FP_DISABLED 4
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#define SPARC_WINDOW_OVERFLOW 5
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#define SPARC_WINDOW_UNDERFLOW 6
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#define SPARC_MEM_ADDRESS_NOT_ALIGNED 7
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@ -40,6 +40,7 @@
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#define SPARC_INT15 31
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#define SPARC_TRAP_INSTRUCTION 128
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#define SPARC_FPU_SEQUENCE_ERROR
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// TODO: when there are more SPARC CPUs, move setter to a base class
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#define MCFG_SPARC_ADD_ASI_DESC(desc) \
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mb86901_device::add_asi_desc(*device, desc);
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@ -85,35 +86,56 @@ public:
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protected:
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template<typename T> void add_asi_desc(const T &desc) { m_dasm.add_asi_desc(desc); }
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bool invoke_queued_traps();
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bool check_main_traps(UINT32 op, bool privileged, UINT32 alignment, UINT8 registeralign, bool noimmediate);
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void update_gpr_pointers();
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void save_restore_update_cwp(UINT32 op, UINT8 new_cwp);
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bool execute_group2(UINT32 op);
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void execute_add(UINT32 op);
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void execute_taddcc(UINT32 op);
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void execute_sub(UINT32 op);
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void execute_tsubcc(UINT32 op);
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void execute_logical(UINT32 op);
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void execute_shift(UINT32 op);
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void execute_mulscc(UINT32 op);
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void execute_rdsr(UINT32 op);
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void execute_wrsr(UINT32 op);
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void execute_rett(UINT32 op);
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void execute_saverestore(UINT32 op);
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void execute_jmpl(UINT32 op);
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void execute_group2(UINT32 op);
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void execute_load(UINT32 op);
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void execute_store(UINT32 op);
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void execute_ldstub(UINT32 op);
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void execute_group3(UINT32 op);
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bool execute_bicc(UINT32 op);
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bool execute_ticc(UINT32 op);
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bool evaluate_condition(UINT32 op);
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void execute_bicc(UINT32 op);
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void execute_ticc(UINT32 op);
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void select_trap();
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void execute_trap();
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void complete_instruction_execution(UINT32 op);
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void dispatch_instruction(UINT32 op);
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void complete_fp_execution(UINT32 /*op*/);
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void execute_step();
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void reset_step();
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void error_step();
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// address spaces
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const address_space_config m_program_config;
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// memory access
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UINT32 read_byte(UINT8 asi, UINT32 address);
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INT32 read_signed_byte(UINT8 asi, UINT32 address);
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UINT32 read_half(UINT8 asi, UINT32 address);
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INT32 read_signed_half(UINT8 asi, UINT32 address);
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UINT32 read_word(UINT8 asi, UINT32 address);
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UINT64 read_doubleword(UINT8 asi, UINT32 address);
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void write_byte(UINT8 asi, UINT32 address, UINT8 data);
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void write_half(UINT8 asi, UINT32 address, UINT16 data);
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void write_word(UINT8 asi, UINT32 address, UINT32 data);
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void write_doubleword(UINT8 asi, UINT32 address, UINT64 data);
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UINT32 read_sized_word(UINT8 asi, UINT32 address, int size);
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void write_sized_word(UINT8 asi, UINT32 address, UINT32 data, int size);
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// general-purpose registers
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UINT32 m_r[120];
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// FPU registers
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UINT32 m_fpr[32];
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UINT32 m_fsr;
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UINT8 m_ftt;
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// control/status registers
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UINT32 m_pc;
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UINT32 m_npc;
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@ -122,6 +144,45 @@ protected:
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UINT32 m_tbr;
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UINT32 m_y;
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bool m_bp_reset_in;
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UINT8 m_bp_irl;
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bool m_bp_fpu_present;
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bool m_bp_cp_present;
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bool m_pb_error;
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bool m_pb_block_ldst_byte;
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bool m_pb_block_ldst_word;
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// trap and error registers
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bool m_trap;
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UINT8 m_tt;
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UINT8 m_ticc_trap_type;
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UINT8 m_interrupt_level;
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bool m_privileged_instruction;
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bool m_illegal_instruction;
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bool m_mem_address_not_aligned;
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bool m_fp_disabled;
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bool m_fp_exception;
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bool m_cp_disabled; // SPARCv8
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bool m_cp_exception; // SPARCv8
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bool m_unimplemented_FLUSH; // SPARCv8
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bool m_r_register_access_error; // SPARCv8
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bool m_instruction_access_error; // SPARCv8
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bool m_instruction_access_exception;
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bool m_data_access_error; // SPARCv8
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bool m_data_store_error; // SPARCv8
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bool m_data_access_exception;
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bool m_division_by_zero; // SPARCv8
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bool m_trap_instruction;
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bool m_window_underflow;
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bool m_window_overflow;
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bool m_tag_overflow;
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bool m_reset_mode;
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bool m_reset_trap;
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bool m_execute_mode;
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bool m_error_mode;
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UINT8 m_fpu_sequence_err;
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UINT8 m_cp_sequence_err;
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// fields separated out from PSR (Processor State Register)
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UINT8 m_impl; // implementation (always 0 in MB86901)
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UINT8 m_ver; // version (always 0 in MB86901)
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@ -134,19 +195,20 @@ protected:
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bool m_et; // enable traps
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UINT8 m_cwp; // current window pointer
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bool m_alu_op3_assigned[64];
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bool m_ldst_op3_assigned[64];
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// register windowing helpers
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UINT32* m_regs[32];
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// addressing helpers
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UINT8 m_insn_asi;
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UINT8 m_data_asi;
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UINT8 m_asi;
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// other internal states
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UINT32 m_trap_priorities[256];
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UINT32 m_queued_tt;
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UINT32 m_queued_priority;
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bool m_privileged_asr[32];
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bool m_illegal_instruction_asr[32];
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bool m_mae;
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bool m_annul;
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bool m_hold_bus;
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int m_icount;
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@ -158,7 +220,7 @@ protected:
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address_space *m_program;
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// processor configuration
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static const int WINDOW_COUNT;
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static const int NWINDOWS;
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};
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// device type definition
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@ -12,8 +12,6 @@
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#ifndef __MB86901_DEFS_H__
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#define __MB86901_DEFS_H__
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#define GET_OPCODE 0; { m_asi = m_insn_asi; op = m_program->read_dword(m_pc); }
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#define PSR_CWP_MASK 0x0000001f
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#define PSR_ET_SHIFT 5
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#define PSR_ET_MASK 0x00000020
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@ -43,21 +41,25 @@
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#define PSR_ZERO_MASK (PSR_IMPL_MASK | PSR_VER_MASK | PSR_RES_MASK)
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#define ICC_N_SET (m_psr & PSR_N_MASK)
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#define ICC_N (ICC_N_SET ? 1 : 0)
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#define ICC_N_CLEAR (!ICC_N_SET)
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#define SET_ICC_N_FLAG do { m_psr |= PSR_N_MASK; } while(0);
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#define CLEAR_ICC_N_FLAG do { m_psr &= ~PSR_N_MASK; } while(0);
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#define ICC_Z_SET (m_psr & PSR_Z_MASK)
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#define ICC_Z (ICC_Z_SET ? 1 : 0)
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#define ICC_Z_CLEAR (!ICC_Z_SET)
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#define SET_ICC_Z_FLAG do { m_psr |= PSR_Z_MASK; } while(0);
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#define CLEAR_ICC_Z_FLAG do { m_psr &= ~PSR_Z_MASK; } while(0);
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#define ICC_V_SET (m_psr & PSR_V_MASK)
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#define ICC_V_CLEAR (!ICC_B_SET)
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#define ICC_V (ICC_V_SET ? 1 : 0)
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#define ICC_V_CLEAR (!ICC_V_SET)
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#define SET_ICC_V_FLAG do { m_psr |= PSR_V_MASK; } while(0);
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#define CLEAR_ICC_V_FLAG do { m_psr &= ~PSR_V_MASK; } while(0);
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#define ICC_C_SET (m_psr & PSR_C_MASK)
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#define ICC_C (ICC_C_SET ? 1 : 0)
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#define ICC_C_CLEAR (!ICC_C_SET)
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#define SET_ICC_C_FLAG do { m_psr |= PSR_C_MASK; } while(0);
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#define CLEAR_ICC_C_FLAG do { m_psr &= ~PSR_C_MASK; } while(0);
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@ -66,18 +68,23 @@
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#define TEST_ICC_NZ(x) do { m_psr &= ~PSR_ICC_MASK; m_psr |= (x & 0x80000000) ? PSR_N_MASK : 0; m_psr |= (x == 0) ? PSR_Z_MASK : 0; } while (0);
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#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; m_insn_asi = m_s ? 9 : 8; m_data_asi = m_s ? 11 : 10; } while(0);
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#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; m_insn_asi = m_s ? 9 : 8; m_data_asi = m_s ? 11 : 10; } while(0);
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#define MAKE_PSR do { m_psr = (m_impl << PSR_IMPL_SHIFT) | (m_ver << PSR_VER_SHIFT) | (m_icc << PSR_ICC_SHIFT) | (m_ec ? PSR_EC_MASK : 0) | (m_ef ? PSR_EF_MASK : 0) | (m_pil << PSR_PIL_SHIFT) | (m_s ? PSR_S_MASK : 0) | (m_ps ? PSR_PS_MASK : 0) | (m_et ? PSR_ET_MASK : 0) | m_cwp; } while(0);
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#define BREAK_PSR do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; m_ec = m_psr & PSR_EC_MASK; m_ef = m_psr & PSR_EF_MASK; m_pil = (m_psr & PSR_PIL_MASK) >> PSR_PIL_SHIFT; m_s = m_psr & PSR_S_MASK; m_ps = m_psr & PSR_PS_MASK; m_et = m_psr & PSR_ET_MASK; m_cwp = m_psr & PSR_CWP_MASK; } while(0);
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#define MAKE_ICC do { m_icc = (m_psr & PSR_ICC_MASK) >> PSR_ICC_SHIFT; } while(0);
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#define CWP m_cwp
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#define S m_s
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#define PS m_ps
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#define IS_SUPERVISOR (m_psr & PSR_S_MASK)
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#define IS_USER (!IS_SUPERVISOR)
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#define TRAPS_ENABLED (m_psr & PSR_ET_MASK)
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#define TRAPS_DISABLED (!TRAPS_ENABLED)
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#define FPU_ENABLED (m_psr & PSR_EF_MASK)
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#define FPU_DISABLED (!FPU_ENABLED)
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#define PSR m_psr
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#define WIM m_wim
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#define TBR m_tbr
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#define OP (op >> 30) // gangnam style
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#define OP2 ((op >> 22) & 7)
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@ -121,11 +128,15 @@
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#define RS1 ((op >> 14) & 31)
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#define RS2 (op & 31)
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#define REG(x) *m_regs[x]
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#define FREG(x) m_fpr[(x)]
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#define FDREG m_fpr[RD]
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#define FSR m_fsr
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#define REG(x) *m_regs[(x)]
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#define RDREG *m_regs[RD]
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#define RS1REG *m_regs[RS1]
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#define RS2REG *m_regs[RS2]
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#define SET_RDREG(x) if(RD) { RDREG = x; }
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#define SET_RDREG(x) if(RD) { RDREG = (x); }
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#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG))
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#define PC m_pc
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@ -134,8 +145,180 @@
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#define Y m_y
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#define ET m_et
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#define EF m_ef
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#define EC m_ec
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#define PIL m_pil
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#define MAE m_mae
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#define HOLD_BUS m_hold_bus
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#define BIT31(x) ((x) & 0x80000000)
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#define UPDATE_PC true
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#define PC_UPDATED false
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#define OP_TYPE0 0
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#define OP_CALL 1
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#define OP_ALU 2
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#define OP_LDST 3
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#define OP2_UNIMP 0
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#define OP2_BICC 2
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#define OP2_SETHI 4
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#define OP2_FBFCC 6
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#define OP2_CBCCC 7
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#define OP3_ADD 0
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#define OP3_AND 1
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#define OP3_OR 2
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#define OP3_XOR 3
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#define OP3_SUB 4
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#define OP3_ANDN 5
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#define OP3_ORN 6
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#define OP3_XNOR 7
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#define OP3_ADDX 8
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#define OP3_UMUL 10
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#define OP3_SMUL 11
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#define OP3_SUBX 12
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#define OP3_UDIV 14
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#define OP3_SDIV 15
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#define OP3_ADDCC 16
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#define OP3_ANDCC 17
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#define OP3_ORCC 18
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#define OP3_XORCC 19
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#define OP3_SUBCC 20
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#define OP3_ANDNCC 21
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#define OP3_ORNCC 22
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#define OP3_XNORCC 23
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#define OP3_ADDXCC 24
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#define OP3_UMULCC 26
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#define OP3_SMULCC 27
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#define OP3_SUBXCC 28
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#define OP3_UDIVCC 30
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#define OP3_SDIVCC 31
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#define OP3_TADDCC 32
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#define OP3_TSUBCC 33
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#define OP3_TADDCCTV 34
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#define OP3_TSUBCCTV 35
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#define OP3_MULSCC 36
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#define OP3_SLL 37
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#define OP3_SRL 38
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#define OP3_SRA 39
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#define OP3_RDASR 40
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#define OP3_RDPSR 41
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#define OP3_RDWIM 42
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#define OP3_RDTBR 43
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#define OP3_WRASR 48
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#define OP3_WRPSR 49
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#define OP3_WRWIM 50
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#define OP3_WRTBR 51
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#define OP3_FPOP1 52
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#define OP3_FPOP2 53
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#define OP3_JMPL 56
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#define OP3_RETT 57
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#define OP3_TICC 58
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#define OP3_SAVE 60
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#define OP3_RESTORE 61
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#define OP3_LD 0
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#define OP3_LDUB 1
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#define OP3_LDUH 2
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#define OP3_LDD 3
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#define OP3_ST 4
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#define OP3_STB 5
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#define OP3_STH 6
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#define OP3_STD 7
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#define OP3_LDSB 9
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#define OP3_LDSH 10
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#define OP3_LDSTUB 13
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#define OP3_SWAP 15
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#define OP3_LDA 16
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#define OP3_LDUBA 17
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#define OP3_LDUHA 18
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#define OP3_LDDA 19
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#define OP3_STA 20
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#define OP3_STBA 21
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#define OP3_STHA 22
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#define OP3_STDA 23
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#define OP3_LDSBA 25
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#define OP3_LDSHA 26
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#define OP3_LDSTUBA 29
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#define OP3_SWAPA 31
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#define OP3_LDFPR 32
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#define OP3_LDFSR 33
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#define OP3_LDDFPR 35
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#define OP3_STFPR 36
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#define OP3_STFSR 37
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#define OP3_STDFQ 38
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#define OP3_STDFPR 39
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#define OP3_LDCPR 40
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#define OP3_LDCSR 41
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#define OP3_LDDCPR 43
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#define OP3_STCPR 44
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#define OP3_STCSR 45
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#define OP3_STDCQ 46
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#define OP3_STDCPR 47
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#define OP3_CPOP1 54
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#define OP3_CPOP2 55
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#define COND_BN 0
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#define COND_BE 1
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#define COND_BLE 2
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#define COND_BL 3
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#define COND_BLEU 4
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#define COND_BCS 5
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#define COND_BNEG 6
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#define COND_BVS 7
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#define COND_BA 8
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#define COND_BNE 9
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#define COND_BG 10
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#define COND_BGE 11
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#define COND_BGU 12
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#define COND_BCC 13
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#define COND_BPOS 14
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#define COND_BVC 15
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#define LDD (OP3 == OP3_LDD)
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#define LD (OP3 == OP3_LD)
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#define LDSH (OP3 == OP3_LDSH)
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#define LDUH (OP3 == OP3_LDUH)
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#define LDSB (OP3 == OP3_LDSB)
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#define LDUB (OP3 == OP3_LDUB)
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#define LDDF (OP3 == OP3_LDDFPR)
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#define LDF (OP3 == OP3_LDFPR)
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#define LDFSR (OP3 == OP3_LDFSR)
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#define LDDC (OP3 == OP3_LDDCPR)
|
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#define LDC (OP3 == OP3_LDCPR)
|
||||
#define LDCSR (OP3 == OP3_LDCSR)
|
||||
#define LDDA (OP3 == OP3_LDDA)
|
||||
#define LDA (OP3 == OP3_LDA)
|
||||
#define LDSHA (OP3 == OP3_LDSHA)
|
||||
#define LDUHA (OP3 == OP3_LDUHA)
|
||||
#define LDSBA (OP3 == OP3_LDSBA)
|
||||
#define LDUBA (OP3 == OP3_LDUBA)
|
||||
|
||||
#define STD (OP3 == OP3_STD)
|
||||
#define ST (OP3 == OP3_ST)
|
||||
#define STH (OP3 == OP3_STH)
|
||||
#define STB (OP3 == OP3_STB)
|
||||
#define STDA (OP3 == OP3_STDA)
|
||||
#define STA (OP3 == OP3_STA)
|
||||
#define STHA (OP3 == OP3_STHA)
|
||||
#define STBA (OP3 == OP3_STBA)
|
||||
#define STF (OP3 == OP3_STFPR)
|
||||
#define STFSR (OP3 == OP3_STFSR)
|
||||
#define STDFQ (OP3 == OP3_STDFQ)
|
||||
#define STDF (OP3 == OP3_STDFPR)
|
||||
#define STC (OP3 == OP3_STCPR)
|
||||
#define STCSR (OP3 == OP3_STCSR)
|
||||
#define STDCQ (OP3 == OP3_STDCQ)
|
||||
#define STDC (OP3 == OP3_STDCPR)
|
||||
|
||||
#define JMPL (OP3 == OP3_JMPL)
|
||||
#define TICC (OP3 == OP3_TICC)
|
||||
#define RETT (OP3 == OP3_RETT)
|
||||
|
||||
#define LDSTUB (OP3 == OP3_LDSTUB)
|
||||
#define LDSTUBA (OP3 == OP3_LDSTUBA)
|
||||
|
||||
#endif // __MB86901_DEFS_H__
|
||||
Loading…
Reference in New Issue
Block a user