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timer irq "cpustate->m37710_regs[m37710_irq_levels[curirq]] |= 0x08;" is unneeded (it was 0x04 but that was a plain hack)

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m37710i_update_irqs:
- FLAG_I check at the start prevented NMIs (even tho NMIs aren't implemented yet, not counting software interrupts)
- "indicate we're servicing it now" is unnecessary

m37710i_interrupt_hardware: junk/leftover

opcodes:
- software int, pull all, push all: forgot to put ipl(statusreg hi) on stack
- PLP, RTI, pull all: FLAG_I or ipl may have changed, so do an m37710i_update_irqs
This commit is contained in:
Michaël Banaan Ananas 2011-09-05 11:56:02 +00:00
parent c0db0605af
commit b7345fe4fc
2 changed files with 24 additions and 50 deletions
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39
src/emu/cpu/m37710/m37710.c
View File

@ -220,8 +220,8 @@ static const char *const m37710_rnames[128] =
"Timer B2 mode", "Timer B2 mode",
"Processor mode", "Processor mode",
"", "",
"Watchdog reset", "Watchdog reset", // 0x60
"Watchdog frequency", // 0x60 "Watchdog frequency", // 0x61
"", "",
"", "",
"", "",
@ -268,7 +268,6 @@ static TIMER_CALLBACK( m37710_timer_cb )
cpustate->timers[which]->adjust(cpustate->reload[which], param); cpustate->timers[which]->adjust(cpustate->reload[which], param);
cpustate->m37710_regs[m37710_irq_levels[curirq]] |= 0x08;
m37710_set_irq_line(cpustate, curirq, PULSE_LINE); m37710_set_irq_line(cpustate, curirq, PULSE_LINE);
device_triggerint(cpustate->device); device_triggerint(cpustate->device);
} }
@ -665,15 +664,8 @@ INLINE uint m37710i_get_reg_p(m37710i_cpu_struct *cpustate)
void m37710i_update_irqs(m37710i_cpu_struct *cpustate) void m37710i_update_irqs(m37710i_cpu_struct *cpustate)
{ {
int curirq, pending = LINE_IRQ; int curirq, pending = LINE_IRQ;
int wantedIRQ, curpri; int wantedIRQ = -1;
int curpri = -1;
if (FLAG_I)
{
return;
}
curpri = -1;
wantedIRQ = -1;
for (curirq = M37710_LINE_MAX - 1; curirq >= 0; curirq--) for (curirq = M37710_LINE_MAX - 1; curirq >= 0; curirq--)
{ {
@ -682,17 +674,14 @@ void m37710i_update_irqs(m37710i_cpu_struct *cpustate)
// this IRQ is set // this IRQ is set
if (m37710_irq_levels[curirq]) if (m37710_irq_levels[curirq])
{ {
// logerror("line %d set, level %x curpri %x IPL %x\n", curirq, cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7, curpri, cpustate->ipl); int thispri = cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7;
// it's maskable, check if the level works // logerror("line %d set, level %x curpri %x IPL %x\n", curirq, thispri, curpri, cpustate->ipl);
if ((cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7) > curpri) // it's maskable, check if the level works, also make sure it's acceptable for the current CPU level
if (!FLAG_I && thispri > curpri && thispri > cpustate->ipl)
{ {
// also make sure it's acceptable for the current CPU level // mark us as the best candidate
if ((cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7) > cpustate->ipl) wantedIRQ = curirq;
{ curpri = thispri;
// mark us as the best candidate
wantedIRQ = curirq;
curpri = cpustate->m37710_regs[m37710_irq_levels[curirq]] & 7;
}
} }
} }
else else
@ -712,12 +701,6 @@ void m37710i_update_irqs(m37710i_cpu_struct *cpustate)
// make sure we're running to service the interrupt // make sure we're running to service the interrupt
CPU_STOPPED &= ~STOP_LEVEL_WAI; CPU_STOPPED &= ~STOP_LEVEL_WAI;
// indicate we're servicing it now
if (m37710_irq_levels[wantedIRQ])
{
cpustate->m37710_regs[m37710_irq_levels[wantedIRQ]] &= ~8;
}
// auto-clear if it's an internal line // auto-clear if it's an internal line
if (wantedIRQ <= 12) if (wantedIRQ <= 12)
{ {

35
src/emu/cpu/m37710/m37710op.h
View File

@ -289,24 +289,12 @@ INLINE void m37710i_set_reg_ipl(m37710i_cpu_struct *cpustate, uint value)
/* =============================== INTERRUPTS ============================= */ /* =============================== INTERRUPTS ============================= */
/* ======================================================================== */ /* ======================================================================== */
INLINE void m37710i_interrupt_hardware(m37710i_cpu_struct *cpustate, uint vector)
{
CLK(8);
m37710i_push_8(cpustate, REG_PB>>16);
m37710i_push_16(cpustate, REG_PC);
m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate));
FLAG_D = DFLAG_CLEAR;
m37710i_set_flag_i(cpustate, IFLAG_SET);
REG_PB = 0;
m37710i_jump_16(cpustate, m37710i_read_16_normal(cpustate, vector));
if(INT_ACK) INT_ACK(cpustate->device, 0);
}
INLINE void m37710i_interrupt_software(m37710i_cpu_struct *cpustate, uint vector) INLINE void m37710i_interrupt_software(m37710i_cpu_struct *cpustate, uint vector)
{ {
CLK(8); CLK(8);
m37710i_push_8(cpustate, REG_PB>>16); m37710i_push_8(cpustate, REG_PB>>16);
m37710i_push_16(cpustate, REG_PC); m37710i_push_16(cpustate, REG_PC);
m37710i_push_8(cpustate, cpustate->ipl);
m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate));
FLAG_D = DFLAG_CLEAR; FLAG_D = DFLAG_CLEAR;
m37710i_set_flag_i(cpustate, IFLAG_SET); m37710i_set_flag_i(cpustate, IFLAG_SET);
@ -533,7 +521,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
if (SRC&0x40) \ if (SRC&0x40) \
{ m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \ { m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \
if (SRC&0x80) \ if (SRC&0x80) \
{ m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); } { m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); }
#else // FLAG_SET_X #else // FLAG_SET_X
#define OP_PSH(MODE) \ #define OP_PSH(MODE) \
SRC = OPER_8_##MODE(cpustate); \ SRC = OPER_8_##MODE(cpustate); \
@ -553,7 +541,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
if (SRC&0x40) \ if (SRC&0x40) \
{ m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \ { m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \
if (SRC&0x80) \ if (SRC&0x80) \
{ m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); } { m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); }
#endif // FLAG_SET_X #endif // FLAG_SET_X
#else // FLAG_SET_M #else // FLAG_SET_M
#if FLAG_SET_X #if FLAG_SET_X
@ -575,7 +563,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
if (SRC&0x40) \ if (SRC&0x40) \
{ m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \ { m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \
if (SRC&0x80) \ if (SRC&0x80) \
{ m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); } { m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); }
#else // FLAG_SET_X #else // FLAG_SET_X
#define OP_PSH(MODE) \ #define OP_PSH(MODE) \
SRC = OPER_8_##MODE(cpustate); \ SRC = OPER_8_##MODE(cpustate); \
@ -595,7 +583,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
if (SRC&0x40) \ if (SRC&0x40) \
{ m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \ { m37710i_push_8(cpustate, REG_PB>>16); CLK(1); } \
if (SRC&0x80) \ if (SRC&0x80) \
{ m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); } { m37710i_push_8(cpustate, cpustate->ipl); m37710i_push_8(cpustate, m37710i_get_reg_p(cpustate)); CLK(2); }
#endif // FLAG_SET_X #endif // FLAG_SET_X
#endif // FLAG_SET_M #endif // FLAG_SET_M
@ -605,7 +593,7 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
SRC = OPER_8_##MODE(cpustate); \ SRC = OPER_8_##MODE(cpustate); \
CLK(14); \ CLK(14); \
if (SRC&0x80) \ if (SRC&0x80) \
{ m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); CLK(3); } \ { m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); CLK(3); } \
if (SRC&0x40) \ if (SRC&0x40) \
{ REG_PB = m37710i_pull_8(cpustate) << 16; CLK(3); } \ { REG_PB = m37710i_pull_8(cpustate) << 16; CLK(3); } \
if (SRC&0x20) \ if (SRC&0x20) \
@ -639,7 +627,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
{ REG_BA = m37710i_pull_16(cpustate); CLK(3); } \ { REG_BA = m37710i_pull_16(cpustate); CLK(3); } \
if (SRC&0x1) \ if (SRC&0x1) \
{ REG_A = m37710i_pull_16(cpustate); CLK(3); } \ { REG_A = m37710i_pull_16(cpustate); CLK(3); } \
} } \
m37710i_update_irqs(cpustate)
/* M37710 Multiply */ /* M37710 Multiply */
#undef OP_MPY #undef OP_MPY
@ -1670,8 +1659,9 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
#undef OP_PLP #undef OP_PLP
#define OP_PLP() \ #define OP_PLP() \
CLK(CLK_OP + CLK_R8 + 2); \ CLK(CLK_OP + CLK_R8 + 2); \
m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); \ m37710i_set_reg_p(cpustate, m37710i_pull_8(cpustate)); \
m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)) m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); \
m37710i_update_irqs(cpustate)
/* M37710 Reset Program status word */ /* M37710 Reset Program status word */
#undef OP_REP #undef OP_REP
@ -1810,7 +1800,8 @@ INLINE uint EA_SIY(m37710i_cpu_struct *cpustate) {return MAKE_UINT_16(read_16_
m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); \ m37710i_set_reg_ipl(cpustate, m37710i_pull_8(cpustate)); \
m37710i_jump_16(cpustate, m37710i_pull_16(cpustate)); \ m37710i_jump_16(cpustate, m37710i_pull_16(cpustate)); \
REG_PB = m37710i_pull_8(cpustate) << 16; \ REG_PB = m37710i_pull_8(cpustate) << 16; \
m37710i_jumping(REG_PB | REG_PC) m37710i_jumping(REG_PB | REG_PC); \
m37710i_update_irqs(cpustate)
/* M37710 Return from Subroutine Long */ /* M37710 Return from Subroutine Long */
#undef OP_RTL #undef OP_RTL