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h8 io: More simplifications, thanks everyone for the pointers

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This commit is contained in:
Olivier Galibert 2023-06-08 18:16:47 +02:00
parent baddea6659
commit b76f18dbe8
13 changed files with 96 additions and 104 deletions
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1
src/devices/cpu/h8/gt913.cpp
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@ -268,7 +268,6 @@ device_memory_interface::space_config_vector gt913_device::memory_space_config()
{
return space_config_vector{
std::make_pair(AS_PROGRAM, &m_program_config),
std::make_pair(AS_IO, &m_io_config),
std::make_pair(AS_DATA, &m_data_config)
};
}

22
src/devices/cpu/h8/h8.cpp
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@ -18,10 +18,9 @@
h8_device::h8_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor map_delegate) :
cpu_device(mconfig, type, tag, owner, clock),
m_program_config("program", ENDIANNESS_BIG, 16, 16, 0, map_delegate),
m_io_config("io", ENDIANNESS_BIG, 16, 16, -1),
m_read_adc{ *this, *this, *this, *this, *this, *this, *this, *this },
m_read_port{ *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this },
m_write_port{ *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this, *this },
m_read_adc(*this),
m_read_port(*this),
m_write_port(*this),
m_PPC(0), m_NPC(0), m_PC(0), m_PIR(0), m_EXR(0), m_CCR(0), m_MAC(0), m_MACF(0),
m_TMP1(0), m_TMP2(0), m_TMPR(0), m_inst_state(0), m_inst_substate(0), m_icount(0), m_bcount(0), m_irq_vector(0), m_taken_irq_vector(0), m_irq_level(0), m_taken_irq_level(0), m_irq_required(false), m_irq_nmi(false)
{
@ -34,7 +33,7 @@ h8_device::h8_device(const machine_config &mconfig, device_type type, const char
m_has_trace = false;
m_has_hc = true;
for(int i=0; i != 8; i++)
for(unsigned int i=0; i != m_read_adc.size(); i++)
m_read_adc[i].bind().set([this, i]() { return adc_default(i); });
for(int i=0; i != PORT_COUNT; i++) {
m_read_port[i].bind().set([this, i]() { return port_default_r(i); });
@ -71,14 +70,10 @@ void h8_device::device_start()
{
space(AS_PROGRAM).cache(m_cache);
space(AS_PROGRAM).specific(m_program);
space(AS_IO).specific(m_io);
for(auto &r : m_read_adc)
r.resolve();
for(auto &r : m_read_port)
r.resolve();
for(auto &w : m_write_port)
w.resolve();
m_read_adc.resolve_all();
m_read_port.resolve_all();
m_write_port.resolve_all();
uint32_t pcmask = m_mode_advanced ? 0xffffff : 0xffff;
state_add<uint32_t>(H8_PC, "PC",
@ -321,8 +316,7 @@ void h8_device::internal_update()
device_memory_interface::space_config_vector h8_device::memory_space_config() const
{
return space_config_vector {
std::make_pair(AS_PROGRAM, &m_program_config),
std::make_pair(AS_IO, &m_io_config)
std::make_pair(AS_PROGRAM, &m_program_config)
};
}

9
src/devices/cpu/h8/h8.h
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@ -113,13 +113,12 @@ protected:
// device_disasm_interface overrides
virtual std::unique_ptr<util::disasm_interface> create_disassembler() override;
address_space_config m_program_config, m_io_config;
address_space_config m_program_config;
memory_access<32, 1, 0, ENDIANNESS_BIG>::cache m_cache;
memory_access<32, 1, 0, ENDIANNESS_BIG>::specific m_program;
memory_access<16, 1, -1, ENDIANNESS_BIG>::specific m_io;
std::array<devcb_read16, 8> m_read_adc;
std::array<devcb_read8, PORT_COUNT> m_read_port;
std::array<devcb_write8, PORT_COUNT> m_write_port;
devcb_read16::array<8> m_read_adc;
devcb_read8::array<PORT_COUNT> m_read_port;
devcb_write8::array<PORT_COUNT> m_write_port;
h8gen_dma_device *m_dma_device;
h8_dtc_device *m_dtc_device;

16
src/devices/sound/xt446.cpp
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@ -75,14 +75,14 @@ void xt446_device::device_add_mconfig(machine_config &config)
{
H8S2655(config, m_maincpu, 16_MHz_XTAL);
m_maincpu->set_addrmap(AS_PROGRAM, &xt446_device::xt446_map);
m_maincpu->read_adc(0).set([]() -> u16 { return 0; });
m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
m_maincpu->read_adc(2).set([]() -> u16 { return 0; });
m_maincpu->read_adc(3).set([]() -> u16 { return 0; });
m_maincpu->read_adc(4).set([]() -> u16 { return 0; });
m_maincpu->read_adc(5).set([]() -> u16 { return 0; });
m_maincpu->read_adc(6).set([]() -> u16 { return 0x200; });
m_maincpu->read_adc(7).set([]() -> u16 { return 0x200; });
m_maincpu->read_adc(0).set_constant(0);
m_maincpu->read_adc(1).set_constant(0);
m_maincpu->read_adc(2).set_constant(0);
m_maincpu->read_adc(3).set_constant(0);
m_maincpu->read_adc(4).set_constant(0);
m_maincpu->read_adc(5).set_constant(0);
m_maincpu->read_adc(6).set_constant(0x200);
m_maincpu->read_adc(7).set_constant(0x200);
SWP30(config, m_swp30);
m_swp30->set_addrmap(0, &xt446_device::swp30_map);

60
src/mame/casio/ctk551.cpp
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@ -451,16 +451,16 @@ void ctk551_state::ap10(machine_config& config)
m_maincpu->set_addrmap(AS_DATA, &ctk551_state::ap10_map);
m_maincpu->add_route(0, "lspeaker", 1.0);
m_maincpu->add_route(1, "rspeaker", 1.0);
m_maincpu->read_adc(0).set([]() -> u16 { return 0; });
m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
m_maincpu->read_adc(0).set_constant(0);
m_maincpu->read_adc(1).set_constant(0);
m_maincpu->read_port1().set_ioport("P1");
m_maincpu->write_port1().set_ioport("P1");
m_maincpu->read_port2().set([]() -> u16 { return 0; });
m_maincpu->write_port2().set([](u16) {});
m_maincpu->read_port3().set([]() -> u16 { return 0; });
m_maincpu->write_port3().set([](u16) {});
m_maincpu->read_port4().set([]() -> u16 { return 0; });
m_maincpu->write_port4().set([](u16) {});
m_maincpu->read_port2().set_constant(0);
m_maincpu->write_port2().set_nop();
m_maincpu->read_port3().set_constant(0);
m_maincpu->write_port3().set_nop();
m_maincpu->read_port4().set_constant(0);
m_maincpu->write_port4().set_nop();
NVRAM(config, "nvram");
@ -488,14 +488,14 @@ void ctk551_state::ctk530(machine_config& config)
m_maincpu->set_addrmap(AS_DATA, &ctk551_state::ctk530_map);
m_maincpu->add_route(0, "lspeaker", 1.0);
m_maincpu->add_route(1, "rspeaker", 1.0);
m_maincpu->read_adc(0).set([]() -> u16 { return 0; });
m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
m_maincpu->read_adc(0).set_constant(0);
m_maincpu->read_adc(1).set_constant(0);
m_maincpu->read_port1().set_ioport("P1");
m_maincpu->write_port1().set_ioport("P1");
m_maincpu->read_port2().set([]() -> u16 { return 0; });
m_maincpu->write_port2().set([](u16) {});
m_maincpu->read_port3().set([]() -> u16 { return 0; });
m_maincpu->write_port3().set([](u16) {});
m_maincpu->read_port2().set_constant(0);
m_maincpu->write_port2().set_nop();
m_maincpu->read_port3().set_constant(0);
m_maincpu->write_port3().set_nop();
m_maincpu->write_port4().set_ioport("PLE");
// MIDI
@ -524,16 +524,16 @@ void ctk551_state::gz70sp(machine_config& config)
m_maincpu->set_addrmap(AS_DATA, &ctk551_state::gz70sp_map);
m_maincpu->add_route(0, "lspeaker", 1.0);
m_maincpu->add_route(1, "rspeaker", 1.0);
m_maincpu->read_adc(0).set([]() -> u16 { return 0; });
m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
m_maincpu->read_adc(0).set_constant(0);
m_maincpu->read_adc(1).set_constant(0);
m_maincpu->read_port1().set_ioport("P1");
m_maincpu->write_port1().set_ioport("P1");
m_maincpu->read_port2().set_ioport("P2");
m_maincpu->write_port2().set_ioport("P2");
m_maincpu->read_port3().set([]() -> u16 { return 0; });
m_maincpu->write_port3().set([](u16) {});
m_maincpu->read_port4().set([]() -> u16 { return 0; });
m_maincpu->write_port4().set([](u16) {});
m_maincpu->read_port3().set_constant(0);
m_maincpu->write_port3().set_nop();
m_maincpu->read_port4().set_constant(0);
m_maincpu->write_port4().set_nop();
// MIDI (sci0 for RS232/422, sci1 for standard MIDI)
auto& mdin(MIDI_PORT(config, "mdin"));
@ -551,16 +551,16 @@ void ctk551_state::ctk601(machine_config& config)
m_maincpu->set_addrmap(AS_DATA, &ctk551_state::ctk601_map);
m_maincpu->add_route(0, "lspeaker", 1.0);
m_maincpu->add_route(1, "rspeaker", 1.0);
m_maincpu->read_adc(0).set([]() -> u16 { return 0; });
m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
m_maincpu->read_adc(0).set_constant(0);
m_maincpu->read_adc(1).set_constant(0);
m_maincpu->read_port1().set_ioport("P1_R");
m_maincpu->write_port1().set_ioport("P1_W");
m_maincpu->read_port2().set_ioport("P2");
m_maincpu->write_port2().set_ioport("P2");
m_maincpu->read_port3().set([]() -> u16 { return 0; }); // port 3 pins are shared w/ key matrix
m_maincpu->write_port3().set([](u16) {});
m_maincpu->read_port4().set([]() -> u16 { return 0; });
m_maincpu->write_port4().set([](u16) {});
m_maincpu->read_port3().set_constant(0); // port 3 pins are shared w/ key matrix
m_maincpu->write_port3().set_nop();
m_maincpu->read_port4().set_constant(0);
m_maincpu->write_port4().set_nop();
// TODO: DSP
@ -602,10 +602,10 @@ void ctk551_state::ctk551(machine_config &config)
m_maincpu->write_port1().set_ioport("P1_W");
m_maincpu->read_port2().set_ioport("P2");
m_maincpu->write_port2().set_ioport("P2");
m_maincpu->read_port3().set([]() -> u16 { return 0; }); // port 3 pins are shared w/ key matrix
m_maincpu->write_port3().set([](u16) {});
m_maincpu->read_port4().set([]() -> u16 { return 0; });
m_maincpu->write_port4().set([](u16) {});
m_maincpu->read_port3().set_constant(0); // port 3 pins are shared w/ key matrix
m_maincpu->write_port3().set_nop();
m_maincpu->read_port4().set_constant(0);
m_maincpu->write_port4().set_nop();
// MIDI
auto &mdin(MIDI_PORT(config, "mdin"));

8
src/mame/namco/namcond1.cpp
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@ -496,10 +496,10 @@ void namcond1_state::namcond1(machine_config &config)
H83002(config, m_mcu, XTAL(49'152'000) / 3);
m_mcu->set_addrmap(AS_PROGRAM, &namcond1_state::h8rwmap);
m_mcu->set_vblank_int("screen", FUNC(namcond1_state::mcu_interrupt));
m_mcu->read_adc(0).set([]() -> u16 { return 0; }); // MCU reads these, but the games have no analog controls
m_mcu->read_adc(1).set([]() -> u16 { return 0; });
m_mcu->read_adc(2).set([]() -> u16 { return 0; });
m_mcu->read_adc(3).set([]() -> u16 { return 0; });
m_mcu->read_adc(0).set_constant(0); // MCU reads these, but the games have no analog controls
m_mcu->read_adc(1).set_constant(0);
m_mcu->read_adc(2).set_constant(0);
m_mcu->read_adc(3).set_constant(0);
m_mcu->read_port7().set(FUNC(namcond1_state::mcu_p7_read));
m_mcu->read_porta().set(FUNC(namcond1_state::mcu_pa_read));
m_mcu->write_porta().set(FUNC(namcond1_state::mcu_pa_write));

26
src/mame/namco/namcos12.cpp
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@ -1691,14 +1691,14 @@ void namcos12_state::namcos12_mobo(machine_config &config)
/* basic machine hardware */
H83002(config, m_sub, 16934400); // frequency based on research (superctr)
m_sub->set_addrmap(AS_PROGRAM, &namcos12_state::s12h8rwmap);
m_sub->read_adc(0).set([]() -> u16 { return 0; });
m_sub->read_adc(1).set([]() -> u16 { return 0; });
m_sub->read_adc(2).set([]() -> u16 { return 0; });
m_sub->read_adc(3).set([]() -> u16 { return 0; });
m_sub->read_adc(0).set_constant(0);
m_sub->read_adc(1).set_constant(0);
m_sub->read_adc(2).set_constant(0);
m_sub->read_adc(3).set_constant(0);
m_sub->read_port6().set(FUNC(namcos12_state::s12_mcu_p6_r));
m_sub->read_port7().set_ioport("DSW");
m_sub->read_port8().set(FUNC(namcos12_state::s12_mcu_p8_r));
m_sub->write_port8().set([](u16) {});
m_sub->write_port8().set_nop();
m_sub->read_porta().set(FUNC(namcos12_state::s12_mcu_pa_r));
m_sub->write_porta().set(FUNC(namcos12_state::s12_mcu_pa_w));
m_sub->read_portb().set(FUNC(namcos12_state::s12_mcu_portB_r));
@ -1889,13 +1889,13 @@ void namcos12_boothack_state::aplarail(machine_config &config)
// modify H8/3002 map to omit direct-connected controls
m_sub->set_addrmap(AS_PROGRAM, &namcos12_boothack_state::s12h8rwjvsmap);
m_sub->read_adc(0).set_ioport("LEVER");
m_sub->read_adc(1).set([]() -> u16 { return 0; });
m_sub->read_adc(2).set([]() -> u16 { return 0; });
m_sub->read_adc(3).set([]() -> u16 { return 0; });
m_sub->read_adc(1).set_constant(0);
m_sub->read_adc(2).set_constant(0);
m_sub->read_adc(3).set_constant(0);
m_sub->read_port6().set(FUNC(namcos12_boothack_state::s12_mcu_p6_r));
m_sub->read_port7().set_ioport("DSW");
m_sub->read_port8().set(FUNC(namcos12_boothack_state::s12_mcu_jvs_p8_r));
m_sub->write_port8().set([](u8) {});
m_sub->write_port8().set_nop();
m_sub->read_porta().set(FUNC(namcos12_boothack_state::s12_mcu_pa_r));
m_sub->write_porta().set(FUNC(namcos12_boothack_state::s12_mcu_pa_w));
m_sub->read_portb().set(FUNC(namcos12_boothack_state::s12_mcu_portB_r));
@ -1903,10 +1903,10 @@ void namcos12_boothack_state::aplarail(machine_config &config)
h83334_device &iocpu(H83334(config, "iocpu", JVSCLOCK));
iocpu.set_addrmap(AS_PROGRAM, &namcos12_boothack_state::plarailjvsmap);
iocpu.read_adc(0).set([]() -> u16 { return 0; });
iocpu.read_adc(1).set([]() -> u16 { return 0; });
iocpu.read_adc(2).set([]() -> u16 { return 0; });
iocpu.read_adc(3).set([]() -> u16 { return 0; });
iocpu.read_adc(0).set_constant(0);
iocpu.read_adc(1).set_constant(0);
iocpu.read_adc(2).set_constant(0);
iocpu.read_adc(3).set_constant(0);
iocpu.read_port4().set(FUNC(namcos12_boothack_state::iob_p4_r));
iocpu.write_port4().set(FUNC(namcos12_boothack_state::iob_p4_w));
iocpu.read_port6().set_ioport("SERVICE");

22
src/mame/namco/namcos23.cpp
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@ -3793,10 +3793,10 @@ void namcos23_state::gorgon(machine_config &config)
H83002(config, m_subcpu, H8CLOCK);
m_subcpu->set_addrmap(AS_PROGRAM, &namcos23_state::s23h8rwmap);
m_subcpu->read_adc(0).set([]() -> u16 { return 0; });
m_subcpu->read_adc(1).set([]() -> u16 { return 0; });
m_subcpu->read_adc(2).set([]() -> u16 { return 0; });
m_subcpu->read_adc(3).set([]() -> u16 { return 0; });
m_subcpu->read_adc(0).set_constant(0);
m_subcpu->read_adc(1).set_constant(0);
m_subcpu->read_adc(2).set_constant(0);
m_subcpu->read_adc(3).set_constant(0);
m_subcpu->read_port6().set(FUNC(namcos23_state::mcu_p6_r));
m_subcpu->write_port6().set(FUNC(namcos23_state::mcu_p6_w));
m_subcpu->read_port8().set(FUNC(namcos23_state::mcu_p8_r));
@ -3821,11 +3821,11 @@ void namcos23_state::gorgon(machine_config &config)
m_iocpu->read_adc(7).set_ioport("ADC7");
m_iocpu->read_port4().set(FUNC(namcos23_state::iob_p4_r));
m_iocpu->write_port4().set(FUNC(namcos23_state::iob_p4_w));
m_iocpu->write_port5().set([](u8) {}); // bit 2 = status LED to indicate transmitting packet to main
m_iocpu->write_port5().set_nop(); // bit 2 = status LED to indicate transmitting packet to main
m_iocpu->read_port6().set(FUNC(namcos23_state::iob_p6_r));
m_iocpu->write_port6().set(FUNC(namcos23_state::iob_p6_w));
m_iocpu->write_port8().set([](u8) {}); // unknown - used on ASCA-5 only
m_iocpu->write_port9().set([](u8) {}); // unknown - used on ASCA-5 only
m_iocpu->write_port8().set_nop(); // unknown - used on ASCA-5 only
m_iocpu->write_port9().set_nop(); // unknown - used on ASCA-5 only
m_iocpu->subdevice<h8_sci_device>("sci0")->tx_handler().set("subcpu:sci0", FUNC(h8_sci_device::rx_w));
m_subcpu->subdevice<h8_sci_device>("sci0")->tx_handler().set("iocpu:sci0", FUNC(h8_sci_device::rx_w));
@ -3880,10 +3880,10 @@ void namcos23_state::s23(machine_config &config)
H83002(config, m_subcpu, H8CLOCK);
m_subcpu->set_addrmap(AS_PROGRAM, &namcos23_state::s23h8rwmap);
m_subcpu->read_adc(0).set([]() -> u16 { return 0; });
m_subcpu->read_adc(1).set([]() -> u16 { return 0; });
m_subcpu->read_adc(2).set([]() -> u16 { return 0; });
m_subcpu->read_adc(3).set([]() -> u16 { return 0; });
m_subcpu->read_adc(0).set_constant(0);
m_subcpu->read_adc(1).set_constant(0);
m_subcpu->read_adc(2).set_constant(0);
m_subcpu->read_adc(3).set_constant(0);
m_subcpu->read_port6().set(FUNC(namcos23_state::mcu_p6_r));
m_subcpu->write_port6().set(FUNC(namcos23_state::mcu_p6_w));
m_subcpu->read_port8().set(FUNC(namcos23_state::mcu_p8_r));

4
src/mame/taito/invqix.cpp
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@ -324,7 +324,7 @@ void invqix_state::invqix(machine_config &config)
m_maincpu->set_periodic_int(FUNC(invqix_state::irq0_line_hold), attotime::from_hz(60));
m_maincpu->read_port1().set_ioport("P1");
m_maincpu->read_port2().set_ioport("SYSTEM");
m_maincpu->write_port2().set([](u8) {});
m_maincpu->write_port2().set_nop();
m_maincpu->read_port3().set(FUNC(invqix_state::port3_r));
m_maincpu->write_port3().set(FUNC(invqix_state::port3_w));
m_maincpu->read_port4().set_ioport("P4");
@ -334,7 +334,7 @@ void invqix_state::invqix(machine_config &config)
m_maincpu->write_port6().set(FUNC(invqix_state::port6_w));
m_maincpu->read_porta().set(FUNC(invqix_state::porta_r));
m_maincpu->read_portg().set(FUNC(invqix_state::portg_r));
m_maincpu->write_portg().set([](u8) {});
m_maincpu->write_portg().set_nop();
/* video hardware */
screen_device &screen(SCREEN(config, "screen", SCREEN_TYPE_RASTER));

6
src/mame/yamaha/ymmu100.cpp
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@ -675,11 +675,11 @@ void mu100_state::mu100(machine_config &config)
H8S2655(config, m_maincpu, 16_MHz_XTAL);
m_maincpu->set_addrmap(AS_PROGRAM, &mu100_state::mu100_map);
m_maincpu->read_adc(0).set(FUNC(mu100_state::adc_ar_r));
m_maincpu->read_adc(1).set([]() -> u16 { return 0; });
m_maincpu->read_adc(1).set_constant(0);
m_maincpu->read_adc(2).set(FUNC(mu100_state::adc_al_r));
m_maincpu->read_adc(3).set([]() -> u16 { return 0; });
m_maincpu->read_adc(3).set_constant(0);
m_maincpu->read_adc(4).set(FUNC(mu100_state::adc_midisw_r));
m_maincpu->read_adc(5).set([]() -> u16 { return 0; });
m_maincpu->read_adc(5).set_constant(0);
m_maincpu->read_adc(6).set(FUNC(mu100_state::adc_battery_r));
m_maincpu->read_adc(7).set(FUNC(mu100_state::adc_type_r));
m_maincpu->read_port1().set(FUNC(mu100_state::p1_r));

8
src/mame/yamaha/ymmu50.cpp
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@ -206,13 +206,13 @@ void mu50_state::mu50(machine_config &config)
H83003(config, m_mu50cpu, 12_MHz_XTAL);
m_mu50cpu->set_addrmap(AS_PROGRAM, &mu50_state::mu50_map);
m_mu50cpu->read_adc(0).set(FUNC(mu50_state::adc_ar_r));
m_mu50cpu->read_adc(1).set([]() -> u16 { return 0; });
m_mu50cpu->read_adc(1).set_constant(0);
m_mu50cpu->read_adc(2).set(FUNC(mu50_state::adc_al_r));
m_mu50cpu->read_adc(3).set([]() -> u16 { return 0; });
m_mu50cpu->read_adc(3).set_constant(0);
m_mu50cpu->read_adc(4).set(FUNC(mu50_state::adc_midisw_r));
m_mu50cpu->read_adc(5).set([]() -> u16 { return 0; });
m_mu50cpu->read_adc(5).set_constant(0);
m_mu50cpu->read_adc(6).set(FUNC(mu50_state::adc_battery_r));
m_mu50cpu->read_adc(7).set([]() -> u16 { return 0; });
m_mu50cpu->read_adc(7).set_constant(0);
m_mu50cpu->read_port6().set(FUNC(mu50_state::p6_r));
m_mu50cpu->write_port6().set(FUNC(mu50_state::p6_w));
m_mu50cpu->read_porta().set(FUNC(mu50_state::pa_r));

8
src/mame/yamaha/ymmu80.cpp
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@ -322,13 +322,13 @@ void mu80_state::mu80(machine_config &config)
H83002(config, m_mu80cpu, 12_MHz_XTAL);
m_mu80cpu->set_addrmap(AS_PROGRAM, &mu80_state::mu80_map);
m_mu80cpu->read_adc(0).set(FUNC(mu80_state::adc_ar_r));
m_mu80cpu->read_adc(1).set([]() -> u16 { return 0; });
m_mu80cpu->read_adc(1).set_constant(0);
m_mu80cpu->read_adc(2).set(FUNC(mu80_state::adc_al_r));
m_mu80cpu->read_adc(3).set([]() -> u16 { return 0; });
m_mu80cpu->read_adc(3).set_constant(0);
m_mu80cpu->read_adc(4).set(FUNC(mu80_state::adc_midisw_r));
m_mu80cpu->read_adc(5).set([]() -> u16 { return 0; });
m_mu80cpu->read_adc(5).set_constant(0);
m_mu80cpu->read_adc(6).set(FUNC(mu80_state::adc_battery_r));
m_mu80cpu->read_adc(7).set([]() -> u16 { return 0; }); // inputmod from the gate array
m_mu80cpu->read_adc(7).set_constant(0); // inputmod from the gate array
m_mu80cpu->read_port6().set(FUNC(mu80_state::p6_r));
m_mu80cpu->write_port6().set(FUNC(mu80_state::p6_w));
m_mu80cpu->read_porta().set(FUNC(mu80_state::pa_r));

10
src/mame/yamaha/ymvl70.cpp
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@ -202,13 +202,13 @@ void vl70_state::vl70(machine_config &config)
H83003(config, m_vl70cpu, 10_MHz_XTAL);
m_vl70cpu->set_addrmap(AS_PROGRAM, &vl70_state::vl70_map);
m_vl70cpu->read_adc(0).set(FUNC(vl70_state::adc_breath_r));
m_vl70cpu->read_adc(1).set([]() -> u16 { return 0; });
m_vl70cpu->read_adc(1).set_constant(0);
m_vl70cpu->read_adc(2).set(FUNC(vl70_state::adc_midisw_r));
m_vl70cpu->read_adc(3).set([]() -> u16 { return 0; });
m_vl70cpu->read_adc(3).set_constant(0);
m_vl70cpu->read_adc(4).set(FUNC(vl70_state::adc_battery_r));
m_vl70cpu->read_adc(5).set([]() -> u16 { return 0; });
m_vl70cpu->read_adc(6).set([]() -> u16 { return 0; });
m_vl70cpu->read_adc(7).set([]() -> u16 { return 0; });
m_vl70cpu->read_adc(5).set_constant(0);
m_vl70cpu->read_adc(6).set_constant(0);
m_vl70cpu->read_adc(7).set_constant(0);
m_vl70cpu->read_port6().set(FUNC(vl70_state::p6_r));
m_vl70cpu->write_port6().set(FUNC(vl70_state::p6_w));
m_vl70cpu->read_porta().set(FUNC(vl70_state::pa_r));