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https://github.com/holub/mame
synced 2025-07-02 00:29:37 +03:00
mz2500.cpp: converted memory bank to address_map_bank_device array (nw)
This commit is contained in:
parent
57a07f7df4
commit
b8f7bce7e2
@ -31,17 +31,6 @@
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- Sound Gal Music Editor: wants a "master disk", that apparently isn't available;
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- Sound Gal Music Editor: wants a "master disk", that apparently isn't available;
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- Yukar K2 (normal version): moans about something, DFJustin: "please put the system disk back to normal", disk write-protected?
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- Yukar K2 (normal version): moans about something, DFJustin: "please put the system disk back to normal", disk write-protected?
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memory map:
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0x00000-0x3ffff Work RAM
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0x40000-0x5ffff CG RAM
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0x60000-0x67fff "Read modify write" area (related to the CG RAM) (0x30-0x33)
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0x68000-0x6ffff IPL ROM (0x34-0x37)
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0x70000-0x71fff TVRAM (0x38)
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0x72000-0x73fff Kanji ROM / PCG RAM (banked) (0x39)
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0x74000-0x75fff Dictionary ROM (banked) (0x3a)
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0x76000-0x77fff NOP (0x3b)
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0x78000-0x7ffff Phone ROM (0x3c-0x3f)
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********************************************************************************************************************************/
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********************************************************************************************************************************/
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#include "emu.h"
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#include "emu.h"
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@ -101,7 +90,7 @@ void mz2500_state::mz2500_draw_pixel(bitmap_ind16 &bitmap,int x,int y,uint16_t
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void mz2500_state::draw_80x25(bitmap_ind16 &bitmap,const rectangle &cliprect,uint16_t map_addr)
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void mz2500_state::draw_80x25(bitmap_ind16 &bitmap,const rectangle &cliprect,uint16_t map_addr)
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{
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{
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uint8_t *vram = m_main_ram.get(); // TODO
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uint8_t *vram = m_tvram;
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int x,y,count,xi,yi;
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int x,y,count,xi,yi;
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uint8_t *gfx_data;
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uint8_t *gfx_data;
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uint8_t y_step;
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uint8_t y_step;
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@ -118,10 +107,10 @@ void mz2500_state::draw_80x25(bitmap_ind16 &bitmap,const rectangle &cliprect,uin
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{
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{
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for (x=0;x<80;x++)
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for (x=0;x<80;x++)
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{
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{
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int tile = vram[0x70000+count+0x0000] & 0xff;
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int tile = vram[count+0x0000] & 0xff;
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int attr = vram[0x70000+count+0x0800];
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int attr = vram[count+0x0800];
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int tile_bank = vram[0x70000+count+0x1000] & 0x3f;
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int tile_bank = vram[count+0x1000] & 0x3f;
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int gfx_sel = (attr & 0x38) | (vram[0x70000+count+0x1000] & 0xc0);
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int gfx_sel = (attr & 0x38) | (vram[count+0x1000] & 0xc0);
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int color = attr & 7;
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int color = attr & 7;
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int inv_col = (attr & 0x40) >> 6;
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int inv_col = (attr & 0x40) >> 6;
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@ -190,7 +179,7 @@ void mz2500_state::draw_80x25(bitmap_ind16 &bitmap,const rectangle &cliprect,uin
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void mz2500_state::draw_40x25(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,uint16_t map_addr)
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void mz2500_state::draw_40x25(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,uint16_t map_addr)
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{
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{
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uint8_t *vram = m_main_ram.get(); // TODO
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uint8_t *vram = m_tvram;
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int x,y,count,xi,yi;
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int x,y,count,xi,yi;
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uint8_t *gfx_data;
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uint8_t *gfx_data;
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uint8_t y_step;
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uint8_t y_step;
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@ -207,10 +196,10 @@ void mz2500_state::draw_40x25(bitmap_ind16 &bitmap,const rectangle &cliprect,int
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{
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{
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for (x=0;x<40;x++)
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for (x=0;x<40;x++)
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{
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{
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int tile = vram[0x70000+count+0x0000] & 0xff;
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int tile = vram[count+0x0000] & 0xff;
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int attr = vram[0x70000+count+0x0800];
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int attr = vram[count+0x0800];
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int tile_bank = vram[0x70000+count+0x1000] & 0x3f;
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int tile_bank = vram[count+0x1000] & 0x3f;
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int gfx_sel = (attr & 0x38) | (vram[0x70000+count+0x1000] & 0xc0);
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int gfx_sel = (attr & 0x38) | (vram[count+0x1000] & 0xc0);
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//int gfx_num;
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//int gfx_num;
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int color = attr & 7;
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int color = attr & 7;
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int inv_col = (attr & 0x40) >> 6;
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int inv_col = (attr & 0x40) >> 6;
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@ -281,12 +270,12 @@ void mz2500_state::draw_40x25(bitmap_ind16 &bitmap,const rectangle &cliprect,int
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void mz2500_state::draw_cg4_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int pri)
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void mz2500_state::draw_cg4_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int pri)
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{
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{
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uint32_t count;
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uint32_t count;
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uint8_t *vram = m_main_ram.get(); // TODO
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uint8_t *vram = m_cgram;
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uint8_t pen,pen_bit[2];
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uint8_t pen,pen_bit[2];
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int x,y,xi,pen_i;
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int x,y,xi,pen_i;
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int res_x,res_y;
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int res_x,res_y;
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count = 0x40000;
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count = 0x0000;
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for(y=0;y<400;y++)
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for(y=0;y<400;y++)
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{
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{
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@ -322,7 +311,7 @@ void mz2500_state::draw_cg4_screen(bitmap_ind16 &bitmap,const rectangle &cliprec
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void mz2500_state::draw_cg16_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int x_size,int pri)
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void mz2500_state::draw_cg16_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int x_size,int pri)
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{
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{
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uint32_t count;
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uint32_t count;
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uint8_t *vram = m_main_ram.get(); //TODO
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uint8_t *vram = m_cgram; //TODO
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uint8_t pen,pen_bit[4];
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uint8_t pen,pen_bit[4];
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int x,y,xi,pen_i;
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int x,y,xi,pen_i;
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uint32_t wa_reg;
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uint32_t wa_reg;
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@ -356,10 +345,10 @@ void mz2500_state::draw_cg16_screen(bitmap_ind16 &bitmap,const rectangle &clipre
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if(res_x < m_cg_hs || res_x >= m_cg_he || res_y < m_cg_vs || res_y >= m_cg_ve)
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if(res_x < m_cg_hs || res_x >= m_cg_he || res_y < m_cg_vs || res_y >= m_cg_ve)
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continue;
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continue;
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pen_bit[0] = (vram[count+0x40000+((plane & 1) * 0x2000)+(((plane & 2)>>1) * 0x10000)]>>(xi)) & 1 ? (pen_mask & 0x01) : 0; //B
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pen_bit[0] = (vram[count+0x0000+((plane & 1) * 0x2000)+(((plane & 2)>>1) * 0x10000)]>>(xi)) & 1 ? (pen_mask & 0x01) : 0; //B
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pen_bit[1] = (vram[count+0x44000+((plane & 1) * 0x2000)+(((plane & 2)>>1) * 0x10000)]>>(xi)) & 1 ? (pen_mask & 0x02) : 0; //R
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pen_bit[1] = (vram[count+0x4000+((plane & 1) * 0x2000)+(((plane & 2)>>1) * 0x10000)]>>(xi)) & 1 ? (pen_mask & 0x02) : 0; //R
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pen_bit[2] = (vram[count+0x48000+((plane & 1) * 0x2000)+(((plane & 2)>>1) * 0x10000)]>>(xi)) & 1 ? (pen_mask & 0x04) : 0; //G
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pen_bit[2] = (vram[count+0x8000+((plane & 1) * 0x2000)+(((plane & 2)>>1) * 0x10000)]>>(xi)) & 1 ? (pen_mask & 0x04) : 0; //G
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pen_bit[3] = (vram[count+0x4c000+((plane & 1) * 0x2000)+(((plane & 2)>>1) * 0x10000)]>>(xi)) & 1 ? (pen_mask & 0x08) : 0; //I
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pen_bit[3] = (vram[count+0xc000+((plane & 1) * 0x2000)+(((plane & 2)>>1) * 0x10000)]>>(xi)) & 1 ? (pen_mask & 0x08) : 0; //I
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pen = 0;
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pen = 0;
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for(pen_i=0;pen_i<4;pen_i++)
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for(pen_i=0;pen_i<4;pen_i++)
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@ -379,7 +368,7 @@ void mz2500_state::draw_cg16_screen(bitmap_ind16 &bitmap,const rectangle &clipre
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void mz2500_state::draw_cg256_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int pri)
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void mz2500_state::draw_cg256_screen(bitmap_ind16 &bitmap,const rectangle &cliprect,int plane,int pri)
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{
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{
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uint32_t count;
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uint32_t count;
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uint8_t *vram = m_main_ram.get();
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uint8_t *vram = m_cgram;
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uint8_t pen,pen_bit[8];
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uint8_t pen,pen_bit[8];
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int x,y,xi,pen_i;
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int x,y,xi,pen_i;
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uint32_t wa_reg;
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uint32_t wa_reg;
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@ -409,14 +398,14 @@ void mz2500_state::draw_cg256_screen(bitmap_ind16 &bitmap,const rectangle &clipr
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if(res_x < m_cg_hs || res_x >= m_cg_he || res_y < m_cg_vs || res_y >= m_cg_ve)
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if(res_x < m_cg_hs || res_x >= m_cg_he || res_y < m_cg_vs || res_y >= m_cg_ve)
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continue;
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continue;
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pen_bit[0] = (vram[count + 0x40000 + (((plane & 2)>>1) * 0x10000) + 0x2000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x10) : 0; // B1
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pen_bit[0] = (vram[count + 0x0000 + (((plane & 2)>>1) * 0x10000) + 0x2000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x10) : 0; // B1
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pen_bit[1] = (vram[count + 0x40000 + (((plane & 2)>>1) * 0x10000) + 0x0000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x01) : 0; // B0
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pen_bit[1] = (vram[count + 0x0000 + (((plane & 2)>>1) * 0x10000) + 0x0000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x01) : 0; // B0
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pen_bit[2] = (vram[count + 0x40000 + (((plane & 2)>>1) * 0x10000) + 0x6000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x20) : 0; // R1
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pen_bit[2] = (vram[count + 0x0000 + (((plane & 2)>>1) * 0x10000) + 0x6000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x20) : 0; // R1
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pen_bit[3] = (vram[count + 0x40000 + (((plane & 2)>>1) * 0x10000) + 0x4000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x02) : 0; // R0
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pen_bit[3] = (vram[count + 0x0000 + (((plane & 2)>>1) * 0x10000) + 0x4000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x02) : 0; // R0
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pen_bit[4] = (vram[count + 0x40000 + (((plane & 2)>>1) * 0x10000) + 0xa000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x40) : 0; // G1
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pen_bit[4] = (vram[count + 0x0000 + (((plane & 2)>>1) * 0x10000) + 0xa000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x40) : 0; // G1
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pen_bit[5] = (vram[count + 0x40000 + (((plane & 2)>>1) * 0x10000) + 0x8000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x04) : 0; // G0
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pen_bit[5] = (vram[count + 0x0000 + (((plane & 2)>>1) * 0x10000) + 0x8000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x04) : 0; // G0
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pen_bit[6] = (vram[count + 0x40000 + (((plane & 2)>>1) * 0x10000) + 0xe000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x80) : 0; // I1
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pen_bit[6] = (vram[count + 0x0000 + (((plane & 2)>>1) * 0x10000) + 0xe000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x80) : 0; // I1
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pen_bit[7] = (vram[count + 0x40000 + (((plane & 2)>>1) * 0x10000) + 0xc000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x08) : 0; // I0
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pen_bit[7] = (vram[count + 0x0000 + (((plane & 2)>>1) * 0x10000) + 0xc000]>>(xi)) & 1 ? (m_cg_reg[0x18] & 0x08) : 0; // I0
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pen = 0;
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pen = 0;
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for(pen_i=0;pen_i<8;pen_i++)
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for(pen_i=0;pen_i<8;pen_i++)
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@ -608,202 +597,6 @@ uint8_t mz2500_state::mz2500_cg_latch_compare()
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return res;
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return res;
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}
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}
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uint8_t mz2500_state::mz2500_ram_read(uint16_t offset, uint8_t bank_num)
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{
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uint8_t *ram = m_main_ram.get(); // TODO
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uint8_t cur_bank = m_bank_val[bank_num];
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switch(cur_bank)
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{
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case 0x30:
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case 0x31:
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case 0x32:
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case 0x33:
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{
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// READ MODIFY WRITE
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if(m_cg_reg[0x0e] == 0x3)
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{
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// ...
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}
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else
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{
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int plane;
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m_cg_latch[0] = ram[offset+((cur_bank & 3)*0x2000)+0x40000]; //B
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m_cg_latch[1] = ram[offset+((cur_bank & 3)*0x2000)+0x44000]; //R
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m_cg_latch[2] = ram[offset+((cur_bank & 3)*0x2000)+0x48000]; //G
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m_cg_latch[3] = ram[offset+((cur_bank & 3)*0x2000)+0x4c000]; //I
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plane = m_cg_reg[0x07] & 3;
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if(m_cg_reg[0x07] & 0x10)
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return mz2500_cg_latch_compare();
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else
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return m_cg_latch[plane];
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}
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}
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break;
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case 0x39:
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{
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if(m_kanji_bank & 0x80) //kanji ROM
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return m_kanji_rom[(offset & 0x7ff)+((m_kanji_bank & 0x7f)*0x800)];
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else //PCG RAM
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return m_pcg_ram[offset];
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}
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case 0x3a:
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{
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return m_dic_rom[(offset & 0x1fff) + ((m_dic_bank & 0x1f)*0x2000)];
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}
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case 0x3c:
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case 0x3d:
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case 0x3e:
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case 0x3f:
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{
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return m_phone_rom[offset+(cur_bank & 3)*0x2000];
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}
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default: return ram[offset+cur_bank*0x2000];
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}
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// never executed
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return 0xff;
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}
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void mz2500_state::mz2500_ram_write(uint16_t offset, uint8_t data, uint8_t bank_num)
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{
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uint8_t *ram = m_main_ram.get(); // TODO
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uint8_t cur_bank = m_bank_val[bank_num];
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// if(cur_bank >= 0x30 && cur_bank <= 0x33)
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// printf("CG REG = %02x %02x %02x %02x | offset = %04x | data = %02x\n",m_cg_reg[0],m_cg_reg[1],m_cg_reg[2],m_cg_reg[3],offset,data);
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switch(cur_bank)
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{
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case 0x30:
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case 0x31:
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case 0x32:
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case 0x33:
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{
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// READ MODIFY WRITE
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if(m_cg_reg[0x0e] == 0x3)
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{
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// ...
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}
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else
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{
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if((m_cg_reg[0x05] & 0xc0) == 0x00) //replace
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{
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if(m_cg_reg[5] & 1) //B
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{
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ram[offset+((cur_bank & 3)*0x2000)+0x40000] &= ~m_cg_reg[6];
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ram[offset+((cur_bank & 3)*0x2000)+0x40000] |= (m_cg_reg[4] & 1) ? (data & m_cg_reg[0] & m_cg_reg[6]) : 0;
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}
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if(m_cg_reg[5] & 2) //R
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{
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ram[offset+((cur_bank & 3)*0x2000)+0x44000] &= ~m_cg_reg[6];
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ram[offset+((cur_bank & 3)*0x2000)+0x44000] |= (m_cg_reg[4] & 2) ? (data & m_cg_reg[1] & m_cg_reg[6]) : 0;
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}
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if(m_cg_reg[5] & 4) //G
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{
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ram[offset+((cur_bank & 3)*0x2000)+0x48000] &= ~m_cg_reg[6];
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ram[offset+((cur_bank & 3)*0x2000)+0x48000] |= (m_cg_reg[4] & 4) ? (data & m_cg_reg[2] & m_cg_reg[6]) : 0;
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}
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if(m_cg_reg[5] & 8) //I
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{
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ram[offset+((cur_bank & 3)*0x2000)+0x4c000] &= ~m_cg_reg[6];
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ram[offset+((cur_bank & 3)*0x2000)+0x4c000] |= (m_cg_reg[4] & 8) ? (data & m_cg_reg[3] & m_cg_reg[6]) : 0;
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}
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}
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else if((m_cg_reg[0x05] & 0xc0) == 0x40) //pset
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{
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if(m_cg_reg[5] & 1) //B
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{
|
|
||||||
ram[offset+((cur_bank & 3)*0x2000)+0x40000] &= ~data;
|
|
||||||
ram[offset+((cur_bank & 3)*0x2000)+0x40000] |= (m_cg_reg[4] & 1) ? (data & m_cg_reg[0]) : 0;
|
|
||||||
}
|
|
||||||
if(m_cg_reg[5] & 2) //R
|
|
||||||
{
|
|
||||||
ram[offset+((cur_bank & 3)*0x2000)+0x44000] &= ~data;
|
|
||||||
ram[offset+((cur_bank & 3)*0x2000)+0x44000] |= (m_cg_reg[4] & 2) ? (data & m_cg_reg[1]) : 0;
|
|
||||||
}
|
|
||||||
if(m_cg_reg[5] & 4) //G
|
|
||||||
{
|
|
||||||
ram[offset+((cur_bank & 3)*0x2000)+0x48000] &= ~data;
|
|
||||||
ram[offset+((cur_bank & 3)*0x2000)+0x48000] |= (m_cg_reg[4] & 4) ? (data & m_cg_reg[2]) : 0;
|
|
||||||
}
|
|
||||||
if(m_cg_reg[5] & 8) //I
|
|
||||||
{
|
|
||||||
ram[offset+((cur_bank & 3)*0x2000)+0x4c000] &= ~data;
|
|
||||||
ram[offset+((cur_bank & 3)*0x2000)+0x4c000] |= (m_cg_reg[4] & 8) ? (data & m_cg_reg[3]) : 0;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x34:
|
|
||||||
case 0x35:
|
|
||||||
case 0x36:
|
|
||||||
case 0x37:
|
|
||||||
{
|
|
||||||
// IPL ROM, WRITENOP
|
|
||||||
//printf("%04x %02x\n",offset+bank_num*0x2000,data);
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x38:
|
|
||||||
{
|
|
||||||
// TVRAM
|
|
||||||
ram[offset+cur_bank*0x2000] = data;
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x39:
|
|
||||||
{
|
|
||||||
ram[offset+cur_bank*0x2000] = data;
|
|
||||||
if(m_kanji_bank & 0x80) //kanji ROM
|
|
||||||
{
|
|
||||||
//NOP
|
|
||||||
}
|
|
||||||
else //PCG RAM
|
|
||||||
{
|
|
||||||
m_pcg_ram[offset] = data;
|
|
||||||
if((offset & 0x1800) == 0x0000)
|
|
||||||
m_gfxdecode->gfx(3)->mark_dirty((offset) >> 3);
|
|
||||||
else
|
|
||||||
m_gfxdecode->gfx(4)->mark_dirty((offset & 0x7ff) >> 3);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x3a:
|
|
||||||
{
|
|
||||||
// DIC ROM, WRITENOP
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
case 0x3c:
|
|
||||||
case 0x3d:
|
|
||||||
case 0x3e:
|
|
||||||
case 0x3f:
|
|
||||||
{
|
|
||||||
// PHONE ROM, WRITENOP
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
default: ram[offset+cur_bank*0x2000] = data; break;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
READ8_MEMBER(mz2500_state::bank0_r){ return mz2500_ram_read(offset, 0); }
|
|
||||||
READ8_MEMBER(mz2500_state::bank1_r){ return mz2500_ram_read(offset, 1); }
|
|
||||||
READ8_MEMBER(mz2500_state::bank2_r){ return mz2500_ram_read(offset, 2); }
|
|
||||||
READ8_MEMBER(mz2500_state::bank3_r){ return mz2500_ram_read(offset, 3); }
|
|
||||||
READ8_MEMBER(mz2500_state::bank4_r){ return mz2500_ram_read(offset, 4); }
|
|
||||||
READ8_MEMBER(mz2500_state::bank5_r){ return mz2500_ram_read(offset, 5); }
|
|
||||||
READ8_MEMBER(mz2500_state::bank6_r){ return mz2500_ram_read(offset, 6); }
|
|
||||||
READ8_MEMBER(mz2500_state::bank7_r){ return mz2500_ram_read(offset, 7); }
|
|
||||||
WRITE8_MEMBER(mz2500_state::bank0_w){ mz2500_ram_write(offset, data, 0); }
|
|
||||||
WRITE8_MEMBER(mz2500_state::bank1_w){ mz2500_ram_write(offset, data, 1); }
|
|
||||||
WRITE8_MEMBER(mz2500_state::bank2_w){ mz2500_ram_write(offset, data, 2); }
|
|
||||||
WRITE8_MEMBER(mz2500_state::bank3_w){ mz2500_ram_write(offset, data, 3); }
|
|
||||||
WRITE8_MEMBER(mz2500_state::bank4_w){ mz2500_ram_write(offset, data, 4); }
|
|
||||||
WRITE8_MEMBER(mz2500_state::bank5_w){ mz2500_ram_write(offset, data, 5); }
|
|
||||||
WRITE8_MEMBER(mz2500_state::bank6_w){ mz2500_ram_write(offset, data, 6); }
|
|
||||||
WRITE8_MEMBER(mz2500_state::bank7_w){ mz2500_ram_write(offset, data, 7); }
|
|
||||||
|
|
||||||
|
|
||||||
READ8_MEMBER(mz2500_state::mz2500_bank_addr_r)
|
READ8_MEMBER(mz2500_state::mz2500_bank_addr_r)
|
||||||
{
|
{
|
||||||
return m_bank_addr;
|
return m_bank_addr;
|
||||||
@ -829,9 +622,8 @@ READ8_MEMBER(mz2500_state::mz2500_bank_data_r)
|
|||||||
|
|
||||||
WRITE8_MEMBER(mz2500_state::mz2500_bank_data_w)
|
WRITE8_MEMBER(mz2500_state::mz2500_bank_data_w)
|
||||||
{
|
{
|
||||||
// static const char *const bank_name[] = { "bank0", "bank1", "bank2", "bank3", "bank4", "bank5", "bank6", "bank7" };
|
|
||||||
|
|
||||||
m_bank_val[m_bank_addr] = data & 0x3f;
|
m_bank_val[m_bank_addr] = data & 0x3f;
|
||||||
|
m_rambank[m_bank_addr]->set_bank(m_bank_val[m_bank_addr]);
|
||||||
|
|
||||||
// if((data*2) >= 0x70)
|
// if((data*2) >= 0x70)
|
||||||
// printf("%s %02x\n",bank_name[m_bank_addr],m_bank_val[m_bank_addr]*2);
|
// printf("%s %02x\n",bank_name[m_bank_addr],m_bank_val[m_bank_addr]*2);
|
||||||
@ -1029,19 +821,141 @@ WRITE8_MEMBER(mz2500_state::floppy_side_w)
|
|||||||
m_floppy->ss_w(BIT(data, 0));
|
m_floppy->ss_w(BIT(data, 0));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
void mz2500_state::mz2500_map(address_map &map)
|
void mz2500_state::mz2500_map(address_map &map)
|
||||||
{
|
{
|
||||||
map(0x0000, 0x1fff).rw(FUNC(mz2500_state::bank0_r), FUNC(mz2500_state::bank0_w));
|
map(0x0000, 0x1fff).m(m_rambank[0], FUNC(address_map_bank_device::amap8));
|
||||||
map(0x2000, 0x3fff).rw(FUNC(mz2500_state::bank1_r), FUNC(mz2500_state::bank1_w));
|
map(0x2000, 0x3fff).m(m_rambank[1], FUNC(address_map_bank_device::amap8));
|
||||||
map(0x4000, 0x5fff).rw(FUNC(mz2500_state::bank2_r), FUNC(mz2500_state::bank2_w));
|
map(0x4000, 0x5fff).m(m_rambank[2], FUNC(address_map_bank_device::amap8));
|
||||||
map(0x6000, 0x7fff).rw(FUNC(mz2500_state::bank3_r), FUNC(mz2500_state::bank3_w));
|
map(0x6000, 0x7fff).m(m_rambank[3], FUNC(address_map_bank_device::amap8));
|
||||||
map(0x8000, 0x9fff).rw(FUNC(mz2500_state::bank4_r), FUNC(mz2500_state::bank4_w));
|
map(0x8000, 0x9fff).m(m_rambank[4], FUNC(address_map_bank_device::amap8));
|
||||||
map(0xa000, 0xbfff).rw(FUNC(mz2500_state::bank5_r), FUNC(mz2500_state::bank5_w));
|
map(0xa000, 0xbfff).m(m_rambank[5], FUNC(address_map_bank_device::amap8));
|
||||||
map(0xc000, 0xdfff).rw(FUNC(mz2500_state::bank6_r), FUNC(mz2500_state::bank6_w));
|
map(0xc000, 0xdfff).m(m_rambank[6], FUNC(address_map_bank_device::amap8));
|
||||||
map(0xe000, 0xffff).rw(FUNC(mz2500_state::bank7_r), FUNC(mz2500_state::bank7_w));
|
map(0xe000, 0xffff).m(m_rambank[7], FUNC(address_map_bank_device::amap8));
|
||||||
}
|
}
|
||||||
|
|
||||||
|
READ8_MEMBER(mz2500_state::rmw_r)
|
||||||
|
{
|
||||||
|
// TODO: correct?
|
||||||
|
if(m_cg_reg[0x0e] == 0x3)
|
||||||
|
return 0xff;
|
||||||
|
|
||||||
|
int plane;
|
||||||
|
m_cg_latch[0] = m_cgram[offset+0x0000]; //B
|
||||||
|
m_cg_latch[1] = m_cgram[offset+0x4000]; //R
|
||||||
|
m_cg_latch[2] = m_cgram[offset+0x8000]; //G
|
||||||
|
m_cg_latch[3] = m_cgram[offset+0xc000]; //I
|
||||||
|
plane = m_cg_reg[0x07] & 3;
|
||||||
|
|
||||||
|
if(m_cg_reg[0x07] & 0x10)
|
||||||
|
return mz2500_cg_latch_compare();
|
||||||
|
|
||||||
|
return m_cg_latch[plane];
|
||||||
|
}
|
||||||
|
|
||||||
|
WRITE8_MEMBER(mz2500_state::rmw_w)
|
||||||
|
{
|
||||||
|
// TODO: correct?
|
||||||
|
if(m_cg_reg[0x0e] == 0x3)
|
||||||
|
return;
|
||||||
|
|
||||||
|
if((m_cg_reg[0x05] & 0xc0) == 0x00) //replace
|
||||||
|
{
|
||||||
|
if(m_cg_reg[5] & 1) //B
|
||||||
|
{
|
||||||
|
m_cgram[offset+0x0000] &= ~m_cg_reg[6];
|
||||||
|
m_cgram[offset+0x0000] |= (m_cg_reg[4] & 1) ? (data & m_cg_reg[0] & m_cg_reg[6]) : 0;
|
||||||
|
}
|
||||||
|
if(m_cg_reg[5] & 2) //R
|
||||||
|
{
|
||||||
|
m_cgram[offset+0x4000] &= ~m_cg_reg[6];
|
||||||
|
m_cgram[offset+0x4000] |= (m_cg_reg[4] & 2) ? (data & m_cg_reg[1] & m_cg_reg[6]) : 0;
|
||||||
|
}
|
||||||
|
if(m_cg_reg[5] & 4) //G
|
||||||
|
{
|
||||||
|
m_cgram[offset+0x8000] &= ~m_cg_reg[6];
|
||||||
|
m_cgram[offset+0x8000] |= (m_cg_reg[4] & 4) ? (data & m_cg_reg[2] & m_cg_reg[6]) : 0;
|
||||||
|
}
|
||||||
|
if(m_cg_reg[5] & 8) //I
|
||||||
|
{
|
||||||
|
m_cgram[offset+0xc000] &= ~m_cg_reg[6];
|
||||||
|
m_cgram[offset+0xc000] |= (m_cg_reg[4] & 8) ? (data & m_cg_reg[3] & m_cg_reg[6]) : 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
else if((m_cg_reg[0x05] & 0xc0) == 0x40) //pset
|
||||||
|
{
|
||||||
|
if(m_cg_reg[5] & 1) //B
|
||||||
|
{
|
||||||
|
m_cgram[offset+0x0000] &= ~data;
|
||||||
|
m_cgram[offset+0x0000] |= (m_cg_reg[4] & 1) ? (data & m_cg_reg[0]) : 0;
|
||||||
|
}
|
||||||
|
if(m_cg_reg[5] & 2) //R
|
||||||
|
{
|
||||||
|
m_cgram[offset+0x4000] &= ~data;
|
||||||
|
m_cgram[offset+0x4000] |= (m_cg_reg[4] & 2) ? (data & m_cg_reg[1]) : 0;
|
||||||
|
}
|
||||||
|
if(m_cg_reg[5] & 4) //G
|
||||||
|
{
|
||||||
|
m_cgram[offset+0x8000] &= ~data;
|
||||||
|
m_cgram[offset+0x8000] |= (m_cg_reg[4] & 4) ? (data & m_cg_reg[2]) : 0;
|
||||||
|
}
|
||||||
|
if(m_cg_reg[5] & 8) //I
|
||||||
|
{
|
||||||
|
m_cgram[offset+0xc000] &= ~data;
|
||||||
|
m_cgram[offset+0xc000] |= (m_cg_reg[4] & 8) ? (data & m_cg_reg[3]) : 0;
|
||||||
|
}
|
||||||
|
}
|
||||||
|
}
|
||||||
|
|
||||||
|
READ8_MEMBER(mz2500_state::kanji_pcg_r)
|
||||||
|
{
|
||||||
|
if(m_kanji_bank & 0x80) //kanji ROM
|
||||||
|
return m_kanji_rom[(offset & 0x7ff)+((m_kanji_bank & 0x7f)*0x800)];
|
||||||
|
|
||||||
|
//PCG RAM
|
||||||
|
return m_pcg_ram[offset];
|
||||||
|
}
|
||||||
|
|
||||||
|
WRITE8_MEMBER(mz2500_state::kanji_pcg_w)
|
||||||
|
{
|
||||||
|
if((m_kanji_bank & 0x80) == 0) ////PCG RAM
|
||||||
|
{
|
||||||
|
m_pcg_ram[offset] = data;
|
||||||
|
if((offset & 0x1800) == 0x0000)
|
||||||
|
m_gfxdecode->gfx(3)->mark_dirty((offset) >> 3);
|
||||||
|
else
|
||||||
|
m_gfxdecode->gfx(4)->mark_dirty((offset & 0x7ff) >> 3);
|
||||||
|
}
|
||||||
|
// kanji ROM is read only
|
||||||
|
}
|
||||||
|
|
||||||
|
READ8_MEMBER(mz2500_state::dict_rom_r)
|
||||||
|
{
|
||||||
|
return m_dic_rom[(offset & 0x1fff) + ((m_dic_bank & 0x1f)*0x2000)];
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
memory map:
|
||||||
|
0x00000-0x3ffff Work RAM
|
||||||
|
0x40000-0x5ffff CG RAM
|
||||||
|
0x60000-0x67fff "Read modify write" area (related to the CG RAM) (0x30-0x33)
|
||||||
|
0x68000-0x6ffff IPL ROM (0x34-0x37)
|
||||||
|
0x70000-0x71fff TVRAM (0x38)
|
||||||
|
0x72000-0x73fff Kanji ROM / PCG RAM (banked) (0x39)
|
||||||
|
0x74000-0x75fff Dictionary ROM (banked) (0x3a)
|
||||||
|
0x76000-0x77fff NOP (0x3b)
|
||||||
|
0x78000-0x7ffff Phone ROM (0x3c-0x3f)
|
||||||
|
*/
|
||||||
|
void mz2500_state::mz2500_bank_window_map(address_map &map)
|
||||||
|
{
|
||||||
|
map(0x00000,0x3ffff).ram().share("wram");
|
||||||
|
map(0x40000,0x5ffff).ram().share("cgram");
|
||||||
|
map(0x60000,0x67fff).rw(FUNC(mz2500_state::rmw_r),FUNC(mz2500_state::rmw_w));
|
||||||
|
map(0x68000,0x6ffff).rom().region("ipl", 0);
|
||||||
|
map(0x70000,0x71fff).ram().share("tvram");
|
||||||
|
map(0x72000,0x73fff).rw(FUNC(mz2500_state::kanji_pcg_r),FUNC(mz2500_state::kanji_pcg_w));
|
||||||
|
map(0x74000,0x75fff).r(FUNC(mz2500_state::dict_rom_r));
|
||||||
|
map(0x78000,0x7ffff).rom().region("phone", 0);
|
||||||
|
}
|
||||||
|
|
||||||
READ8_MEMBER(mz2500_state::mz2500_rom_r)
|
READ8_MEMBER(mz2500_state::mz2500_rom_r)
|
||||||
{
|
{
|
||||||
@ -1171,7 +1085,7 @@ WRITE8_MEMBER(mz2500_state::mz2500_cg_data_w)
|
|||||||
if((m_cg_reg_index & 0x1f) == 0x05 && (m_cg_reg[0x05] & 0xc0) == 0x80) //clear bitmap buffer
|
if((m_cg_reg_index & 0x1f) == 0x05 && (m_cg_reg[0x05] & 0xc0) == 0x80) //clear bitmap buffer
|
||||||
{
|
{
|
||||||
uint32_t i;
|
uint32_t i;
|
||||||
uint8_t *vram = m_main_ram.get(); // TODO
|
uint8_t *vram = m_cgram;
|
||||||
uint32_t layer_bank;
|
uint32_t layer_bank;
|
||||||
|
|
||||||
layer_bank = (m_cg_reg[0x0e] & 0x80) ? 0x10000 : 0x00000;
|
layer_bank = (m_cg_reg[0x0e] & 0x80) ? 0x10000 : 0x00000;
|
||||||
@ -1180,22 +1094,22 @@ WRITE8_MEMBER(mz2500_state::mz2500_cg_data_w)
|
|||||||
if(m_cg_reg[0x05] & 1)
|
if(m_cg_reg[0x05] & 1)
|
||||||
{
|
{
|
||||||
for(i=0;i<0x4000;i++)
|
for(i=0;i<0x4000;i++)
|
||||||
vram[i+0x40000+layer_bank] = 0x00; //clear B
|
vram[i+0x0000+layer_bank] = 0x00; //clear B
|
||||||
}
|
}
|
||||||
if(m_cg_reg[0x05] & 2)
|
if(m_cg_reg[0x05] & 2)
|
||||||
{
|
{
|
||||||
for(i=0;i<0x4000;i++)
|
for(i=0;i<0x4000;i++)
|
||||||
vram[i+0x44000+layer_bank] = 0x00; //clear R
|
vram[i+0x4000+layer_bank] = 0x00; //clear R
|
||||||
}
|
}
|
||||||
if(m_cg_reg[0x05] & 4)
|
if(m_cg_reg[0x05] & 4)
|
||||||
{
|
{
|
||||||
for(i=0;i<0x4000;i++)
|
for(i=0;i<0x4000;i++)
|
||||||
vram[i+0x48000+layer_bank] = 0x00; //clear G
|
vram[i+0x8000+layer_bank] = 0x00; //clear G
|
||||||
}
|
}
|
||||||
if(m_cg_reg[0x05] & 8)
|
if(m_cg_reg[0x05] & 8)
|
||||||
{
|
{
|
||||||
for(i=0;i<0x4000;i++)
|
for(i=0;i<0x4000;i++)
|
||||||
vram[i+0x4c000+layer_bank] = 0x00; //clear I
|
vram[i+0xc000+layer_bank] = 0x00; //clear I
|
||||||
}
|
}
|
||||||
m_cg_clear_flag = 1;
|
m_cg_clear_flag = 1;
|
||||||
}
|
}
|
||||||
@ -1535,12 +1449,15 @@ static INPUT_PORTS_START( mz2500 )
|
|||||||
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
|
PORT_BIT( 0x80, IP_ACTIVE_LOW, IPT_UNUSED )
|
||||||
INPUT_PORTS_END
|
INPUT_PORTS_END
|
||||||
|
|
||||||
void mz2500_state::mz2500_reset(mz2500_state *state, uint8_t type)
|
void mz2500_state::reset_banks(uint8_t type)
|
||||||
{
|
{
|
||||||
int i;
|
int i;
|
||||||
|
|
||||||
for(i=0;i<8;i++)
|
for(i=0;i<8;i++)
|
||||||
|
{
|
||||||
m_bank_val[i] = bank_reset_val[type][i];
|
m_bank_val[i] = bank_reset_val[type][i];
|
||||||
|
m_rambank[i]->set_bank(m_bank_val[i]);
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
static const gfx_layout mz2500_pcg_layout_1bpp =
|
static const gfx_layout mz2500_pcg_layout_1bpp =
|
||||||
@ -1567,8 +1484,6 @@ static const gfx_layout mz2500_pcg_layout_3bpp =
|
|||||||
|
|
||||||
void mz2500_state::machine_start()
|
void mz2500_state::machine_start()
|
||||||
{
|
{
|
||||||
/* TODO: main RAM actually needs to be splitted */
|
|
||||||
m_main_ram = make_unique_clear<uint8_t[]>(0x80000);
|
|
||||||
m_pcg_ram = make_unique_clear<uint8_t[]>(0x2000);
|
m_pcg_ram = make_unique_clear<uint8_t[]>(0x2000);
|
||||||
m_ipl_rom = memregion("ipl")->base();
|
m_ipl_rom = memregion("ipl")->base();
|
||||||
m_kanji_rom = memregion("kanji")->base();
|
m_kanji_rom = memregion("kanji")->base();
|
||||||
@ -1578,7 +1493,6 @@ void mz2500_state::machine_start()
|
|||||||
m_phone_rom = memregion("phone")->base();
|
m_phone_rom = memregion("phone")->base();
|
||||||
m_iplpro_rom = memregion("iplpro")->base();
|
m_iplpro_rom = memregion("iplpro")->base();
|
||||||
|
|
||||||
save_pointer(NAME(m_main_ram), 0x80000);
|
|
||||||
save_pointer(NAME(m_pcg_ram), 0x2000);
|
save_pointer(NAME(m_pcg_ram), 0x2000);
|
||||||
save_pointer(NAME(m_emm_ram), 0x100000);
|
save_pointer(NAME(m_emm_ram), 0x100000);
|
||||||
|
|
||||||
@ -1591,23 +1505,16 @@ void mz2500_state::machine_reset()
|
|||||||
{
|
{
|
||||||
uint32_t i;
|
uint32_t i;
|
||||||
|
|
||||||
mz2500_reset(this, IPL_RESET);
|
reset_banks(IPL_RESET);
|
||||||
|
|
||||||
//m_irq_vector[0] = 0xef; /* RST 28h - vblank */
|
//m_irq_vector[0] = 0xef; /* RST 28h - vblank */
|
||||||
|
|
||||||
m_text_col_size = 0;
|
m_text_col_size = 0;
|
||||||
m_text_font_reg = 0;
|
m_text_font_reg = 0;
|
||||||
|
|
||||||
/* copy IPL to its natural bank ROM/RAM position */
|
|
||||||
for(i=0;i<0x8000;i++)
|
|
||||||
{
|
|
||||||
//m_main_ram[i] = IPL[i];
|
|
||||||
m_main_ram[i+0x68000] = m_ipl_rom[i];
|
|
||||||
}
|
|
||||||
|
|
||||||
/* clear CG RAM */
|
/* clear CG RAM */
|
||||||
for(i=0;i<0x20000;i++)
|
for(i=0;i<0x20000;i++)
|
||||||
m_main_ram[i+0x40000] = 0x00;
|
m_cgram[i] = 0x00;
|
||||||
|
|
||||||
/* disable IRQ */
|
/* disable IRQ */
|
||||||
for(i=0;i<4;i++)
|
for(i=0;i<4;i++)
|
||||||
@ -1737,7 +1644,7 @@ WRITE8_MEMBER(mz2500_state::mz2500_portc_w)
|
|||||||
/* work RAM reset */
|
/* work RAM reset */
|
||||||
if((m_old_portc & 0x02) == 0x00 && (data & 0x02))
|
if((m_old_portc & 0x02) == 0x00 && (data & 0x02))
|
||||||
{
|
{
|
||||||
mz2500_reset(this, WRAM_RESET);
|
reset_banks(WRAM_RESET);
|
||||||
/* correct? */
|
/* correct? */
|
||||||
m_maincpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
|
m_maincpu->pulse_input_line(INPUT_LINE_RESET, attotime::zero);
|
||||||
}
|
}
|
||||||
@ -1746,7 +1653,7 @@ WRITE8_MEMBER(mz2500_state::mz2500_portc_w)
|
|||||||
|
|
||||||
/* IPL reset */
|
/* IPL reset */
|
||||||
if((m_old_portc & 0x08) == 0x00 && (data & 0x08))
|
if((m_old_portc & 0x08) == 0x00 && (data & 0x08))
|
||||||
mz2500_reset(this, IPL_RESET);
|
reset_banks(IPL_RESET);
|
||||||
|
|
||||||
m_old_portc = data;
|
m_old_portc = data;
|
||||||
|
|
||||||
@ -1886,6 +1793,14 @@ static void mz2500_floppies(device_slot_interface &device)
|
|||||||
device.option_add("dd", FLOPPY_35_DD);
|
device.option_add("dd", FLOPPY_35_DD);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
#define MCFG_ADDRESS_BANK(tag) \
|
||||||
|
MCFG_DEVICE_ADD(tag, ADDRESS_MAP_BANK, 0) \
|
||||||
|
MCFG_DEVICE_PROGRAM_MAP(mz2500_bank_window_map) \
|
||||||
|
MCFG_ADDRESS_MAP_BANK_ENDIANNESS(ENDIANNESS_LITTLE) \
|
||||||
|
MCFG_ADDRESS_MAP_BANK_DATA_WIDTH(8) \
|
||||||
|
MCFG_ADDRESS_MAP_BANK_ADDR_WIDTH(16+3) \
|
||||||
|
MCFG_ADDRESS_MAP_BANK_STRIDE(0x2000)
|
||||||
|
|
||||||
|
|
||||||
MACHINE_CONFIG_START(mz2500_state::mz2500)
|
MACHINE_CONFIG_START(mz2500_state::mz2500)
|
||||||
/* basic machine hardware */
|
/* basic machine hardware */
|
||||||
@ -1895,6 +1810,15 @@ MACHINE_CONFIG_START(mz2500_state::mz2500)
|
|||||||
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", mz2500_state, mz2500_vbl)
|
MCFG_DEVICE_VBLANK_INT_DRIVER("screen", mz2500_state, mz2500_vbl)
|
||||||
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(mz2500_state,mz2500_irq_ack)
|
MCFG_DEVICE_IRQ_ACKNOWLEDGE_DRIVER(mz2500_state,mz2500_irq_ack)
|
||||||
|
|
||||||
|
MCFG_ADDRESS_BANK("rambank0")
|
||||||
|
MCFG_ADDRESS_BANK("rambank1")
|
||||||
|
MCFG_ADDRESS_BANK("rambank2")
|
||||||
|
MCFG_ADDRESS_BANK("rambank3")
|
||||||
|
MCFG_ADDRESS_BANK("rambank4")
|
||||||
|
MCFG_ADDRESS_BANK("rambank5")
|
||||||
|
MCFG_ADDRESS_BANK("rambank6")
|
||||||
|
MCFG_ADDRESS_BANK("rambank7")
|
||||||
|
|
||||||
MCFG_DEVICE_ADD("i8255_0", I8255, 0)
|
MCFG_DEVICE_ADD("i8255_0", I8255, 0)
|
||||||
MCFG_I8255_IN_PORTA_CB(READ8(*this, mz2500_state, mz2500_porta_r))
|
MCFG_I8255_IN_PORTA_CB(READ8(*this, mz2500_state, mz2500_porta_r))
|
||||||
MCFG_I8255_OUT_PORTA_CB(WRITE8(*this, mz2500_state, mz2500_porta_w))
|
MCFG_I8255_OUT_PORTA_CB(WRITE8(*this, mz2500_state, mz2500_porta_w))
|
||||||
|
@ -20,6 +20,7 @@
|
|||||||
#include "machine/z80pio.h"
|
#include "machine/z80pio.h"
|
||||||
#include "sound/2203intf.h"
|
#include "sound/2203intf.h"
|
||||||
#include "sound/beep.h"
|
#include "sound/beep.h"
|
||||||
|
#include "machine/bankdev.h"
|
||||||
#include "emupal.h"
|
#include "emupal.h"
|
||||||
#include "screen.h"
|
#include "screen.h"
|
||||||
#include "softlist.h"
|
#include "softlist.h"
|
||||||
@ -47,7 +48,11 @@ public:
|
|||||||
m_floppy2(*this, "mb8877a:2"),
|
m_floppy2(*this, "mb8877a:2"),
|
||||||
m_floppy3(*this, "mb8877a:3"),
|
m_floppy3(*this, "mb8877a:3"),
|
||||||
m_floppy(nullptr),
|
m_floppy(nullptr),
|
||||||
m_palette(*this, "palette")
|
m_palette(*this, "palette"),
|
||||||
|
m_rambank(*this, "rambank%u", 0),
|
||||||
|
m_tvram(*this, "tvram"),
|
||||||
|
m_cgram(*this, "cgram"),
|
||||||
|
m_wram(*this, "wram")
|
||||||
{ }
|
{ }
|
||||||
|
|
||||||
required_device<cpu_device> m_maincpu;
|
required_device<cpu_device> m_maincpu;
|
||||||
@ -61,10 +66,13 @@ public:
|
|||||||
required_device<floppy_connector> m_floppy1;
|
required_device<floppy_connector> m_floppy1;
|
||||||
required_device<floppy_connector> m_floppy2;
|
required_device<floppy_connector> m_floppy2;
|
||||||
required_device<floppy_connector> m_floppy3;
|
required_device<floppy_connector> m_floppy3;
|
||||||
|
|
||||||
floppy_image_device *m_floppy;
|
floppy_image_device *m_floppy;
|
||||||
|
required_device<palette_device> m_palette;
|
||||||
|
required_device_array<address_map_bank_device, 8> m_rambank;
|
||||||
|
required_shared_ptr<uint8_t> m_tvram;
|
||||||
|
required_shared_ptr<uint8_t> m_cgram;
|
||||||
|
required_shared_ptr<uint8_t> m_wram;
|
||||||
|
|
||||||
std::unique_ptr<uint8_t[]> m_main_ram;
|
|
||||||
uint8_t *m_ipl_rom;
|
uint8_t *m_ipl_rom;
|
||||||
uint8_t *m_kanji_rom;
|
uint8_t *m_kanji_rom;
|
||||||
uint8_t *m_kanji2_rom;
|
uint8_t *m_kanji2_rom;
|
||||||
@ -119,22 +127,6 @@ public:
|
|||||||
uint8_t m_pio_latchb;
|
uint8_t m_pio_latchb;
|
||||||
uint8_t m_ym_porta;
|
uint8_t m_ym_porta;
|
||||||
uint8_t m_screen_enable;
|
uint8_t m_screen_enable;
|
||||||
DECLARE_READ8_MEMBER(bank0_r);
|
|
||||||
DECLARE_READ8_MEMBER(bank1_r);
|
|
||||||
DECLARE_READ8_MEMBER(bank2_r);
|
|
||||||
DECLARE_READ8_MEMBER(bank3_r);
|
|
||||||
DECLARE_READ8_MEMBER(bank4_r);
|
|
||||||
DECLARE_READ8_MEMBER(bank5_r);
|
|
||||||
DECLARE_READ8_MEMBER(bank6_r);
|
|
||||||
DECLARE_READ8_MEMBER(bank7_r);
|
|
||||||
DECLARE_WRITE8_MEMBER(bank0_w);
|
|
||||||
DECLARE_WRITE8_MEMBER(bank1_w);
|
|
||||||
DECLARE_WRITE8_MEMBER(bank2_w);
|
|
||||||
DECLARE_WRITE8_MEMBER(bank3_w);
|
|
||||||
DECLARE_WRITE8_MEMBER(bank4_w);
|
|
||||||
DECLARE_WRITE8_MEMBER(bank5_w);
|
|
||||||
DECLARE_WRITE8_MEMBER(bank6_w);
|
|
||||||
DECLARE_WRITE8_MEMBER(bank7_w);
|
|
||||||
DECLARE_READ8_MEMBER(mz2500_bank_addr_r);
|
DECLARE_READ8_MEMBER(mz2500_bank_addr_r);
|
||||||
DECLARE_WRITE8_MEMBER(mz2500_bank_addr_w);
|
DECLARE_WRITE8_MEMBER(mz2500_bank_addr_w);
|
||||||
DECLARE_READ8_MEMBER(mz2500_bank_data_r);
|
DECLARE_READ8_MEMBER(mz2500_bank_data_r);
|
||||||
@ -164,9 +156,14 @@ public:
|
|||||||
DECLARE_READ8_MEMBER(mz2500_emm_data_r);
|
DECLARE_READ8_MEMBER(mz2500_emm_data_r);
|
||||||
DECLARE_WRITE8_MEMBER(mz2500_emm_addr_w);
|
DECLARE_WRITE8_MEMBER(mz2500_emm_addr_w);
|
||||||
DECLARE_WRITE8_MEMBER(mz2500_emm_data_w);
|
DECLARE_WRITE8_MEMBER(mz2500_emm_data_w);
|
||||||
|
|
||||||
|
DECLARE_READ8_MEMBER(rmw_r);
|
||||||
|
DECLARE_WRITE8_MEMBER(rmw_w);
|
||||||
|
DECLARE_READ8_MEMBER(kanji_pcg_r);
|
||||||
|
DECLARE_WRITE8_MEMBER(kanji_pcg_w);
|
||||||
|
DECLARE_READ8_MEMBER(dict_rom_r);
|
||||||
|
|
||||||
uint8_t mz2500_cg_latch_compare();
|
uint8_t mz2500_cg_latch_compare();
|
||||||
uint8_t mz2500_ram_read(uint16_t offset, uint8_t bank_num);
|
|
||||||
void mz2500_ram_write(uint16_t offset, uint8_t data, uint8_t bank_num);
|
|
||||||
virtual void machine_start() override;
|
virtual void machine_start() override;
|
||||||
virtual void machine_reset() override;
|
virtual void machine_reset() override;
|
||||||
virtual void video_start() override;
|
virtual void video_start() override;
|
||||||
@ -204,11 +201,12 @@ public:
|
|||||||
void mz2500_draw_pixel(bitmap_ind16 &bitmap,int x,int y,uint16_t pen,uint8_t width,uint8_t height);
|
void mz2500_draw_pixel(bitmap_ind16 &bitmap,int x,int y,uint16_t pen,uint8_t width,uint8_t height);
|
||||||
void mz2500_reconfigure_screen();
|
void mz2500_reconfigure_screen();
|
||||||
uint8_t pal_256_param(int index, int param);
|
uint8_t pal_256_param(int index, int param);
|
||||||
void mz2500_reset(mz2500_state *state, uint8_t type);
|
void reset_banks(uint8_t type);
|
||||||
required_device<palette_device> m_palette;
|
|
||||||
void mz2500(machine_config &config);
|
void mz2500(machine_config &config);
|
||||||
void mz2500_io(address_map &map);
|
void mz2500_io(address_map &map);
|
||||||
void mz2500_map(address_map &map);
|
void mz2500_map(address_map &map);
|
||||||
|
void mz2500_bank_window_map(address_map &map);
|
||||||
};
|
};
|
||||||
|
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user