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t6a84: remove unneeded devcb

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This commit is contained in:
hap 2025-04-10 13:55:49 +02:00
parent 6e595d751f
commit b8f93608a7
4 changed files with 45 additions and 46 deletions
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29
src/devices/cpu/z80/t6a84.cpp
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@ -42,9 +42,6 @@ t6a84_device::t6a84_device(const machine_config &mconfig, device_type type, cons
, m_data_space_config("data", ENDIANNESS_LITTLE, 8, 20, 0, 16, 0)
, m_stack_space_config("stack", ENDIANNESS_LITTLE, 8, 20, 0, 16, 0)
, m_io_space_config("io", ENDIANNESS_LITTLE, 8, 16, 0, io_map)
, m_branch_cb(*this)
, m_irqfetch_cb(*this)
, m_reti_cb(*this)
, m_code_page(0)
, m_delay_code_page(0)
, m_is_delay_code_page_set(false)
@ -53,20 +50,26 @@ t6a84_device::t6a84_device(const machine_config &mconfig, device_type type, cons
, m_stack_page(8)
, m_vector_page(0)
{
// Interrupt vectors need to be fetched and executed from their corresponding page.
// For simplicity, we switch pages via callbacks, instead of using a dedicated address space.
// TODO: Find a better way to solve this, at least these hacks are isolated to t6a84.cpp for now.
irqfetch_cb().set([this](int state) {
}
// Interrupt vectors need to be fetched and executed from their corresponding page.
// For simplicity, we switch pages via callbacks, instead of using a dedicated address space.
// TODO: Find a better way to solve this, at least these hacks are isolated to t6a84.cpp for now.
void t6a84_device::paged_irqfetch()
{
LOGMASKED(LOG_PAGE_W, "IRQ FETCH %02x => %02x\n", m_code_page, m_vector_page);
m_prev_code_page = m_code_page;
m_code_page = m_vector_page;
});
reti_cb().set([this](int state) {
}
void t6a84_device::paged_reti()
{
LOGMASKED(LOG_PAGE_W, "IRQ RET %02x => %02x\n", m_code_page, m_prev_code_page);
m_code_page = m_prev_code_page;
});
branch_cb().set([this](int state) {
LOGMASKED(LOG_PAGE_W, "BRANCH %02x => %02x\n", m_code_page, m_prev_code_page);
}
void t6a84_device::paged_jump()
{
/*
When setting a code page, it only becomes effective after jumping to a far address in that page.
Any instructions fetched and executed before that jump still use the previous code page.
@ -78,10 +81,10 @@ t6a84_device::t6a84_device(const machine_config &mconfig, device_type type, cons
ROM_00::1ead c3 00 00 JP RST0
*/
if (!machine().side_effects_disabled() && m_is_delay_code_page_set) {
LOGMASKED(LOG_PAGE_W, "BRANCH %02x => %02x\n", m_code_page, m_prev_code_page);
m_code_page = m_delay_code_page;
m_is_delay_code_page_set = false;
}
});
}
void t6a84_device::execute_run()

12
src/devices/cpu/z80/t6a84.h
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@ -40,10 +40,6 @@ public:
uint32_t data_address(uint16_t address);
uint32_t stack_address(uint16_t address);
auto branch_cb() { return m_branch_cb.bind(); }
auto irqfetch_cb() { return m_irqfetch_cb.bind(); }
auto reti_cb() { return m_reti_cb.bind(); }
protected:
t6a84_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock, address_map_constructor io_map);
@ -67,6 +63,10 @@ protected:
void stack_page_w(uint8_t page);
void vector_page_w(uint8_t page);
void paged_irqfetch();
void paged_reti();
void paged_jump();
void internal_io_map(address_map &map) const;
virtual space_config_vector memory_space_config() const override;
virtual bool memory_translate(int spacenum, int intention, offs_t &address, address_space *&target_space) override;
@ -78,10 +78,6 @@ protected:
memory_access<16, 0, 0, ENDIANNESS_LITTLE>::specific m_stack;
devcb_write_line m_branch_cb;
devcb_write_line m_irqfetch_cb;
devcb_write_line m_reti_cb;
private:
uint8_t m_code_page;
uint8_t m_delay_code_page;

10
src/devices/cpu/z80/z80.lst
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@ -91,7 +91,7 @@ macro jp
macro t6a84:jp
call arg16
PC = TDAT; WZ = PC;
m_branch_cb(1);
paged_jump();
macro jp_cond
if (TDAT8) {
@ -107,7 +107,7 @@ macro t6a84:jp_cond
if (TDAT8) {
call arg16
PC = TDAT; WZ = PC;
m_branch_cb(1);
paged_jump();
} else {
// implicit do PC += 2
call arg16
@ -125,7 +125,7 @@ macro t6a84:jr
TADR = PC-1;
5 * call nomreq_addr
PC += (s8)TDAT8; WZ = PC;
m_branch_cb(1);
paged_jump();
macro r800:jr
call arg
@ -194,7 +194,7 @@ macro reti
macro t6a84:reti
call pop
PC = TDAT; WZ = PC; m_iff1 = m_iff2;
m_reti_cb(1);
paged_reti();
daisy_call_reti_device();
macro ld_r_a
@ -566,7 +566,7 @@ macro irqfetch
macro t6a84:irqfetch
{
// fetch the IRQ vector
m_irqfetch_cb(1);
paged_irqfetch();
device_z80daisy_interface *intf = daisy_get_irq_device();
m_tmp_irq_vector = (intf != nullptr) ? intf->z80daisy_irq_ack() : standard_irq_callback(0, m_pc.w);
LOGMASKED(LOG_INT, "single INT m_tmp_irq_vector $%02x\n", m_tmp_irq_vector);

4
src/mame/saitek/prisma.cpp
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@ -10,8 +10,8 @@ NVRAM won't save properly. To force a cold boot, hold the PLAY button and trigge
a power on/reset (F3).
It's the 'sequel' to Simultano, and the first chess computer with a H8 CPU. Even
though H8 is much faster than 6502, it plays weaker, probably due to less RAM.
And/or it could also be due to the programmer(s) being unfamiliar with H8.
though H8 is much faster than 6502, it plays weaker than Simultano, probably due to
less RAM. And/or it could also be due to the programmer(s) unfamiliarity with H8.
Hardware notes:
- PCB label: ST9A-PE-001