mirror of
https://github.com/holub/mame
synced 2025-10-06 17:08:28 +03:00
Optimized netlist proxies. Small but measurable performance increase for pongf and Pong Doubles. In addition, moved some code between classes and sorted code in nl_base.c
This commit is contained in:
parent
9e57e262c6
commit
b94047212b
@ -116,11 +116,11 @@ NETLIB_START(QBJT_switch)
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NETLIB_UPDATE(QBJT_switch)
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NETLIB_UPDATE(QBJT_switch)
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{
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{
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if (!m_RB.m_P.net().isRailNet())
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if (!m_RB.m_P.net().isRailNet())
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m_RB.m_P.net().as_analog().schedule_solve(); // Basis
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m_RB.m_P.schedule_solve(); // Basis
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else if (!m_RB.m_N.net().isRailNet())
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else if (!m_RB.m_N.net().isRailNet())
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m_RB.m_N.net().as_analog().schedule_solve(); // Emitter
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m_RB.m_N.schedule_solve(); // Emitter
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else if (!m_RC.m_P.net().isRailNet())
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else if (!m_RC.m_P.net().isRailNet())
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m_RC.m_P.net().as_analog().schedule_solve(); // Collector
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m_RC.m_P.schedule_solve(); // Collector
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}
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}
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@ -176,11 +176,11 @@ NETLIB_START(QBJT_EB)
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NETLIB_UPDATE(QBJT_EB)
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NETLIB_UPDATE(QBJT_EB)
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{
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{
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if (!m_D_EB.m_P.net().isRailNet())
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if (!m_D_EB.m_P.net().isRailNet())
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m_D_EB.m_P.net().as_analog().schedule_solve(); // Basis
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m_D_EB.m_P.schedule_solve(); // Basis
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else if (!m_D_EB.m_N.net().isRailNet())
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else if (!m_D_EB.m_N.net().isRailNet())
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m_D_EB.m_N.net().as_analog().schedule_solve(); // Emitter
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m_D_EB.m_N.schedule_solve(); // Emitter
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else
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else
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m_D_CB.m_N.net().as_analog().schedule_solve(); // Collector
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m_D_CB.m_N.schedule_solve(); // Collector
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}
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}
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NETLIB_RESET(QBJT_EB)
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NETLIB_RESET(QBJT_EB)
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@ -63,13 +63,13 @@ NETLIB_UPDATE(VCCS)
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/* only called if connected to a rail net ==> notify the solver to recalculate */
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/* only called if connected to a rail net ==> notify the solver to recalculate */
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/* Big FIXME ... */
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/* Big FIXME ... */
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if (!m_IP.net().isRailNet())
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if (!m_IP.net().isRailNet())
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m_IP.net().as_analog().schedule_solve();
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m_IP.schedule_solve();
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else if (!m_IN.net().isRailNet())
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else if (!m_IN.net().isRailNet())
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m_IN.net().as_analog().schedule_solve();
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m_IN.schedule_solve();
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else if (!m_OP.net().isRailNet())
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else if (!m_OP.net().isRailNet())
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m_OP.net().as_analog().schedule_solve();
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m_OP.schedule_solve();
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else if (!m_ON.net().isRailNet())
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else if (!m_ON.net().isRailNet())
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m_ON.net().as_analog().schedule_solve();
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m_ON.schedule_solve();
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}
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}
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// ----------------------------------------------------------------------------------------
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// ----------------------------------------------------------------------------------------
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@ -205,6 +205,10 @@ public:
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ATTR_HOT inline bool is_timestep() { return m_step_devices.count() > 0; }
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ATTR_HOT inline bool is_timestep() { return m_step_devices.count() > 0; }
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ATTR_HOT void update_forced();
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ATTR_HOT void update_forced();
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ATTR_HOT inline void update_after(const netlist_time after)
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{
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m_Q_sync.net().reschedule_in_queue(after);
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}
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/* netdevice functions */
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/* netdevice functions */
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ATTR_HOT virtual void update();
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ATTR_HOT virtual void update();
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@ -60,9 +60,9 @@ NETLIB_UPDATE(twoterm)
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/* only called if connected to a rail net ==> notify the solver to recalculate */
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/* only called if connected to a rail net ==> notify the solver to recalculate */
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/* we only need to call the non-rail terminal */
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/* we only need to call the non-rail terminal */
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if (!m_P.net().isRailNet())
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if (!m_P.net().isRailNet())
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m_P.net().as_analog().schedule_solve();
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m_P.schedule_solve();
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else
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else
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m_N.net().as_analog().schedule_solve();
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m_N.schedule_solve();
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}
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}
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// ----------------------------------------------------------------------------------------
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// ----------------------------------------------------------------------------------------
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@ -87,12 +87,51 @@ NETLIB_UPDATE_PARAM(analog_input)
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// nld_d_to_a_proxy
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// nld_d_to_a_proxy
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// ----------------------------------------------------------------------------------------
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// ----------------------------------------------------------------------------------------
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ATTR_COLD void nld_d_to_a_proxy::start()
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{
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nld_base_d_to_a_proxy::start();
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register_sub(m_RV, "RV");
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register_terminal("1", m_RV.m_P);
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register_terminal("2", m_RV.m_N);
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register_output("_Q", m_Q);
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register_subalias("Q", m_RV.m_P);
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connect(m_RV.m_N, m_Q);
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m_Q.initial(0.0);
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}
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ATTR_COLD void nld_d_to_a_proxy::reset()
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{
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m_RV.do_reset();
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}
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ATTR_COLD netlist_core_terminal_t &nld_d_to_a_proxy::out()
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{
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return m_RV.m_P;
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}
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ATTR_HOT ATTR_ALIGN void nld_d_to_a_proxy::update()
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ATTR_HOT ATTR_ALIGN void nld_d_to_a_proxy::update()
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{
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{
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double R = INPLOGIC(m_I) ? m_family_desc->m_R_high : m_family_desc->m_R_low;
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const int state = INPLOGIC(m_I);
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double V = INPLOGIC(m_I) ? m_family_desc->m_high_V : m_family_desc->m_low_V;
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if (state != m_last_state)
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{
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m_last_state = state;
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const double R = state ? m_family_desc->m_R_high : m_family_desc->m_R_low;
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const double V = state ? m_family_desc->m_high_V : m_family_desc->m_low_V;
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m_R.update_dev();
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// We only need to update the net first if this is a time stepping net
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OUTANALOG(m_Q, V);
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if (m_RV.m_P.net().as_analog().solver()->is_timestep())
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m_R.set_R(R);
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{
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m_RV.update_dev();
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m_RV.set(1.0 / R, V, 0.0);
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m_RV.m_P.schedule_after(NLTIME_FROM_NS(1));
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}
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else
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{
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m_RV.set(1.0 / R, V, 0.0);
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m_RV.update_dev();
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}
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}
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}
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}
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@ -225,39 +225,27 @@ class nld_d_to_a_proxy : public nld_base_d_to_a_proxy
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{
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{
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public:
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public:
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ATTR_COLD nld_d_to_a_proxy(netlist_output_t &out_proxied)
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ATTR_COLD nld_d_to_a_proxy(netlist_output_t &out_proxied)
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: nld_base_d_to_a_proxy(out_proxied)
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: nld_base_d_to_a_proxy(out_proxied)
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, m_RV(TWOTERM)
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, m_last_state(-1)
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{
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{
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}
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}
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ATTR_COLD virtual ~nld_d_to_a_proxy() {}
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ATTR_COLD virtual ~nld_d_to_a_proxy() {}
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protected:
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protected:
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ATTR_COLD void start()
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ATTR_COLD virtual void start();
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{
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nld_base_d_to_a_proxy::start();
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register_sub(m_R, "R");
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ATTR_COLD virtual void reset();
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register_output("_Q", m_Q);
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register_subalias("Q", m_R.m_P);
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connect(m_R.m_N, m_Q);
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ATTR_COLD virtual netlist_core_terminal_t &out();
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}
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ATTR_COLD void reset()
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{
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m_R.do_reset();
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}
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ATTR_COLD virtual netlist_core_terminal_t &out()
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{
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return m_R.m_P;
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}
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ATTR_HOT ATTR_ALIGN void update();
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ATTR_HOT ATTR_ALIGN void update();
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private:
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private:
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netlist_analog_output_t m_Q;
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netlist_analog_output_t m_Q;
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nld_R_base m_R;
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nld_twoterm m_RV;
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int m_last_state;
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};
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};
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#endif
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#endif
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@ -356,7 +356,7 @@ ATTR_HOT ATTR_ALIGN const netlist_sig_t netlist_core_device_t::INPLOGIC_PASSIVE(
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// ----------------------------------------------------------------------------------------
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// ----------------------------------------------------------------------------------------
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// net_device_t
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// netlist_device_t
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// ----------------------------------------------------------------------------------------
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// ----------------------------------------------------------------------------------------
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netlist_device_t::netlist_device_t()
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netlist_device_t::netlist_device_t()
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@ -448,7 +448,7 @@ template ATTR_COLD void netlist_device_t::register_param(const pstring &sname, n
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// ----------------------------------------------------------------------------------------
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// ----------------------------------------------------------------------------------------
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// net_net_t
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// netlist_net_t
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// ----------------------------------------------------------------------------------------
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// ----------------------------------------------------------------------------------------
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ATTR_COLD netlist_net_t::netlist_net_t(const family_t afamily)
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ATTR_COLD netlist_net_t::netlist_net_t(const family_t afamily)
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@ -471,19 +471,11 @@ ATTR_COLD netlist_net_t::~netlist_net_t()
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netlist().remove_save_items(this);
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netlist().remove_save_items(this);
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}
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}
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ATTR_COLD netlist_analog_net_t::netlist_analog_net_t()
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ATTR_COLD void netlist_net_t::init_object(netlist_base_t &nl, const pstring &aname)
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: netlist_net_t(ANALOG)
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, m_DD_n_m_1(0.0)
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, m_h_n_m_1(1e-6)
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, m_solver(NULL)
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{
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{
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};
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netlist_object_t::init_object(nl, aname);
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nl.m_nets.add(this);
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ATTR_COLD netlist_logic_net_t::netlist_logic_net_t()
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}
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: netlist_net_t(LOGIC)
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{
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};
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ATTR_HOT void netlist_net_t::inc_active(netlist_core_terminal_t &term)
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ATTR_HOT void netlist_net_t::inc_active(netlist_core_terminal_t &term)
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{
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{
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@ -530,6 +522,12 @@ ATTR_HOT void netlist_net_t::dec_active(netlist_core_terminal_t &term)
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}
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}
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}
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}
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ATTR_COLD void netlist_net_t::register_railterminal(netlist_output_t &mr)
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{
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assert(m_railterminal == NULL);
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m_railterminal = &mr;
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}
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ATTR_COLD void netlist_net_t::rebuild_list()
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ATTR_COLD void netlist_net_t::rebuild_list()
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{
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{
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/* rebuild m_list */
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/* rebuild m_list */
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@ -540,6 +538,64 @@ ATTR_COLD void netlist_net_t::rebuild_list()
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m_list_active.add(*m_core_terms[i]);
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m_list_active.add(*m_core_terms[i]);
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}
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}
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ATTR_COLD void netlist_net_t::save_register()
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{
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save(NAME(m_time));
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save(NAME(m_active));
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save(NAME(m_in_queue));
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save(NAME(m_last_Analog));
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save(NAME(m_cur_Analog));
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save(NAME(m_last_Q));
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save(NAME(m_cur_Q));
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save(NAME(m_new_Q));
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netlist_object_t::save_register();
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}
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ATTR_HOT ATTR_ALIGN static inline void update_dev(const netlist_core_terminal_t *inp, const UINT32 mask)
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{
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if ((inp->state() & mask) != 0)
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{
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netlist_core_device_t &netdev = inp->netdev();
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begin_timing(netdev.total_time);
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inc_stat(netdev.stat_count);
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netdev.update_dev();
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end_timing(netdev().total_time);
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}
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}
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ATTR_HOT ATTR_ALIGN inline void netlist_net_t::update_devs()
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{
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//assert(m_num_cons != 0);
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assert(this->isRailNet());
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const UINT32 masks[4] = { 1, 5, 3, 1 };
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const UINT32 mask = masks[ (m_last_Q << 1) | m_new_Q ];
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netlist_core_terminal_t *p = m_list_active.first();
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m_in_queue = 2; /* mark as taken ... */
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m_cur_Q = m_new_Q;
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switch (m_active)
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{
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case 2:
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update_dev(p, mask);
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p = m_list_active.next(p);
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if (p == NULL) break;
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case 1:
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update_dev(p, mask);
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break;
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default:
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while (p != NULL)
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{
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update_dev(p, mask);
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p = m_list_active.next(p);
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}
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break;
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}
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m_last_Q = m_cur_Q;
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m_last_Analog = m_cur_Analog;
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}
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ATTR_COLD void netlist_net_t::reset()
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ATTR_COLD void netlist_net_t::reset()
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{
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{
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m_time = netlist_time::zero;
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m_time = netlist_time::zero;
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@ -566,51 +622,24 @@ ATTR_COLD void netlist_net_t::reset()
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m_active++;
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m_active++;
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}
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}
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ATTR_COLD void netlist_logic_net_t::reset()
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ATTR_COLD void netlist_net_t::register_con(netlist_core_terminal_t &terminal)
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{
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{
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netlist_net_t::reset();
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terminal.set_net(*this);
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m_core_terms.add(&terminal);
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if (terminal.state() != netlist_input_t::STATE_INP_PASSIVE)
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m_active++;
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}
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}
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ATTR_COLD void netlist_analog_net_t::reset()
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ATTR_COLD void netlist_net_t::move_connections(netlist_net_t *dest_net)
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{
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{
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netlist_net_t::reset();
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for (int i = 0; i < m_core_terms.count(); i++)
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}
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{
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netlist_core_terminal_t *p = m_core_terms[i];
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ATTR_COLD void netlist_net_t::init_object(netlist_base_t &nl, const pstring &aname)
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dest_net->register_con(*p);
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{
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}
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netlist_object_t::init_object(nl, aname);
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m_core_terms.clear(); // FIXME: othernet needs to be free'd from memory
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nl.m_nets.add(this);
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}
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ATTR_COLD void netlist_net_t::save_register()
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{
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save(NAME(m_time));
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save(NAME(m_active));
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save(NAME(m_in_queue));
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save(NAME(m_last_Analog));
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save(NAME(m_cur_Analog));
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save(NAME(m_last_Q));
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save(NAME(m_cur_Q));
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save(NAME(m_new_Q));
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netlist_object_t::save_register();
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}
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ATTR_COLD void netlist_analog_net_t::save_register()
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{
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save(NAME(m_DD_n_m_1));
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save(NAME(m_h_n_m_1));
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netlist_net_t::save_register();
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}
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ATTR_COLD void netlist_logic_net_t::save_register()
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{
|
|
||||||
netlist_net_t::save_register();
|
|
||||||
}
|
|
||||||
|
|
||||||
ATTR_COLD void netlist_net_t::register_railterminal(netlist_output_t &mr)
|
|
||||||
{
|
|
||||||
assert(m_railterminal == NULL);
|
|
||||||
m_railterminal = &mr;
|
|
||||||
}
|
}
|
||||||
|
|
||||||
ATTR_COLD void netlist_net_t::merge_net(netlist_net_t *othernet)
|
ATTR_COLD void netlist_net_t::merge_net(netlist_net_t *othernet)
|
||||||
@ -639,14 +668,48 @@ ATTR_COLD void netlist_net_t::merge_net(netlist_net_t *othernet)
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
ATTR_COLD void netlist_net_t::move_connections(netlist_net_t *dest_net)
|
// ----------------------------------------------------------------------------------------
|
||||||
|
// netlist_logic_net_t
|
||||||
|
// ----------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
ATTR_COLD netlist_logic_net_t::netlist_logic_net_t()
|
||||||
|
: netlist_net_t(LOGIC)
|
||||||
{
|
{
|
||||||
for (int i = 0; i < m_core_terms.count(); i++)
|
};
|
||||||
{
|
|
||||||
netlist_core_terminal_t *p = m_core_terms[i];
|
|
||||||
dest_net->register_con(*p);
|
ATTR_COLD void netlist_logic_net_t::reset()
|
||||||
}
|
{
|
||||||
m_core_terms.clear(); // FIXME: othernet needs to be free'd from memory
|
netlist_net_t::reset();
|
||||||
|
}
|
||||||
|
|
||||||
|
ATTR_COLD void netlist_logic_net_t::save_register()
|
||||||
|
{
|
||||||
|
netlist_net_t::save_register();
|
||||||
|
}
|
||||||
|
|
||||||
|
// ----------------------------------------------------------------------------------------
|
||||||
|
// netlist_analog_net_t
|
||||||
|
// ----------------------------------------------------------------------------------------
|
||||||
|
|
||||||
|
ATTR_COLD netlist_analog_net_t::netlist_analog_net_t()
|
||||||
|
: netlist_net_t(ANALOG)
|
||||||
|
, m_DD_n_m_1(0.0)
|
||||||
|
, m_h_n_m_1(1e-6)
|
||||||
|
, m_solver(NULL)
|
||||||
|
{
|
||||||
|
};
|
||||||
|
|
||||||
|
ATTR_COLD void netlist_analog_net_t::reset()
|
||||||
|
{
|
||||||
|
netlist_net_t::reset();
|
||||||
|
}
|
||||||
|
|
||||||
|
ATTR_COLD void netlist_analog_net_t::save_register()
|
||||||
|
{
|
||||||
|
save(NAME(m_DD_n_m_1));
|
||||||
|
save(NAME(m_h_n_m_1));
|
||||||
|
netlist_net_t::save_register();
|
||||||
}
|
}
|
||||||
|
|
||||||
ATTR_COLD bool netlist_analog_net_t::already_processed(list_t *groups, int cur_group)
|
ATTR_COLD bool netlist_analog_net_t::already_processed(list_t *groups, int cur_group)
|
||||||
@ -684,70 +747,8 @@ ATTR_COLD void netlist_analog_net_t::process_net(list_t *groups, int &cur_group)
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
ATTR_COLD void netlist_net_t::register_con(netlist_core_terminal_t &terminal)
|
|
||||||
{
|
|
||||||
terminal.set_net(*this);
|
|
||||||
|
|
||||||
m_core_terms.add(&terminal);
|
|
||||||
|
|
||||||
if (terminal.state() != netlist_input_t::STATE_INP_PASSIVE)
|
|
||||||
m_active++;
|
|
||||||
}
|
|
||||||
|
|
||||||
ATTR_HOT ATTR_ALIGN static inline void update_dev(const netlist_core_terminal_t *inp, const UINT32 mask)
|
|
||||||
{
|
|
||||||
if ((inp->state() & mask) != 0)
|
|
||||||
{
|
|
||||||
netlist_core_device_t &netdev = inp->netdev();
|
|
||||||
begin_timing(netdev.total_time);
|
|
||||||
inc_stat(netdev.stat_count);
|
|
||||||
netdev.update_dev();
|
|
||||||
end_timing(netdev().total_time);
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
ATTR_HOT ATTR_ALIGN inline void netlist_net_t::update_devs()
|
|
||||||
{
|
|
||||||
//assert(m_num_cons != 0);
|
|
||||||
assert(this->isRailNet());
|
|
||||||
|
|
||||||
const UINT32 masks[4] = { 1, 5, 3, 1 };
|
|
||||||
const UINT32 mask = masks[ (m_last_Q << 1) | m_new_Q ];
|
|
||||||
netlist_core_terminal_t *p = m_list_active.first();
|
|
||||||
|
|
||||||
m_in_queue = 2; /* mark as taken ... */
|
|
||||||
m_cur_Q = m_new_Q;
|
|
||||||
|
|
||||||
switch (m_active)
|
|
||||||
{
|
|
||||||
case 2:
|
|
||||||
update_dev(p, mask);
|
|
||||||
p = m_list_active.next(p);
|
|
||||||
if (p == NULL) break;
|
|
||||||
case 1:
|
|
||||||
update_dev(p, mask);
|
|
||||||
break;
|
|
||||||
default:
|
|
||||||
while (p != NULL)
|
|
||||||
{
|
|
||||||
update_dev(p, mask);
|
|
||||||
p = m_list_active.next(p);
|
|
||||||
}
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
m_last_Q = m_cur_Q;
|
|
||||||
m_last_Analog = m_cur_Analog;
|
|
||||||
}
|
|
||||||
|
|
||||||
ATTR_HOT void netlist_analog_net_t::schedule_solve()
|
|
||||||
{
|
|
||||||
if (m_solver != NULL)
|
|
||||||
m_solver->update_forced();
|
|
||||||
}
|
|
||||||
|
|
||||||
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
||||||
// netlist_terminal_t
|
// netlist_core_terminal_t
|
||||||
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
||||||
|
|
||||||
ATTR_COLD netlist_core_terminal_t::netlist_core_terminal_t(const type_t atype, const family_t afamily)
|
ATTR_COLD netlist_core_terminal_t::netlist_core_terminal_t(const type_t atype, const family_t afamily)
|
||||||
@ -759,6 +760,15 @@ ATTR_COLD netlist_core_terminal_t::netlist_core_terminal_t(const type_t atype, c
|
|||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ATTR_COLD void netlist_core_terminal_t::set_net(netlist_net_t &anet)
|
||||||
|
{
|
||||||
|
m_net = &anet;
|
||||||
|
}
|
||||||
|
|
||||||
|
// ----------------------------------------------------------------------------------------
|
||||||
|
// netlist_terminal_t
|
||||||
|
// ----------------------------------------------------------------------------------------
|
||||||
|
|
||||||
ATTR_COLD netlist_terminal_t::netlist_terminal_t()
|
ATTR_COLD netlist_terminal_t::netlist_terminal_t()
|
||||||
: netlist_core_terminal_t(TERMINAL, ANALOG)
|
: netlist_core_terminal_t(TERMINAL, ANALOG)
|
||||||
, m_Idr1(NULL)
|
, m_Idr1(NULL)
|
||||||
@ -768,6 +778,15 @@ ATTR_COLD netlist_terminal_t::netlist_terminal_t()
|
|||||||
{
|
{
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ATTR_HOT void netlist_terminal_t::schedule_solve()
|
||||||
|
{
|
||||||
|
net().as_analog().solver()->update_forced();
|
||||||
|
}
|
||||||
|
|
||||||
|
ATTR_HOT void netlist_terminal_t::schedule_after(const netlist_time &after)
|
||||||
|
{
|
||||||
|
net().as_analog().solver()->update_after(after);
|
||||||
|
}
|
||||||
|
|
||||||
ATTR_COLD void netlist_terminal_t::reset()
|
ATTR_COLD void netlist_terminal_t::reset()
|
||||||
{
|
{
|
||||||
@ -787,11 +806,6 @@ ATTR_COLD void netlist_terminal_t::save_register()
|
|||||||
}
|
}
|
||||||
|
|
||||||
|
|
||||||
ATTR_COLD void netlist_core_terminal_t::set_net(netlist_net_t &anet)
|
|
||||||
{
|
|
||||||
m_net = &anet;
|
|
||||||
}
|
|
||||||
|
|
||||||
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
||||||
// net_input_t
|
// net_input_t
|
||||||
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
||||||
|
@ -296,18 +296,19 @@ public:
|
|||||||
};
|
};
|
||||||
enum family_t {
|
enum family_t {
|
||||||
// Terminal families
|
// Terminal families
|
||||||
LOGIC = 1,
|
LOGIC,
|
||||||
ANALOG = 2,
|
ANALOG,
|
||||||
// Device families
|
// Device families
|
||||||
GENERIC = 3, // <== devices usually fall into this category
|
GENERIC, // <== devices usually fall into this category
|
||||||
RESISTOR = 4, // Resistor
|
TWOTERM, // Generic twoterm ...
|
||||||
CAPACITOR = 5, // Capacitor
|
RESISTOR, // Resistor
|
||||||
DIODE = 6, // Diode
|
CAPACITOR, // Capacitor
|
||||||
BJT_SWITCH = 7, // BJT(Switch)
|
DIODE, // Diode
|
||||||
VCVS = 8, // Voltage controlled voltage source
|
BJT_EB, // BJT(Ebers-Moll)
|
||||||
VCCS = 9, // Voltage controlled current source
|
BJT_SWITCH, // BJT(Switch)
|
||||||
BJT_EB = 10, // BJT(Ebers-Moll)
|
VCVS, // Voltage controlled voltage source
|
||||||
GND = 11, // GND device
|
VCCS, // Voltage controlled current source
|
||||||
|
GND, // GND device
|
||||||
};
|
};
|
||||||
|
|
||||||
ATTR_COLD netlist_object_t(const type_t atype, const family_t afamily);
|
ATTR_COLD netlist_object_t(const type_t atype, const family_t afamily);
|
||||||
@ -458,6 +459,8 @@ public:
|
|||||||
set_ptr(m_gt1, GT);
|
set_ptr(m_gt1, GT);
|
||||||
}
|
}
|
||||||
|
|
||||||
|
ATTR_HOT void schedule_solve();
|
||||||
|
ATTR_HOT void schedule_after(const netlist_time &after);
|
||||||
|
|
||||||
netlist_terminal_t *m_otherterm;
|
netlist_terminal_t *m_otherterm;
|
||||||
|
|
||||||
@ -715,7 +718,7 @@ public:
|
|||||||
return m_cur_Analog;
|
return m_cur_Analog;
|
||||||
}
|
}
|
||||||
|
|
||||||
ATTR_HOT void schedule_solve();
|
ATTR_HOT inline netlist_matrix_solver_t *solver() { return m_solver; }
|
||||||
|
|
||||||
ATTR_COLD bool already_processed(list_t *groups, int cur_group);
|
ATTR_COLD bool already_processed(list_t *groups, int cur_group);
|
||||||
ATTR_COLD void process_net(list_t *groups, int &cur_group);
|
ATTR_COLD void process_net(list_t *groups, int &cur_group);
|
||||||
@ -734,8 +737,6 @@ public:
|
|||||||
|
|
||||||
//FIXME: needed by current solver code
|
//FIXME: needed by current solver code
|
||||||
netlist_matrix_solver_t *m_solver;
|
netlist_matrix_solver_t *m_solver;
|
||||||
// netlist_terminal_t::list_t m_terms;
|
|
||||||
// netlist_terminal_t::list_t m_rails;
|
|
||||||
};
|
};
|
||||||
|
|
||||||
// ----------------------------------------------------------------------------------------
|
// ----------------------------------------------------------------------------------------
|
||||||
@ -964,7 +965,12 @@ public:
|
|||||||
out.set_Q(val, delay);
|
out.set_Q(val, delay);
|
||||||
}
|
}
|
||||||
|
|
||||||
ATTR_HOT inline bool INP_HL(const netlist_logic_input_t &inp) const
|
ATTR_HOT inline bool INP_CHANGED(const netlist_logic_input_t &inp) const
|
||||||
|
{
|
||||||
|
return (inp.last_Q() != inp.Q());
|
||||||
|
}
|
||||||
|
|
||||||
|
ATTR_HOT inline bool INP_HL(const netlist_logic_input_t &inp) const
|
||||||
{
|
{
|
||||||
return ((inp.last_Q() & !inp.Q()) == 1);
|
return ((inp.last_Q() & !inp.Q()) == 1);
|
||||||
}
|
}
|
||||||
|
Loading…
Reference in New Issue
Block a user