mirror of
https://github.com/holub/mame
synced 2025-05-24 23:05:32 +03:00
SH2DRC: Fixed output register marking errors
Probably not harmful currently, but if the UML core ever gets more aggressive with optimization (e.g. if we spliced in something like LLVM as a code generator) it could've become an issue.
This commit is contained in:
R. Belmont
parent
14f1e90bed
commit
ba1580bf7d
@ -91,7 +91,7 @@ int sh2_describe(void *param, opcode_desc *desc, const opcode_desc *prev)
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return TRUE;
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case 11: // BSR
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desc->regout[1] |= REGFLAG_PR;
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desc->regout[0] |= REGFLAG_PR;
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// (intentional fallthrough - BSR is BRA with the addition of PR = the return address)
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case 10: // BRA
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{
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@ -150,7 +150,7 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc *
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return TRUE;
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case 0x03: // BSRF(Rn);
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desc->regout[1] |= REGFLAG_PR;
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desc->regout[0] |= REGFLAG_PR;
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desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
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desc->targetpc = BRANCH_TARGET_DYNAMIC;
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@ -179,17 +179,17 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 0x27: // MULL(Rm, Rn);
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case 0x37: // MULL(Rm, Rn);
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desc->regin[0] |= REGFLAG_R(Rn) | REGFLAG_R(Rm);
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desc->regout[1] |= REGFLAG_MACL;
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desc->regout[0] |= REGFLAG_MACL;
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desc->cycles = 2;
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return TRUE;
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case 0x08: // CLRT();
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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return TRUE;
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case 0x0a: // STSMACH(Rn);
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desc->regout[0] |= REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_MACH;
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desc->regout[0] |= REGFLAG_MACH;
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return TRUE;
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case 0x0b: // RTS();
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@ -224,25 +224,25 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 0x2f: // MAC_L(Rm, Rn);
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case 0x3f: // MAC_L(Rm, Rn);
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desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
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desc->regout[0] |= REGFLAG_MACL | REGFLAG_MACH;
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desc->cycles = 3;
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return TRUE;
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case 0x12: // STCGBR(Rn);
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desc->regout[0] |= REGFLAG_R(Rn);
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desc->regin[1] |= REGFLAG_GBR;
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desc->regin[0] |= REGFLAG_GBR;
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return TRUE;
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case 0x18: // SETT();
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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return TRUE;
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case 0x19: // DIV0U();
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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return TRUE;
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case 0x1a: // STSMACL(Rn);
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desc->regin[1] |= REGFLAG_MACL;
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desc->regin[0] |= REGFLAG_MACL;
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desc->regout[0] |= REGFLAG_R(Rn);
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return TRUE;
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@ -252,7 +252,7 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 0x22: // STCVBR(Rn);
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desc->regin[0] |= REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_VBR;
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desc->regout[0] |= REGFLAG_VBR;
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return TRUE;
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case 0x23: // BRAF(Rn);
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@ -264,16 +264,16 @@ static int describe_group_0(SH2 *context, opcode_desc *desc, const opcode_desc *
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return TRUE;
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case 0x28: // CLRMAC();
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desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
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desc->regout[0] |= REGFLAG_MACL | REGFLAG_MACH;
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return TRUE;
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case 0x29: // MOVT(Rn);
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desc->regin[1] |= REGFLAG_SR;
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desc->regin[0] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_R(Rn);
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return TRUE;
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case 0x2a: // STSPR(Rn);
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desc->regin[1] |= REGFLAG_PR;
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desc->regin[0] |= REGFLAG_PR;
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desc->regout[0] |= REGFLAG_R(Rn);
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return TRUE;
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@ -319,7 +319,7 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 8: // TST(Rm, Rn);
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case 12: // CMPSTR(Rm, Rn);
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desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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return TRUE;
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case 9: // AND(Rm, Rn);
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@ -332,7 +332,7 @@ static int describe_group_2(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 14: // MULU(Rm, Rn);
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case 15: // MULS(Rm, Rn);
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desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
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desc->regout[0] |= REGFLAG_MACL | REGFLAG_MACH;
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desc->cycles = 2;
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return TRUE;
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}
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@ -350,7 +350,7 @@ static int describe_group_3(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 6: // CMPHI(Rm, Rn);
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case 7: // CMPGT(Rm, Rn);
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desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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return TRUE;
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case 1: // NOP();
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@ -360,13 +360,13 @@ static int describe_group_3(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 4: // DIV1(Rm, Rn);
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desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
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desc->regout[0] |= REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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return TRUE;
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case 5: // DMULU(Rm, Rn);
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case 13: // DMULS(Rm, Rn);
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desc->regin[0] |= REGFLAG_R(Rm) | REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_MACL | REGFLAG_MACH;
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desc->regout[0] |= REGFLAG_MACL | REGFLAG_MACH;
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desc->cycles = 2;
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return TRUE;
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@ -443,12 +443,12 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 0x0a: // LDSMACH(Rn);
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desc->regin[0] |= REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_MACH;
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desc->regout[0] |= REGFLAG_MACH;
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return TRUE;
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case 0x0b: // JSR(Rn);
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desc->regin[0] |= REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_PR;
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desc->regout[0] |= REGFLAG_PR;
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desc->flags |= OPFLAG_IS_UNCONDITIONAL_BRANCH | OPFLAG_END_SEQUENCE;
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desc->targetpc = BRANCH_TARGET_DYNAMIC;
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desc->delayslots = 1;
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@ -456,7 +456,7 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 0x0e: // LDCSR(Rn);
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desc->regin[0] |= REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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desc->flags |= OPFLAG_CAN_EXPOSE_EXTERNAL_INT | OPFLAG_END_SEQUENCE;
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return TRUE;
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@ -482,7 +482,7 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 0x15: // CMPPL(Rn);
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desc->regin[0] |= REGFLAG_R(Rn);
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desc->regin[1] |= REGFLAG_SR;
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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return TRUE;
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case 0x12: // STSMMACL(Rn);
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@ -515,20 +515,20 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 0x1a: // LDSMACL(Rn);
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desc->regin[0] |= REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_MACL;
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desc->regout[0] |= REGFLAG_MACL;
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return TRUE;
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case 0x1b: // TAS(Rn);
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desc->regin[0] |= REGFLAG_R(Rn);
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desc->regin[1] |= REGFLAG_SR;
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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desc->cycles = 4;
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desc->flags |= OPFLAG_READS_MEMORY | OPFLAG_WRITES_MEMORY;
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return TRUE;
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case 0x1e: // LDCGBR(Rn);
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desc->regin[0] |= REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_GBR;
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desc->regout[0] |= REGFLAG_GBR;
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return TRUE;
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case 0x20: // SHAL(Rn);
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@ -576,7 +576,7 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 0x2a: // LDSPR(Rn);
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desc->regin[0] |= REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_PR;
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desc->regout[0] |= REGFLAG_PR;
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return TRUE;
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case 0x2b: // JMP(Rm);
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@ -588,7 +588,7 @@ static int describe_group_4(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 0x2e: // LDCVBR(Rn);
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desc->regin[0] |= REGFLAG_R(Rn);
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desc->regout[1] |= REGFLAG_VBR;
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desc->regout[0] |= REGFLAG_VBR;
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return TRUE;
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case 0x0c: // NOP();
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@ -691,7 +691,7 @@ static int describe_group_8(SH2 *context, opcode_desc *desc, const opcode_desc *
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case 8<< 8: // CMPIM(opcode & 0xff);
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desc->regin[0] |= REGFLAG_R(Rm);
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desc->regin[1] |= REGFLAG_SR;
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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return TRUE;
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case 9<< 8: // BT(opcode & 0xff);
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@ -746,7 +746,7 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc
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case 8<<8: // TSTI(opcode & 0xff);
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desc->regin[0] |= REGFLAG_R(0);
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desc->regin[1] |= REGFLAG_SR;
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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return TRUE;
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case 9<<8: // ANDI(opcode & 0xff);
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@ -762,7 +762,7 @@ static int describe_group_12(SH2 *context, opcode_desc *desc, const opcode_desc
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case 15<<8: // ORM(opcode & 0xff);
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desc->regin[0] |= REGFLAG_R(0);
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desc->regin[1] |= REGFLAG_SR | REGFLAG_GBR;
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desc->regout[1] |= REGFLAG_SR;
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desc->regout[0] |= REGFLAG_SR;
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desc->flags |= OPFLAG_READS_MEMORY;
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return TRUE;
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}
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