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https://github.com/holub/mame
synced 2025-04-25 17:56:43 +03:00
Changed the 8x300 disassembler to use 'std::ostream &' internally
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a9d260cf14
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@ -41,9 +41,8 @@ static inline bool is_src_rot(uint16_t opcode)
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return true;
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}
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CPU_DISASSEMBLE( n8x300 )
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static offs_t internal_disasm_n8x300(cpu_device *device, std::ostream &stream, offs_t pc, const uint8_t *oprom, const uint8_t *opram, int options)
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{
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char tmp[16];
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unsigned startpc = pc;
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uint16_t opcode = (oprom[pc - startpc] << 8) | oprom[pc+1 - startpc];
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uint8_t inst = opcode >> 13;
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@ -53,99 +52,90 @@ CPU_DISASSEMBLE( n8x300 )
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switch (inst)
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{
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case 0x00:
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sprintf(buffer,"MOVE ");
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strcat(buffer,reg_names[SRC]);
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stream << "MOVE " << reg_names[SRC];
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if(is_rot(opcode))
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sprintf(tmp,"(%i),",ROTLEN);
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util::stream_format(stream, "(%i),", ROTLEN);
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else
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sprintf(tmp,",%i,",ROTLEN);
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strcat(buffer,tmp);
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strcat(buffer,reg_names[DST]);
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util::stream_format(stream, ",%i,", ROTLEN);
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stream << reg_names[DST];
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break;
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case 0x01:
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sprintf(buffer,"ADD ");
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strcat(buffer,reg_names[SRC]);
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stream << "ADD " << reg_names[SRC];
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if(is_rot(opcode))
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sprintf(tmp,"(%i),",ROTLEN);
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util::stream_format(stream, "(%i),", ROTLEN);
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else
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sprintf(tmp,",%i,",ROTLEN);
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strcat(buffer,tmp);
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strcat(buffer,reg_names[DST]);
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util::stream_format(stream, ",%i,", ROTLEN);
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stream << reg_names[DST];
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break;
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case 0x02:
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sprintf(buffer,"AND ");
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strcat(buffer,reg_names[SRC]);
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stream << "AND " << reg_names[SRC];
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if(is_rot(opcode))
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sprintf(tmp,"(%i),",ROTLEN);
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util::stream_format(stream, "(%i),", ROTLEN);
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else
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sprintf(tmp,",%i,",ROTLEN);
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strcat(buffer,tmp);
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strcat(buffer,reg_names[DST]);
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util::stream_format(stream, ",%i,", ROTLEN);
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stream << reg_names[DST];
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break;
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case 0x03:
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sprintf(buffer,"XOR ");
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strcat(buffer,reg_names[SRC]);
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stream << "XOR " << reg_names[SRC];
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if(is_rot(opcode))
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sprintf(tmp,"(%i),",ROTLEN);
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util::stream_format(stream, "(%i),", ROTLEN);
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else
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sprintf(tmp,",%i,",ROTLEN);
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strcat(buffer,tmp);
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strcat(buffer,reg_names[DST]);
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util::stream_format(stream, ",%i,", ROTLEN);
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stream << reg_names[DST];
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break;
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case 0x04:
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sprintf(buffer,"XEC ");
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strcat(buffer,reg_names[SRC]);
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stream << "XEC " << reg_names[SRC];
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if(is_src_rot(opcode))
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{
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sprintf(tmp,",%02XH",IMM8);
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strcat(buffer,tmp);
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util::stream_format(stream, ",%02XH", IMM8);
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}
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else
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{
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sprintf(tmp,",%i",ROTLEN);
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strcat(buffer,tmp);
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sprintf(tmp,",%02XH",IMM5);
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strcat(buffer,tmp);
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util::stream_format(stream, ",%i", ROTLEN);
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util::stream_format(stream, ",%02XH", IMM5);
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}
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break;
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case 0x05:
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sprintf(buffer,"NZT ");
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strcat(buffer,reg_names[SRC]);
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stream << "NZT " << reg_names[SRC];
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if(is_src_rot(opcode))
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{
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sprintf(tmp,",%02XH",IMM8);
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strcat(buffer,tmp);
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util::stream_format(stream, ",%02XH", IMM8);
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}
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else
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{
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sprintf(tmp,",%i",ROTLEN);
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strcat(buffer,tmp);
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sprintf(tmp,",%02XH",IMM5);
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strcat(buffer,tmp);
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util::stream_format(stream, ",%i", ROTLEN);
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util::stream_format(stream, ",%02XH", IMM5);
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}
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break;
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case 0x06:
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sprintf(buffer,"XMIT ");
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stream << "XMIT ";
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if(is_src_rot(opcode))
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{
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sprintf(tmp,"%02XH,",IMM8);
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strcat(buffer,tmp);
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strcat(buffer,reg_names[SRC]);
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util::stream_format(stream, "%02XH,", IMM8);
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stream << reg_names[SRC];
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}
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else
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{
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sprintf(tmp,"%02XH,",IMM5);
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strcat(buffer,tmp);
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strcat(buffer,reg_names[SRC]);
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sprintf(tmp,",%i",ROTLEN);
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strcat(buffer,tmp);
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util::stream_format(stream, "%02XH,", IMM5);
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stream << reg_names[SRC];
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util::stream_format(stream, ",%i", ROTLEN);
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}
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break;
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case 0x07:
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sprintf(buffer,"JMP %04XH",opcode & 0x1fff);
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util::stream_format(stream, "JMP %04XH", opcode & 0x1fff);
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break;
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}
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return (pc - startpc);
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}
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CPU_DISASSEMBLE(n8x300)
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{
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std::ostringstream stream;
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offs_t result = internal_disasm_n8x300(device, stream, pc, oprom, opram, options);
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std::string stream_str = stream.str();
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strcpy(buffer, stream_str.c_str());
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return result;
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}
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