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Merge pull request #931 from fulivi/hp9845_dev
Hp9845: hopefully fixed interrupt handling in hp hybrid processor & minor enhancements
This commit is contained in:
R. Belmont
commit
baf3f115d2
@ -7,25 +7,34 @@
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// I searched for a while for any kind of documentation about them but found nothing at all.
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// Some time later I found the mnemonics in the binary dump of assembly development option ROM:
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// CIM & SIM, respectively. From the mnemonic I deduced their function: Clear & Set Interrupt Mask.
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// I think they are basically used to temporarily disable/enable interrupt recognition inside
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// ISRs. This is consistent with their usage in PPU firmware and test ROM. The official EIR &
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// DIR instructions cannot be used while servicing an interrupt because they probably reset
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// the "in ISR" condition of the processor.
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// Using CIM&SIM only makes sense in low-level ISRs because high-level ones can't be interrupted
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// by anyone.
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// Now, I still have some doubts about the "polarity" of interrupt mask. Is interrupt
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// recognition disabled when the mask is cleared or is it the opposite?
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// I'm leaning towards the "no interrupts with mask cleared" interpretation, but I'm not 100%
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// convinced. CIM & SIM at the moment are implemented with this interpretation (see also
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// NO_ISR_WITH_IM_CLEARED macro below).
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// After a few experiments, crashes, etc. here's my opinion on their purpose.
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// When the CPU receives an interrupt, its AEC registers can be in any state so it could
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// be impossible to properly save state, fetch the interrupt vector and start executing the ISR.
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// The solution is having an hidden "interrupt mask" flag that gets set when an interrupt (either
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// low or high priority) is acknowledged and is cleared when the "ret 0,p" instruction that ends
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// the ISR is executed. The effects of having the interrupt mask set are:
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// * No interrupts are recognized
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// * A few essential AEC registers are overridden to establish a "safe" environment to save state
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// and execute ISR (see hp_5061_3001_cpu_device::add_mae).
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// Inside the ISR, CIM & SIM instructions can be used to change the interrupt mask and switch
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// between normal & overridden settings of AEC.
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// As an example of CIM&SIM usage, we can have a look at the keyboard ISR in 9845B PPU processor:
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// * A key is pressed and IRQ 0 is set
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// * Interrupt 0 is recognized, IM is set
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// * R register is used to save program counter in block = 1 (overriding any R36 value)
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// * Vector is fetched and execution begins in block 5 (overriding R33 value)
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// * Registers are saved to RAM (again in overridden block 1)
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// * AEC registers are set to correct value for ISR execution
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// * CIM is used to exit the special behaviour of AEC and to allow high-priority interrupts
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// * Useful ISR processing is done
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// * SIM is used to re-enter special behaviour of AEC and to block any interrupt
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// * State is restored (including all AEC registers)
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// * RET 0,P is executed to end ISR: return program counter is popped off the stack and IM is cleared
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#include "emu.h"
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#include "debugger.h"
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#include "hphybrid.h"
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// Define this to have "IM cleared" == "No interrupt recognition"
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#define NO_ISR_WITH_IM_CLEARED
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enum {
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HPHYBRID_A,
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HPHYBRID_B,
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@ -539,9 +548,11 @@ UINT16 hp_hybrid_cpu_device::execute_one_sub(UINT16 opcode)
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memmove(&m_reg_PA[ 0 ] , &m_reg_PA[ 1 ] , HPHYBRID_INT_LVLS);
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m_pa_changed_func((UINT8)CURRENT_PA);
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}
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BIT_CLR(m_flags, HPHYBRID_IM_BIT);
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tmp = RM(AEC_CASE_C , m_reg_R--) + (opcode & 0x1f);
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BIT_CLR(m_flags, HPHYBRID_IM_BIT);
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} else {
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tmp = RM(AEC_CASE_C , m_reg_R--) + (opcode & 0x1f);
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}
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tmp = RM(AEC_CASE_C , m_reg_R--) + (opcode & 0x1f);
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return BIT(opcode , 5) ? tmp - 0x20 : tmp;
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} else {
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switch (opcode) {
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@ -1483,11 +1494,7 @@ UINT16 hp_5061_3001_cpu_device::execute_no_bpc_ioc(UINT16 opcode)
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// Probably "Clear Interrupt Mask"
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// No idea at all about exec. time: make it 9 cycles
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m_icount -= 9;
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#ifndef NO_ISR_WITH_IM_CLEARED
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BIT_CLR(m_flags, HPHYBRID_IM_BIT);
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#else
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BIT_SET(m_flags, HPHYBRID_IM_BIT);
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#endif
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logerror("hp-5061-3001: CIM, P = %06x flags = %05x\n" , m_genpc , m_flags);
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break;
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@ -1497,11 +1504,7 @@ UINT16 hp_5061_3001_cpu_device::execute_no_bpc_ioc(UINT16 opcode)
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// Probably "Set Interrupt Mask"
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// No idea at all about exec. time: make it 9 cycles
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m_icount -= 9;
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#ifndef NO_ISR_WITH_IM_CLEARED
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BIT_SET(m_flags, HPHYBRID_IM_BIT);
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#else
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BIT_CLR(m_flags, HPHYBRID_IM_BIT);
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#endif
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logerror("hp-5061-3001: SIM, P = %06x flags = %05x\n" , m_genpc , m_flags);
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break;
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@ -1532,51 +1535,63 @@ offs_t hp_5061_3001_cpu_device::disasm_disassemble(char *buffer, offs_t pc, cons
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UINT32 hp_5061_3001_cpu_device::add_mae(aec_cases_t aec_case , UINT16 addr)
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{
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UINT16 bsc_reg;
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bool top_half = BIT(addr , 15) != 0;
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UINT16 bsc_reg;
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bool top_half = BIT(addr , 15) != 0;
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// Detect accesses to top half of base page
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if ((aec_case == AEC_CASE_C || aec_case == AEC_CASE_I) && (addr & 0xfe00) == 0xfe00) {
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aec_case = AEC_CASE_B;
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// Detect accesses to top half of base page
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if ((aec_case == AEC_CASE_C || aec_case == AEC_CASE_I) && (addr & 0xfe00) == 0xfe00) {
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aec_case = AEC_CASE_B;
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}
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switch (aec_case) {
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case AEC_CASE_A:
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if (top_half) {
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bsc_reg = m_reg_aec[ HP_REG_R34_ADDR - HP_REG_R32_ADDR ];
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} else {
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// Block 5 is used when IM bit overrides R33 value
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bsc_reg = BIT(m_flags , HPHYBRID_IM_BIT) ? 5 : m_reg_aec[ HP_REG_R33_ADDR - HP_REG_R32_ADDR ];
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}
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break;
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switch (aec_case) {
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case AEC_CASE_A:
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bsc_reg = top_half ? HP_REG_R34_ADDR : HP_REG_R33_ADDR;
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break;
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case AEC_CASE_B:
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bsc_reg = top_half ? HP_REG_R36_ADDR : HP_REG_R33_ADDR;
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break;
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case AEC_CASE_C:
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bsc_reg = top_half ? HP_REG_R32_ADDR : HP_REG_R35_ADDR;
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break;
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case AEC_CASE_D:
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bsc_reg = top_half ? HP_REG_R32_ADDR : HP_REG_R37_ADDR;
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break;
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case AEC_CASE_I:
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// Behaviour of AEC during interrupt vector fetch is undocumented but it can be guessed from 9845B firmware.
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// Basically in this case the integrated AEC seems to do what the discrete implementation in 9845A does:
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// top half of memory is mapped to block 0 (fixed) and bottom half is mapped according to content of R35
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// (see pg 334 of patent).
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bsc_reg = top_half ? 0 : HP_REG_R35_ADDR;
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break;
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default:
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logerror("hphybrid: aec_case=%d\n" , aec_case);
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return 0;
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}
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UINT16 aec_reg = (bsc_reg != 0) ? (m_reg_aec[ bsc_reg - HP_REG_R32_ADDR ] & BSC_REG_MASK) : 0;
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if (m_forced_bsc_25) {
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aec_reg = (aec_reg & 0xf) | 0x20;
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case AEC_CASE_B:
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if (top_half) {
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// Block 1 is used when IM bit overrides R36 value
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bsc_reg = BIT(m_flags , HPHYBRID_IM_BIT) ? 1 : m_reg_aec[ HP_REG_R36_ADDR - HP_REG_R32_ADDR ];
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} else {
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// Block 5 is used when IM bit overrides R33 value
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bsc_reg = BIT(m_flags , HPHYBRID_IM_BIT) ? 5 : m_reg_aec[ HP_REG_R33_ADDR - HP_REG_R32_ADDR ];
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}
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break;
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return (UINT32)addr | ((UINT32)aec_reg << 16);
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case AEC_CASE_C:
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bsc_reg = top_half ? m_reg_aec[ HP_REG_R32_ADDR - HP_REG_R32_ADDR ] : m_reg_aec[ HP_REG_R35_ADDR - HP_REG_R32_ADDR ];
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break;
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case AEC_CASE_D:
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bsc_reg = top_half ? m_reg_aec[ HP_REG_R32_ADDR - HP_REG_R32_ADDR ] : m_reg_aec[ HP_REG_R37_ADDR - HP_REG_R32_ADDR ];
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break;
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case AEC_CASE_I:
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// Behaviour of AEC during interrupt vector fetch is undocumented but it can be guessed from 9845B firmware.
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// Basically in this case the integrated AEC seems to do what the discrete implementation in 9845A does:
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// top half of memory is mapped to block 0 (fixed) and bottom half is mapped according to content of R35
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// (see pg 334 of patent).
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// I'm beginning to suspect that these values actually come from IM overriding case "C"
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bsc_reg = top_half ? 0 : m_reg_aec[ HP_REG_R35_ADDR - HP_REG_R32_ADDR ];
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break;
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default:
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logerror("hphybrid: aec_case=%d\n" , aec_case);
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return 0;
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}
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UINT16 aec_reg = bsc_reg & BSC_REG_MASK;
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if (m_forced_bsc_25) {
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aec_reg = (aec_reg & 0xf) | 0x20;
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}
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return (UINT32)addr | ((UINT32)aec_reg << 16);
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}
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UINT16 hp_5061_3001_cpu_device::read_non_common_reg(UINT16 addr)
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@ -1655,10 +1670,8 @@ void hp_5061_3001_cpu_device::write_non_common_reg(UINT16 addr , UINT16 v)
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void hp_5061_3001_cpu_device::enter_isr(void)
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{
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// Set interrupt mask when entering an ISR
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#ifndef NO_ISR_WITH_IM_CLEARED
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BIT_SET(m_flags, HPHYBRID_IM_BIT);
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#endif
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// Set interrupt mask when entering an ISR
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BIT_SET(m_flags, HPHYBRID_IM_BIT);
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}
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hp_5061_3011_cpu_device::hp_5061_3011_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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@ -20,8 +20,8 @@
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// - Keyboard
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// - T15 tape drive
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// - Software list to load optional ROMs
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// What's not yet in:
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// - Beeper
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// What's not yet in:
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// - Better naming of tape drive image (it's now "magt", should be "t15")
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// - Better documentation of this file
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// What's wrong:
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@ -34,6 +34,7 @@
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#include "cpu/hphybrid/hphybrid.h"
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#include "machine/hp_taco.h"
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#include "bus/hp_optroms/hp_optrom.h"
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#include "sound/beep.h"
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#define BIT_MASK(n) (1U << (n))
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@ -111,7 +112,9 @@ public:
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m_io_key1(*this , "KEY1"),
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m_io_key2(*this , "KEY2"),
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m_io_key3(*this , "KEY3"),
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m_t15(*this , "t15")
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m_t15(*this , "t15"),
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m_beeper(*this , "beeper"),
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m_beep_timer(*this , "beep_timer")
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{ }
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UINT32 screen_update(screen_device &screen, bitmap_rgb32 &bitmap, const rectangle &cliprect);
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@ -138,6 +141,7 @@ public:
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DECLARE_READ16_MEMBER(kb_scancode_r);
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DECLARE_READ16_MEMBER(kb_status_r);
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DECLARE_WRITE16_MEMBER(kb_irq_clear_w);
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TIMER_DEVICE_CALLBACK_MEMBER(beeper_off);
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DECLARE_WRITE8_MEMBER(pa_w);
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@ -156,6 +160,8 @@ private:
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required_ioport m_io_key2;
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required_ioport m_io_key3;
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required_device<hp_taco_device> m_t15;
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required_device<beep_device> m_beeper;
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required_device<timer_device> m_beep_timer;
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void set_video_mar(UINT16 mar);
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void video_fill_buff(bool buff_idx);
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@ -416,6 +422,8 @@ void hp9845b_state::machine_reset()
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memset(&m_kb_state[ 0 ] , 0 , sizeof(m_kb_state));
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m_kb_scancode = 0x7f;
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m_kb_status = 0;
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m_beeper->set_state(0);
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}
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void hp9845b_state::set_video_mar(UINT16 mar)
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@ -512,7 +520,6 @@ void hp9845b_state::video_render_buff(unsigned video_scanline , unsigned line_in
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UINT8 chargen_byte = m_chargen[ line_in_row | ((unsigned)charcode << 4) ];
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UINT16 pixels;
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// TODO: Handle selection of 2nd chargen
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// TODO: Check if order of bits in "pixels" is ok
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if ((ul_line && BIT(attrs , 3)) ||
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@ -520,8 +527,11 @@ void hp9845b_state::video_render_buff(unsigned video_scanline , unsigned line_in
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pixels = ~0;
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} else if (char_blink && BIT(attrs , 2)) {
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pixels = 0;
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} else if (BIT(attrs , 4)) {
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// Optional character generator ROM not installed, it reads as 1 everywhere
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pixels = 0x7f << 1;
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} else {
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pixels = (UINT16)(chargen_byte & 0x7f) << 2;
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pixels = (UINT16)(chargen_byte & 0x7f) << 1;
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}
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if (BIT(attrs , 1)) {
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@ -1004,7 +1014,17 @@ WRITE16_MEMBER(hp9845b_state::kb_irq_clear_w)
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BIT_CLR(m_kb_status, 0);
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update_irq();
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m_lpu->status_w(0);
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// TODO: beeper start
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if (BIT(data , 15)) {
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// Start beeper
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m_beep_timer->adjust(attotime::from_ticks(64, KEY_SCAN_OSCILLATOR / 512));
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m_beeper->set_state(1);
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}
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}
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TIMER_DEVICE_CALLBACK_MEMBER(hp9845b_state::beeper_off)
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{
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m_beeper->set_state(0);
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}
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WRITE8_MEMBER(hp9845b_state::pa_w)
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@ -1129,21 +1149,39 @@ static MACHINE_CONFIG_START( hp9845b, hp9845b_state )
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// Actual keyboard refresh rate should be KEY_SCAN_OSCILLATOR / 128 (2560 Hz)
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MCFG_TIMER_DRIVER_ADD_PERIODIC("kb_timer" , hp9845b_state , kb_scan , attotime::from_hz(100))
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// Beeper
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MCFG_SPEAKER_STANDARD_MONO("mono")
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MCFG_SOUND_ADD("beeper" , BEEP , KEY_SCAN_OSCILLATOR / 512)
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MCFG_SOUND_ROUTE(ALL_OUTPUTS , "mono" , 1.00)
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MCFG_TIMER_DRIVER_ADD("beep_timer" , hp9845b_state , beeper_off);
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// Tape controller
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MCFG_DEVICE_ADD("t15" , HP_TACO , 4000000)
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MCFG_TACO_IRQ_HANDLER(WRITELINE(hp9845b_state , t15_irq_w))
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MCFG_TACO_FLG_HANDLER(WRITELINE(hp9845b_state , t15_flg_w))
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MCFG_TACO_STS_HANDLER(WRITELINE(hp9845b_state , t15_sts_w))
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// In real machine there were 8 slots for LPU ROMs and 8 slots for PPU ROMs in
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// right-hand side and left-hand side drawers, respectively.
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// Here we do away with the distinction between LPU & PPU ROMs: in the end they
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// are visible to both CPUs at the same addresses.
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// For now we define just a couple of slots..
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MCFG_DEVICE_ADD("drawer1", HP_OPTROM_SLOT, 0)
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MCFG_DEVICE_SLOT_INTERFACE(hp_optrom_slot_device, NULL, false)
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MCFG_DEVICE_ADD("drawer2", HP_OPTROM_SLOT, 0)
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MCFG_DEVICE_SLOT_INTERFACE(hp_optrom_slot_device, NULL, false)
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// In real machine there were 8 slots for LPU ROMs and 8 slots for PPU ROMs in
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// right-hand side and left-hand side drawers, respectively.
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// Here we do away with the distinction between LPU & PPU ROMs: in the end they
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// are visible to both CPUs at the same addresses.
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MCFG_DEVICE_ADD("drawer1", HP_OPTROM_SLOT, 0)
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MCFG_DEVICE_SLOT_INTERFACE(hp_optrom_slot_device, NULL, false)
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MCFG_DEVICE_ADD("drawer2", HP_OPTROM_SLOT, 0)
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MCFG_DEVICE_SLOT_INTERFACE(hp_optrom_slot_device, NULL, false)
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MCFG_DEVICE_ADD("drawer3", HP_OPTROM_SLOT, 0)
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MCFG_DEVICE_SLOT_INTERFACE(hp_optrom_slot_device, NULL, false)
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MCFG_DEVICE_ADD("drawer4", HP_OPTROM_SLOT, 0)
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MCFG_DEVICE_SLOT_INTERFACE(hp_optrom_slot_device, NULL, false)
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MCFG_DEVICE_ADD("drawer5", HP_OPTROM_SLOT, 0)
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MCFG_DEVICE_SLOT_INTERFACE(hp_optrom_slot_device, NULL, false)
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MCFG_DEVICE_ADD("drawer6", HP_OPTROM_SLOT, 0)
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MCFG_DEVICE_SLOT_INTERFACE(hp_optrom_slot_device, NULL, false)
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MCFG_DEVICE_ADD("drawer7", HP_OPTROM_SLOT, 0)
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MCFG_DEVICE_SLOT_INTERFACE(hp_optrom_slot_device, NULL, false)
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MCFG_DEVICE_ADD("drawer8", HP_OPTROM_SLOT, 0)
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MCFG_DEVICE_SLOT_INTERFACE(hp_optrom_slot_device, NULL, false)
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MCFG_SOFTWARE_LIST_ADD("optrom_list", "hp9845b_rom")
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MACHINE_CONFIG_END
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@ -1253,6 +1291,6 @@ COMP( 1978, hp9845a, 0, 0, hp9845a, hp9845, driver_device, 0,
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COMP( 1978, hp9845s, hp9845a, 0, hp9845a, hp9845, driver_device, 0, "Hewlett-Packard", "9845S", MACHINE_IS_SKELETON | MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
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COMP( 1979, hp9835a, 0, 0, hp9835a, hp9845, driver_device, 0, "Hewlett-Packard", "9835A", MACHINE_IS_SKELETON | MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
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COMP( 1979, hp9835b, hp9835a, 0, hp9835a, hp9845, driver_device, 0, "Hewlett-Packard", "9835B", MACHINE_IS_SKELETON | MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
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COMP( 1980, hp9845b, 0, 0, hp9845b, hp9845b,driver_device, 0, "Hewlett-Packard", "9845B", MACHINE_NO_SOUND )
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COMP( 1980, hp9845b, 0, 0, hp9845b, hp9845b,driver_device, 0, "Hewlett-Packard", "9845B", 0 )
|
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COMP( 1980, hp9845t, hp9845b, 0, hp9845b, hp9845b,driver_device, 0, "Hewlett-Packard", "9845T", MACHINE_IS_SKELETON | MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
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COMP( 1981, hp9845c, hp9845b, 0, hp9845b, hp9845b,driver_device, 0, "Hewlett-Packard", "9845C", MACHINE_IS_SKELETON | MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
|
||||
|
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Loading…
Reference in New Issue
Block a user