Sprinter/mame
2
0
Fork 0
mirror of https://github.com/holub/mame synced 2025-04-25 17:56:43 +03:00
Code Issues Actions Packages Projects Releases Wiki Activity

- SGI: Added R3000 IRIS Indigo skeleton. [MooglyGuy, Jan-Jaap]

Browse Source
This commit is contained in:
therealmogminer@gmail.com 2015-12-23 17:16:38 +01:00
parent b2ae952300
commit bb1bdd9e04
4 changed files with 171 additions and 163 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/mame/drivers/sgi_ip6.cpp → src/mame/drivers/4dpi.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Ryan Holtz
/****************************************************************************
drivers/sgi_ip6.c
drivers/4dpi.cpp
SGI 4D/PI IP6 family skeleton driver
by Ryan Holtz

274
src/mame/drivers/ip20.cpp → src/mame/drivers/indigo.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Ryan Holtz
/*********************************************************************\
*
* SGI IP20 IRIS Indigo workstation
* SGI Indigo workstation
*
* Skeleton Driver
*
@ -20,6 +20,7 @@
#include "emu.h"
#include "cpu/mips/mips3.h"
#include "cpu/mips/r3000.h"
#include "machine/8530scc.h"
#include "machine/sgi.h"
#include "machine/eepromser.h"
@ -27,25 +28,7 @@
#include "bus/scsi/scsicd.h"
#include "machine/wd33c93.h"
struct HPC_t
{
UINT8 nMiscStatus;
UINT32 nParBufPtr;
UINT32 nLocalIOReg0Mask;
UINT32 nLocalIOReg1Mask;
UINT32 nVMEIntMask0;
UINT32 nVMEIntMask1;
UINT32 nSCSI0Descriptor;
UINT32 nSCSI0DMACtrl;
};
struct ip20_RTC_t
{
UINT8 nRAM[32];
UINT8 nTemp;
};
class ip20_state : public driver_device
class indigo_state : public driver_device
{
public:
enum
@ -53,32 +36,55 @@ public:
TIMER_RTC
};
ip20_state(const machine_config &mconfig, device_type type, const char *tag) :
driver_device(mconfig, type, tag),
m_wd33c93(*this, "wd33c93"),
m_scc(*this, "scc"),
m_eeprom(*this, "eeprom"),
m_maincpu(*this, "maincpu")
indigo_state(const machine_config &mconfig, device_type type, const char *tag)
: driver_device(mconfig, type, tag)
, m_maincpu(*this, "maincpu")
, m_wd33c93(*this, "wd33c93")
, m_scc(*this, "scc")
, m_eeprom(*this, "eeprom")
{
}
HPC_t m_HPC;
ip20_RTC_t m_RTC;
DECLARE_READ32_MEMBER(hpc_r);
DECLARE_WRITE32_MEMBER(hpc_w);
DECLARE_READ32_MEMBER(int_r);
DECLARE_WRITE32_MEMBER(int_w);
DECLARE_WRITE_LINE_MEMBER(scsi_irq);
DECLARE_DRIVER_INIT(ip204415);
virtual void machine_start() override;
virtual void video_start() override;
UINT32 screen_update_ip204415(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
TIMER_CALLBACK_MEMBER(ip20_timer_rtc);
UINT32 screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect);
private:
struct hpc_t
{
UINT8 m_misc_status;
UINT32 m_parbuf_ptr;
UINT32 m_local_ioreg0_mask;
UINT32 m_local_ioreg1_mask;
UINT32 m_vme_intmask0;
UINT32 m_vme_intmask1;
UINT32 m_scsi0_descriptor;
UINT32 m_scsi0_dma_ctrl;
};
struct rtc_t
{
UINT8 nRAM[32];
};
required_device<cpu_device> m_maincpu;
required_device<wd33c93_device> m_wd33c93;
required_device<scc8530_t> m_scc;
required_device<eeprom_serial_93cxx_device> m_eeprom;
hpc_t m_hpc;
rtc_t m_rtc;
void indigo_timer_rtc();
inline void ATTR_PRINTF(3,4) verboselog(int n_level, const char *s_fmt, ... );
required_device<cpu_device> m_maincpu;
protected:
virtual void device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr) override;
@ -87,7 +93,7 @@ protected:
#define VERBOSE_LEVEL ( 2 )
inline void ATTR_PRINTF(3,4) ip20_state::verboselog(int n_level, const char *s_fmt, ... )
inline void ATTR_PRINTF(3,4) indigo_state::verboselog(int n_level, const char *s_fmt, ... )
{
if( VERBOSE_LEVEL >= n_level )
{
@ -100,33 +106,33 @@ inline void ATTR_PRINTF(3,4) ip20_state::verboselog(int n_level, const char *s_f
}
}
void ip20_state::video_start()
void indigo_state::video_start()
{
}
UINT32 ip20_state::screen_update_ip204415(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
UINT32 indigo_state::screen_update(screen_device &screen, bitmap_ind16 &bitmap, const rectangle &cliprect)
{
return 0;
}
#define RTC_DAYOFWEEK m_RTC.nRAM[0x0e]
#define RTC_YEAR m_RTC.nRAM[0x0b]
#define RTC_MONTH m_RTC.nRAM[0x0a]
#define RTC_DAY m_RTC.nRAM[0x09]
#define RTC_HOUR m_RTC.nRAM[0x08]
#define RTC_MINUTE m_RTC.nRAM[0x07]
#define RTC_SECOND m_RTC.nRAM[0x06]
#define RTC_HUNDREDTH m_RTC.nRAM[0x05]
#define RTC_DAYOFWEEK m_rtc.nRAM[0x0e]
#define RTC_YEAR m_rtc.nRAM[0x0b]
#define RTC_MONTH m_rtc.nRAM[0x0a]
#define RTC_DAY m_rtc.nRAM[0x09]
#define RTC_HOUR m_rtc.nRAM[0x08]
#define RTC_MINUTE m_rtc.nRAM[0x07]
#define RTC_SECOND m_rtc.nRAM[0x06]
#define RTC_HUNDREDTH m_rtc.nRAM[0x05]
READ32_MEMBER(ip20_state::hpc_r)
READ32_MEMBER(indigo_state::hpc_r)
{
offset <<= 2;
if( offset >= 0x0e00 && offset <= 0x0e7c )
{
verboselog(2, "RTC RAM[0x%02x] Read: %02x\n", ( offset - 0xe00 ) >> 2, m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ] );
return m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ];
verboselog(2, "RTC RAM[0x%02x] Read: %02x\n", ( offset - 0xe00 ) >> 2, m_rtc.nRAM[ ( offset - 0xe00 ) >> 2 ] );
return m_rtc.nRAM[ ( offset - 0xe00 ) >> 2 ];
}
switch( offset )
{
@ -134,8 +140,8 @@ READ32_MEMBER(ip20_state::hpc_r)
verboselog(2, "HPC Unknown Read: %08x (%08x) (returning 0x000000a5 as kludge)\n", 0x1fb80000 + offset, mem_mask );
return 0x0000a500;
case 0x00ac:
verboselog(2, "HPC Parallel Buffer Pointer Read: %08x (%08x)\n", m_HPC.nParBufPtr, mem_mask );
return m_HPC.nParBufPtr;
verboselog(2, "HPC Parallel Buffer Pointer Read: %08x (%08x)\n", m_hpc.m_parbuf_ptr, mem_mask );
return m_hpc.m_parbuf_ptr;
case 0x00c0:
verboselog(2, "HPC Endianness Read: %08x (%08x)\n", 0x0000001f, mem_mask );
return 0x0000001f;
@ -158,23 +164,23 @@ READ32_MEMBER(ip20_state::hpc_r)
return 0;
}
case 0x01b0:
verboselog(2, "HPC Misc. Status Read: %08x (%08x)\n", m_HPC.nMiscStatus, mem_mask );
return m_HPC.nMiscStatus;
verboselog(2, "HPC Misc. Status Read: %08x (%08x)\n", m_hpc.m_misc_status, mem_mask );
return m_hpc.m_misc_status;
case 0x01bc:
// verboselog(machine, 2, "HPC CPU Serial EEPROM Read\n" );
return m_eeprom->do_read() << 4;
case 0x01c4:
verboselog(2, "HPC Local IO Register 0 Mask Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
return m_HPC.nLocalIOReg0Mask;
verboselog(2, "HPC Local IO Register 0 Mask Read: %08x (%08x)\n", m_hpc.m_local_ioreg0_mask, mem_mask );
return m_hpc.m_local_ioreg0_mask;
case 0x01cc:
verboselog(2, "HPC Local IO Register 1 Mask Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
return m_HPC.nLocalIOReg1Mask;
verboselog(2, "HPC Local IO Register 1 Mask Read: %08x (%08x)\n", m_hpc.m_local_ioreg1_mask, mem_mask );
return m_hpc.m_local_ioreg1_mask;
case 0x01d4:
verboselog(2, "HPC VME Interrupt Mask 0 Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
return m_HPC.nVMEIntMask0;
verboselog(2, "HPC VME Interrupt Mask 0 Read: %08x (%08x)\n", m_hpc.m_vme_intmask0, mem_mask );
return m_hpc.m_vme_intmask0;
case 0x01d8:
verboselog(2, "HPC VME Interrupt Mask 1 Read: %08x (%08x)\n", m_HPC.nLocalIOReg0Mask, mem_mask );
return m_HPC.nVMEIntMask1;
verboselog(2, "HPC VME Interrupt Mask 1 Read: %08x (%08x)\n", m_hpc.m_vme_intmask1, mem_mask );
return m_hpc.m_vme_intmask1;
case 0x0d00:
verboselog(2, "HPC DUART0 Channel B Control Read\n" );
// return 0x00000004;
@ -232,27 +238,27 @@ READ32_MEMBER(ip20_state::hpc_r)
return 0;
}
WRITE32_MEMBER(ip20_state::hpc_w)
WRITE32_MEMBER(indigo_state::hpc_w)
{
offset <<= 2;
if( offset >= 0x0e00 && offset <= 0x0e7c )
{
verboselog(2, "RTC RAM[0x%02x] Write: %02x\n", ( offset - 0xe00 ) >> 2, data & 0x000000ff );
m_RTC.nRAM[ ( offset - 0xe00 ) >> 2 ] = data & 0x000000ff;
m_rtc.nRAM[ ( offset - 0xe00 ) >> 2 ] = data & 0x000000ff;
switch( ( offset - 0xe00 ) >> 2 )
{
case 0:
break;
case 4:
if( !( m_RTC.nRAM[0x00] & 0x80 ) )
if( !( m_rtc.nRAM[0x00] & 0x80 ) )
{
if( data & 0x80 )
{
m_RTC.nRAM[0x19] = m_RTC.nRAM[0x06]; //RTC_SECOND;
m_RTC.nRAM[0x1a] = m_RTC.nRAM[0x07]; //RTC_MINUTE;
m_RTC.nRAM[0x1b] = m_RTC.nRAM[0x08]; //RTC_HOUR;
m_RTC.nRAM[0x1c] = m_RTC.nRAM[0x09]; //RTC_DAY;
m_RTC.nRAM[0x1d] = m_RTC.nRAM[0x0a]; //RTC_MONTH;
m_rtc.nRAM[0x19] = m_rtc.nRAM[0x06]; //RTC_SECOND;
m_rtc.nRAM[0x1a] = m_rtc.nRAM[0x07]; //RTC_MINUTE;
m_rtc.nRAM[0x1b] = m_rtc.nRAM[0x08]; //RTC_HOUR;
m_rtc.nRAM[0x1c] = m_rtc.nRAM[0x09]; //RTC_DAY;
m_rtc.nRAM[0x1d] = m_rtc.nRAM[0x0a]; //RTC_MONTH;
}
}
break;
@ -262,11 +268,11 @@ WRITE32_MEMBER(ip20_state::hpc_w)
switch( offset )
{
case 0x0090: // SCSI0 next descriptor pointer
m_HPC.nSCSI0Descriptor = data;
m_hpc.m_scsi0_descriptor = data;
break;
case 0x0094: // SCSI0 control flags
m_HPC.nSCSI0DMACtrl = data;
m_hpc.m_scsi0_dma_ctrl = data;
#if 0
if (data & 0x80)
{
@ -275,10 +281,10 @@ WRITE32_MEMBER(ip20_state::hpc_w)
osd_printf_info("DMA activated for SCSI0\n");
osd_printf_info("Descriptor block:\n");
osd_printf_info("CTL: %08x BUFPTR: %08x DESCPTR %08x\n",
program_read_dword(m_HPC.nSCSI0Descriptor), program_read_dword(m_HPC.nSCSI0Descriptor+4),
program_read_dword(m_HPC.nSCSI0Descriptor+8));
program_read_dword(m_hpc.m_scsi0_descriptor), program_read_dword(m_hpc.m_scsi0_descriptor+4),
program_read_dword(m_hpc.m_scsi0_descriptor+8));
next = program_read_dword(m_HPC.nSCSI0Descriptor+8);
next = program_read_dword(m_hpc.m_scsi0_descriptor+8);
osd_printf_info("CTL: %08x BUFPTR: %08x DESCPTR %08x\n",
program_read_dword(next), program_read_dword(next+4),
program_read_dword(next+8));
@ -288,7 +294,7 @@ WRITE32_MEMBER(ip20_state::hpc_w)
case 0x00ac:
verboselog(2, "HPC Parallel Buffer Pointer Write: %08x (%08x)\n", data, mem_mask );
m_HPC.nParBufPtr = data;
m_hpc.m_parbuf_ptr = data;
break;
case 0x0120:
if (ACCESSING_BITS_8_15)
@ -338,7 +344,7 @@ WRITE32_MEMBER(ip20_state::hpc_w)
{
verboselog(2, " SRAM size: 8K\n" );
}
m_HPC.nMiscStatus = data;
m_hpc.m_misc_status = data;
break;
case 0x01bc:
// verboselog(machine, 2, "HPC CPU Serial EEPROM Write: %08x (%08x)\n", data, mem_mask );
@ -352,19 +358,19 @@ WRITE32_MEMBER(ip20_state::hpc_w)
break;
case 0x01c4:
verboselog(2, "HPC Local IO Register 0 Mask Write: %08x (%08x)\n", data, mem_mask );
m_HPC.nLocalIOReg0Mask = data;
m_hpc.m_local_ioreg0_mask = data;
break;
case 0x01cc:
verboselog(2, "HPC Local IO Register 1 Mask Write: %08x (%08x)\n", data, mem_mask );
m_HPC.nLocalIOReg1Mask = data;
m_hpc.m_local_ioreg1_mask = data;
break;
case 0x01d4:
verboselog(2, "HPC VME Interrupt Mask 0 Write: %08x (%08x)\n", data, mem_mask );
m_HPC.nVMEIntMask0 = data;
m_hpc.m_vme_intmask0 = data;
break;
case 0x01d8:
verboselog(2, "HPC VME Interrupt Mask 1 Write: %08x (%08x)\n", data, mem_mask );
m_HPC.nVMEIntMask1 = data;
m_hpc.m_vme_intmask1 = data;
break;
case 0x0d00:
verboselog(2, "HPC DUART0 Channel B Control Write: %08x (%08x)\n", data, mem_mask );
@ -441,18 +447,18 @@ WRITE32_MEMBER(ip20_state::hpc_w)
}
// INT/INT2/INT3 interrupt controllers
READ32_MEMBER(ip20_state::int_r)
READ32_MEMBER(indigo_state::int_r)
{
osd_printf_info("INT: read @ ofs %x (mask %x) (PC=%x)\n", offset, mem_mask, space.device().safe_pc());
return 0;
}
WRITE32_MEMBER(ip20_state::int_w)
WRITE32_MEMBER(indigo_state::int_w)
{
osd_printf_info("INT: write %x to ofs %x (mask %x) (PC=%x)\n", data, offset, mem_mask, space.device().safe_pc());
}
static ADDRESS_MAP_START( ip204415_map, AS_PROGRAM, 32, ip20_state )
static ADDRESS_MAP_START( indigo_map, AS_PROGRAM, 32, indigo_state )
AM_RANGE( 0x00000000, 0x001fffff ) AM_RAM AM_SHARE("share10")
AM_RANGE( 0x08000000, 0x08ffffff ) AM_RAM AM_SHARE("share5")
AM_RANGE( 0x09000000, 0x097fffff ) AM_RAM AM_SHARE("share6")
@ -460,10 +466,8 @@ static ADDRESS_MAP_START( ip204415_map, AS_PROGRAM, 32, ip20_state )
AM_RANGE( 0x0c000000, 0x0c7fffff ) AM_RAM AM_SHARE("share8")
AM_RANGE( 0x10000000, 0x107fffff ) AM_RAM AM_SHARE("share9")
AM_RANGE( 0x18000000, 0x187fffff ) AM_RAM AM_SHARE("share1")
AM_RANGE( 0x1fa00000, 0x1fa1ffff ) AM_DEVREADWRITE("sgi_mc", sgi_mc_device, read, write )
AM_RANGE( 0x1fb80000, 0x1fb8ffff ) AM_READWRITE(hpc_r, hpc_w )
AM_RANGE( 0x1fbd9000, 0x1fbd903f ) AM_READWRITE(int_r, int_w )
AM_RANGE( 0x1fc00000, 0x1fc7ffff ) AM_ROM AM_SHARE("share2") AM_REGION( "user1", 0 )
AM_RANGE( 0x80000000, 0x801fffff ) AM_RAM AM_SHARE("share10")
AM_RANGE( 0x88000000, 0x88ffffff ) AM_RAM AM_SHARE("share5")
AM_RANGE( 0xa0000000, 0xa01fffff ) AM_RAM AM_SHARE("share10")
@ -473,39 +477,43 @@ static ADDRESS_MAP_START( ip204415_map, AS_PROGRAM, 32, ip20_state )
AM_RANGE( 0xac000000, 0xac7fffff ) AM_RAM AM_SHARE("share8")
AM_RANGE( 0xb0000000, 0xb07fffff ) AM_RAM AM_SHARE("share9")
AM_RANGE( 0xb8000000, 0xb87fffff ) AM_RAM AM_SHARE("share1")
AM_RANGE( 0xbfa00000, 0xbfa1ffff ) AM_DEVREADWRITE("sgi_mc", sgi_mc_device, read, write )
AM_RANGE( 0xbfb80000, 0xbfb8ffff ) AM_READWRITE(hpc_r, hpc_w )
AM_RANGE( 0xbfbd9000, 0xbfbd903f ) AM_READWRITE(int_r, int_w )
ADDRESS_MAP_END
static ADDRESS_MAP_START( indigo3k_map, AS_PROGRAM, 32, indigo_state )
AM_IMPORT_FROM( indigo_map )
AM_RANGE( 0x1fc00000, 0x1fc3ffff ) AM_ROM AM_SHARE("share2") AM_REGION( "user1", 0 )
AM_RANGE( 0xbfc00000, 0xbfc3ffff ) AM_ROM AM_SHARE("share2") /* BIOS Mirror */
ADDRESS_MAP_END
static ADDRESS_MAP_START( indigo4k_map, AS_PROGRAM, 32, indigo_state )
AM_IMPORT_FROM( indigo_map )
AM_RANGE( 0x1fa00000, 0x1fa1ffff ) AM_DEVREADWRITE("sgi_mc", sgi_mc_device, read, write )
AM_RANGE( 0x1fc00000, 0x1fc7ffff ) AM_ROM AM_SHARE("share2") AM_REGION( "user1", 0 )
AM_RANGE( 0xbfa00000, 0xbfa1ffff ) AM_DEVREADWRITE("sgi_mc", sgi_mc_device, read, write )
AM_RANGE( 0xbfc00000, 0xbfc7ffff ) AM_ROM AM_SHARE("share2") /* BIOS Mirror */
ADDRESS_MAP_END
WRITE_LINE_MEMBER(ip20_state::scsi_irq)
WRITE_LINE_MEMBER(indigo_state::scsi_irq)
{
}
DRIVER_INIT_MEMBER(ip20_state,ip204415)
{
}
void ip20_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
void indigo_state::device_timer(emu_timer &timer, device_timer_id id, int param, void *ptr)
{
switch (id)
{
case TIMER_RTC:
ip20_timer_rtc(ptr, param);
indigo_timer_rtc();
break;
default:
assert_always(FALSE, "Unknown id in ip20_state::device_timer");
assert_always(FALSE, "Unknown id in indigo_state::device_timer");
}
}
TIMER_CALLBACK_MEMBER(ip20_state::ip20_timer_rtc)
void indigo_state::indigo_timer_rtc()
{
// update RTC every 10 milliseconds
m_RTC.nTemp++;
if (m_RTC.nTemp >= 10)
{
m_RTC.nTemp = 0;
RTC_HUNDREDTH++;
if( ( RTC_HUNDREDTH & 0x0f ) == 0x0a )
@ -551,48 +559,36 @@ TIMER_CALLBACK_MEMBER(ip20_state::ip20_timer_rtc)
}
}
}
timer_set(attotime::from_msec(10), TIMER_RTC);
}
timer_set(attotime::from_msec(1), TIMER_RTC);
}
void ip20_state::machine_start()
void indigo_state::machine_start()
{
m_HPC.nMiscStatus = 0;
m_HPC.nParBufPtr = 0;
m_HPC.nLocalIOReg0Mask = 0;
m_HPC.nLocalIOReg1Mask = 0;
m_HPC.nVMEIntMask0 = 0;
m_HPC.nVMEIntMask1 = 0;
m_hpc.m_misc_status = 0;
m_hpc.m_parbuf_ptr = 0;
m_hpc.m_local_ioreg0_mask = 0;
m_hpc.m_local_ioreg1_mask = 0;
m_hpc.m_vme_intmask0 = 0;
m_hpc.m_vme_intmask1 = 0;
m_RTC.nTemp = 0;
timer_set(attotime::from_msec(1), TIMER_RTC);
timer_set(attotime::from_msec(10), TIMER_RTC);
}
static INPUT_PORTS_START( ip204415 )
static INPUT_PORTS_START( indigo )
PORT_START("unused")
PORT_BIT ( 0xff, IP_ACTIVE_HIGH, IPT_UNUSED )
INPUT_PORTS_END
#if 0
static const mips3_config config =
{
32768, /* code cache size */
32768 /* data cache size */
};
#endif
static MACHINE_CONFIG_FRAGMENT( cdrom_config )
MCFG_DEVICE_MODIFY( "cdda" )
MCFG_SOUND_ROUTE(ALL_OUTPUTS, "^^^^mono", 1.0)
MACHINE_CONFIG_END
static MACHINE_CONFIG_START( ip204415, ip20_state )
MCFG_CPU_ADD( "maincpu", R4600BE, 50000000*3 )
MCFG_CPU_CONFIG( config )
MCFG_CPU_PROGRAM_MAP( ip204415_map)
static MACHINE_CONFIG_START( indigo3k, indigo_state )
MCFG_CPU_ADD("maincpu", R3041, 33000000)
MCFG_R3000_ENDIANNESS(ENDIANNESS_BIG)
MCFG_CPU_PROGRAM_MAP(indigo3k_map)
/* video hardware */
MCFG_SCREEN_ADD("screen", RASTER)
@ -600,33 +596,45 @@ static MACHINE_CONFIG_START( ip204415, ip20_state )
MCFG_SCREEN_VBLANK_TIME(ATTOSECONDS_IN_USEC(2500)) /* not accurate */
MCFG_SCREEN_SIZE(800, 600)
MCFG_SCREEN_VISIBLE_AREA(0, 799, 0, 599)
MCFG_SCREEN_UPDATE_DRIVER(ip20_state, screen_update_ip204415)
MCFG_SCREEN_UPDATE_DRIVER(indigo_state, screen_update)
MCFG_SCREEN_PALETTE("palette")
MCFG_PALETTE_ADD("palette", 65536)
MCFG_SPEAKER_STANDARD_MONO("mono")
MCFG_DEVICE_ADD("scc", SCC8530, 7000000)
MCFG_DEVICE_ADD("sgi_mc", SGI_MC, 0)
MCFG_DEVICE_ADD("scsi", SCSI_PORT, 0)
MCFG_SCSIDEV_ADD("scsi:" SCSI_PORT_DEVICE1, "cdrom", SCSICD, SCSI_ID_6)
MCFG_SLOT_OPTION_MACHINE_CONFIG("cdrom", cdrom_config)
MCFG_DEVICE_ADD("wd33c93", WD33C93, 0)
MCFG_LEGACY_SCSI_PORT("scsi")
MCFG_WD33C93_IRQ_CB(WRITELINE(ip20_state, scsi_irq)) /* command completion IRQ */
MCFG_WD33C93_IRQ_CB(WRITELINE(indigo_state, scsi_irq)) /* command completion IRQ */
MCFG_EEPROM_SERIAL_93C56_ADD("eeprom")
MACHINE_CONFIG_END
ROM_START( ip204415 )
ROM_REGION( 0x80000, "user1", 0 )
ROM_LOAD( "ip204415.bin", 0x000000, 0x080000, CRC(940d960e) SHA1(596aba530b53a147985ff3f6f853471ce48c866c) )
static MACHINE_CONFIG_DERIVED( indigo4k, indigo3k )
MCFG_CPU_REPLACE("maincpu", R4600BE, 150000000) // Should be R4400
MCFG_MIPS3_ICACHE_SIZE(32768)
MCFG_MIPS3_DCACHE_SIZE(32768)
MCFG_CPU_PROGRAM_MAP(indigo4k_map)
MCFG_DEVICE_ADD("sgi_mc", SGI_MC, 0)
MACHINE_CONFIG_END
ROM_START( indigo3k )
ROM_REGION( 0x40000, "user1", 0 )
ROM_LOAD( "ip12prom.070-8088-xxx.bin", 0x000000, 0x040000, CRC(bb2f32ab) SHA1(d5f63dfbcca1206885753145ee34921b891b7eaf) )
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT INIT COMPANY FULLNAME */
COMP( 1993, ip204415, 0, 0, ip204415, ip204415, ip20_state, ip204415, "Silicon Graphics Inc", "IRIS Indigo (R4400, 150MHz)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
ROM_START( indigo4k )
ROM_REGION( 0x80000, "user1", 0 )
ROM_LOAD( "ip20prom.070-8116-004.bin", 0x000000, 0x080000, CRC(940d960e) SHA1(596aba530b53a147985ff3f6f853471ce48c866c) )
ROM_END
/* YEAR NAME PARENT COMPAT MACHINE INPUT CLASS INIT COMPANY FULLNAME */
COMP( 1991, indigo3k, 0, 0, indigo3k, indigo, driver_device, 0, "Silicon Graphics Inc", "IRIS Indigo (R4400, 150MHz, Ver. 4.0.5D Rev A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )
COMP( 1993, indigo4k, 0, 0, indigo4k, indigo, driver_device, 0, "Silicon Graphics Inc", "IRIS Indigo (R4400, 150MHz, Ver. 4.0.5D Rev A)", MACHINE_NOT_WORKING | MACHINE_NO_SOUND )

0
src/mame/drivers/ip22.cpp → src/mame/drivers/indy_indigo2.cpp
View File

2
src/mame/drivers/sgi_ip2.cpp → src/mame/drivers/iris3130.cpp
View File

@ -2,7 +2,7 @@
// copyright-holders:Ryan Holtz
/****************************************************************************
drivers/sgi_ip2.c
drivers/sgi_ip2.cpp
SGI IRIS 3130 skeleton driver with some meat on its bones
by Ryan Holtz