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https://github.com/holub/mame
synced 2025-04-23 08:49:55 +03:00
scudsp_cpu_device: converted to devcb2 (nw)
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1b4f7107a2
commit
bbad592d0c
@ -692,7 +692,7 @@ void scudsp_cpu_device::scudsp_dma( UINT32 opcode )
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{
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for(m_dma.count = 0;m_dma.count < m_dma.size; m_dma.count++)
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{
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data = (m_in_dma_func(m_dma.src)<<16) | m_in_dma_func(m_dma.src+2);
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data = (m_in_dma_cb(m_dma.src)<<16) | m_in_dma_cb(m_dma.src+2);
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scudsp_set_dest_dma_mem( m_dma.dst, data, m_dma.count );
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m_dma.src += m_dma.add;
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@ -709,8 +709,8 @@ void scudsp_cpu_device::scudsp_dma( UINT32 opcode )
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{
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data = scudsp_get_mem_source_dma( m_dma.src, m_dma.count );
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m_out_dma_func(m_dma.dst, data >> 16 );
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m_out_dma_func(m_dma.dst+2, data & 0xffff );
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m_out_dma_cb(m_dma.dst, data >> 16 );
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m_out_dma_cb(m_dma.dst+2, data & 0xffff );
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m_dma.dst += m_dma.add;
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@ -787,7 +787,7 @@ void scudsp_cpu_device::scudsp_end(UINT32 opcode)
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{
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/*ENDI*/
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EF_1;
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m_out_irq_func(1);
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m_out_irq_cb(1);
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}
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EXF_0; /* END / ENDI */
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@ -806,7 +806,7 @@ void scudsp_cpu_device::scudsp_exec_dma()
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UINT32 data;
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if ( m_dma.dir == 0 )
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{
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data = (m_in_dma_func(m_dma.src)<<16) | m_in_dma_func(m_dma.src+2);
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data = (m_in_dma_cb(m_dma.src)<<16) | m_in_dma_cb(m_dma.src+2);
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scudsp_set_dest_dma_mem( m_dma.dst, data, m_dma.count );
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m_dma.src += m_dma.add;
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@ -820,8 +820,8 @@ void scudsp_cpu_device::scudsp_exec_dma()
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{
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data = scudsp_get_mem_source_dma( m_dma.src, m_dma.count );
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m_out_dma_func(m_dma.dst, data >> 16 );
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m_out_dma_func(m_dma.dst+2, data & 0xffff );
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m_out_dma_cb(m_dma.dst, data >> 16 );
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m_out_dma_cb(m_dma.dst+2, data & 0xffff );
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m_dma.dst += m_dma.add;
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@ -907,27 +907,6 @@ void scudsp_cpu_device::execute_run()
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} while( m_icount > 0 );
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}
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//-------------------------------------------------
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// device_config_complete - perform any
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// operations now that the configuration is
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// complete
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//-------------------------------------------------
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void scudsp_cpu_device::device_config_complete()
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{
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// inherit a copy of the static data
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const scudsp_interface *intf = reinterpret_cast<const scudsp_interface *>(static_config());
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if (intf != NULL)
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*static_cast<scudsp_interface *>(this) = *intf;
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// or error out if none provided
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else
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{
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fatalerror("SCUDSP_INTERFACE for cpu '%s' not defined!\n", tag());
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}
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}
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void scudsp_cpu_device::device_start()
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{
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m_program = &space(AS_PROGRAM);
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@ -988,9 +967,9 @@ void scudsp_cpu_device::device_start()
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state_add( STATE_GENPC, "curpc", m_pc ).noshow();
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state_add( STATE_GENFLAGS, "GENFLAGS", m_flags ).formatstr("%17s").noshow();
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m_out_irq_func.resolve(m_out_irq_cb, *this);
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m_in_dma_func.resolve(m_in_dma_cb, *this);
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m_out_dma_func.resolve(m_out_dma_cb, *this);
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m_out_irq_cb.resolve_safe();
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m_in_dma_cb.resolve_safe(0);
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m_out_dma_cb.resolve_safe();
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m_icountptr = &m_icount;
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}
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@ -1011,6 +990,9 @@ void scudsp_cpu_device::execute_set_input(int irqline, int state)
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scudsp_cpu_device::scudsp_cpu_device(const machine_config &mconfig, const char *tag, device_t *owner, UINT32 clock)
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: cpu_device(mconfig, SCUDSP, "SCUDSP", tag, owner, clock, "scudsp", __FILE__)
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, m_out_irq_cb(*this)
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, m_in_dma_cb(*this)
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, m_out_dma_cb(*this)
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, m_program_config("program", ENDIANNESS_BIG, 32, 8, -2)
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, m_data_config("data", ENDIANNESS_BIG, 32, 8, -2)
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{
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@ -33,17 +33,15 @@ enum
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SCUDSP_CT3
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};
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// ======================> scudsp_interface
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struct scudsp_interface
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{
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devcb_write_line m_out_irq_cb;
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devcb_read16 m_in_dma_cb;
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devcb_write16 m_out_dma_cb;
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};
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#define MCFG_SCUDSP_OUT_IRQ_CB(_devcb) \
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devcb = &scudsp_cpu_device::set_out_irq_callback(*device, DEVCB2_##_devcb);
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#define SCUDSP_INTERFACE(name) \
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const scudsp_interface (name) =
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#define MCFG_SCUDSP_IN_DMA_CB(_devcb) \
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devcb = &scudsp_cpu_device::set_in_dma_callback(*device, DEVCB2_##_devcb);
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#define MCFG_SCUDSP_OUT_DMA_CB(_devcb) \
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devcb = &scudsp_cpu_device::set_out_dma_callback(*device, DEVCB2_##_devcb);
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#define SCUDSP_RESET INPUT_LINE_RESET /* Non-Maskable */
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@ -58,13 +56,16 @@ union SCUDSPREG16 {
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UINT16 ui;
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};
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class scudsp_cpu_device : public cpu_device,
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public scudsp_interface
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class scudsp_cpu_device : public cpu_device
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{
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public:
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// construction/destruction
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scudsp_cpu_device(const machine_config &mconfig, const char *_tag, device_t *_owner, UINT32 _clock);
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template<class _Object> static devcb2_base &set_out_irq_callback(device_t &device, _Object object) { return downcast<scudsp_cpu_device &>(device).m_out_irq_cb.set_callback(object); }
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template<class _Object> static devcb2_base &set_in_dma_callback(device_t &device, _Object object) { return downcast<scudsp_cpu_device &>(device).m_in_dma_cb.set_callback(object); }
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template<class _Object> static devcb2_base &set_out_dma_callback(device_t &device, _Object object) { return downcast<scudsp_cpu_device &>(device).m_out_dma_cb.set_callback(object); }
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/* port 0 */
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DECLARE_READ32_MEMBER( program_control_r );
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DECLARE_WRITE32_MEMBER( program_control_w );
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@ -79,7 +80,6 @@ public:
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protected:
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// device-level overrides
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virtual void device_config_complete();
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virtual void device_start();
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virtual void device_reset();
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@ -101,9 +101,10 @@ protected:
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virtual UINT32 disasm_max_opcode_bytes() const { return 4; }
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virtual offs_t disasm_disassemble(char *buffer, offs_t pc, const UINT8 *oprom, const UINT8 *opram, UINT32 options);
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devcb_resolved_write_line m_out_irq_func;
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devcb_resolved_read16 m_in_dma_func;
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devcb_resolved_write16 m_out_dma_func;
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devcb2_write_line m_out_irq_cb;
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devcb2_read16 m_in_dma_cb;
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devcb2_write16 m_out_dma_cb;
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private:
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address_space_config m_program_config;
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address_space_config m_data_config;
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@ -965,12 +965,6 @@ static ADDRESS_MAP_START( scudsp_data, AS_DATA, 32, stv_state )
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AM_RANGE(0x00, 0xff) AM_RAM
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ADDRESS_MAP_END
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static SCUDSP_INTERFACE( scudsp_config )
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{
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DEVCB_DRIVER_LINE_MEMBER(saturn_state, scudsp_end_w),
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DEVCB_DRIVER_MEMBER16(saturn_state,scudsp_dma_r),
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DEVCB_DRIVER_MEMBER16(saturn_state,scudsp_dma_w)
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};
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static MACHINE_CONFIG_START( stv, stv_state )
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@ -991,7 +985,9 @@ static MACHINE_CONFIG_START( stv, stv_state )
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MCFG_CPU_ADD("scudsp", SCUDSP, MASTER_CLOCK_352/4) // 14 MHz
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MCFG_CPU_PROGRAM_MAP(scudsp_mem)
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MCFG_CPU_DATA_MAP(scudsp_data)
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MCFG_CPU_CONFIG(scudsp_config)
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MCFG_SCUDSP_OUT_IRQ_CB(WRITELINE(saturn_state, scudsp_end_w))
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MCFG_SCUDSP_IN_DMA_CB(READ16(saturn_state, scudsp_dma_r))
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MCFG_SCUDSP_OUT_DMA_CB(WRITE16(saturn_state, scudsp_dma_w))
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MCFG_MACHINE_START_OVERRIDE(stv_state,stv)
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MCFG_MACHINE_RESET_OVERRIDE(stv_state,stv)
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@ -706,13 +706,6 @@ struct cdrom_interface saturn_cdrom =
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NULL
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};
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static SCUDSP_INTERFACE( scudsp_config )
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{
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DEVCB_DRIVER_LINE_MEMBER(saturn_state, scudsp_end_w),
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DEVCB_DRIVER_MEMBER16(saturn_state,scudsp_dma_r),
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DEVCB_DRIVER_MEMBER16(saturn_state,scudsp_dma_w)
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};
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static MACHINE_CONFIG_START( saturn, sat_console_state )
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/* basic machine hardware */
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@ -732,7 +725,9 @@ static MACHINE_CONFIG_START( saturn, sat_console_state )
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MCFG_CPU_ADD("scudsp", SCUDSP, MASTER_CLOCK_352/4) // 14 MHz
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MCFG_CPU_PROGRAM_MAP(scudsp_mem)
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MCFG_CPU_DATA_MAP(scudsp_data)
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MCFG_CPU_CONFIG(scudsp_config)
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MCFG_SCUDSP_OUT_IRQ_CB(WRITELINE(saturn_state, scudsp_end_w))
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MCFG_SCUDSP_IN_DMA_CB(READ16(saturn_state, scudsp_dma_r))
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MCFG_SCUDSP_OUT_DMA_CB(WRITE16(saturn_state, scudsp_dma_w))
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// SH-1
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