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H8: rewrote H8S/2xxx timers [Tim Schuerewegen]

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This commit is contained in:
R. Belmont 2011-08-01 22:54:38 +00:00
parent d2c6d91952
commit bbb7051d8d
5 changed files with 1417 additions and 343 deletions
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131
src/emu/cpu/h83002/h8.h
View File

@ -181,35 +181,87 @@ enum
#define H8S_IO_TSTR H8S_IO(0xFFC0)
#define H8S_IO_TSYR H8S_IO(0xFFC1)
// TPU0
#define H8S_IO_TTCR0 H8S_IO(0xFFD0)
#define H8S_IO_TMDR0 H8S_IO(0xFFD1)
#define H8S_IO_TIOR0H H8S_IO(0xFFD2)
#define H8S_IO_TIOR0L H8S_IO(0xFFD3)
#define H8S_IO_TIER0 H8S_IO(0xFFD4)
#define H8S_IO_TSR0 H8S_IO(0xFFD5)
#define H8S_IO_TTCNT0 H8S_IO(0xFFD6)
#define H8S_IO_TGR0A H8S_IO(0xFFD8)
#define H8S_IO_TGR0B H8S_IO(0xFFDA)
#define H8S_IO_TGR0C H8S_IO(0xFFDC)
#define H8S_IO_TGR0D H8S_IO(0xFFDE)
#define H8S_IO_TTCR0 H8S_IO(0xFFD0)
#define H8S_IO_TMDR0 H8S_IO(0xFFD1)
#define H8S_IO_TIOR0_H H8S_IO(0xFFD2)
#define H8S_IO_TIOR0_L H8S_IO(0xFFD3)
#define H8S_IO_TIER0 H8S_IO(0xFFD4)
#define H8S_IO_TSR0 H8S_IO(0xFFD5)
#define H8S_IO_TCNT0_H H8S_IO(0xFFD6)
#define H8S_IO_TCNT0_L H8S_IO(0xFFD7)
#define H8S_IO_TGR0A_H H8S_IO(0xFFD8)
#define H8S_IO_TGR0A_L H8S_IO(0xFFD9)
#define H8S_IO_TGR0B_H H8S_IO(0xFFDA)
#define H8S_IO_TGR0B_L H8S_IO(0xFFDB)
#define H8S_IO_TGR0C_H H8S_IO(0xFFDC)
#define H8S_IO_TGR0C_L H8S_IO(0xFFDD)
#define H8S_IO_TGR0D_H H8S_IO(0xFFDE)
#define H8S_IO_TGR0D_L H8S_IO(0xFFDF)
// TPU1
#define H8S_IO_TTCR1 H8S_IO(0xFFE0)
#define H8S_IO_TMDR1 H8S_IO(0xFFE1)
#define H8S_IO_TIOR1 H8S_IO(0xFFE2)
#define H8S_IO_TIER1 H8S_IO(0xFFE4)
#define H8S_IO_TSR1 H8S_IO(0xFFE5)
#define H8S_IO_TTCNT1 H8S_IO(0xFFE6)
#define H8S_IO_TGR1A H8S_IO(0xFFE8)
#define H8S_IO_TGR1B H8S_IO(0xFFEA)
#define H8S_IO_TTCR1 H8S_IO(0xFFE0)
#define H8S_IO_TMDR1 H8S_IO(0xFFE1)
#define H8S_IO_TIOR1 H8S_IO(0xFFE2)
#define H8S_IO_TIER1 H8S_IO(0xFFE4)
#define H8S_IO_TSR1 H8S_IO(0xFFE5)
#define H8S_IO_TCNT1_H H8S_IO(0xFFE6)
#define H8S_IO_TCNT1_L H8S_IO(0xFFE7)
#define H8S_IO_TGR1A_H H8S_IO(0xFFE8)
#define H8S_IO_TGR1A_L H8S_IO(0xFFE9)
#define H8S_IO_TGR1B_H H8S_IO(0xFFEA)
#define H8S_IO_TGR1B_L H8S_IO(0xFFEB)
// TPU2
#define H8S_IO_TTCR2 H8S_IO(0xFFF0)
#define H8S_IO_TMDR2 H8S_IO(0xFFF1)
#define H8S_IO_TIOR2 H8S_IO(0xFFF2)
#define H8S_IO_TIER2 H8S_IO(0xFFF4)
#define H8S_IO_TSR2 H8S_IO(0xFFF5)
#define H8S_IO_TCNT2_H H8S_IO(0xFFF6)
#define H8S_IO_TCNT2_L H8S_IO(0xFFF7)
#define H8S_IO_TGR2A_H H8S_IO(0xFFF8)
#define H8S_IO_TGR2A_L H8S_IO(0xFFF9)
#define H8S_IO_TGR2B_H H8S_IO(0xFFFA)
#define H8S_IO_TGR2B_L H8S_IO(0xFFFB)
// TPU3
#define H8S_IO_TTCR3 H8S_IO(0xFE80)
#define H8S_IO_TMDR3 H8S_IO(0xFE81)
#define H8S_IO_TIOR3_H H8S_IO(0xFE82)
#define H8S_IO_TIOR3_L H8S_IO(0xFE83)
#define H8S_IO_TIER3 H8S_IO(0xFE84)
#define H8S_IO_TSR3 H8S_IO(0xFE85)
#define H8S_IO_TCNT3_H H8S_IO(0xFE86)
#define H8S_IO_TCNT3_L H8S_IO(0xFE87)
#define H8S_IO_TGR3A_H H8S_IO(0xFE88)
#define H8S_IO_TGR3A_L H8S_IO(0xFE89)
#define H8S_IO_TGR3B_H H8S_IO(0xFE8A)
#define H8S_IO_TGR3B_L H8S_IO(0xFE8B)
#define H8S_IO_TGR3C_H H8S_IO(0xFE8C)
#define H8S_IO_TGR3C_L H8S_IO(0xFE8D)
#define H8S_IO_TGR3D_H H8S_IO(0xFE8E)
#define H8S_IO_TGR3D_L H8S_IO(0xFE8F)
// TPU4
#define H8S_IO_TTCR4 H8S_IO(0xFE90)
#define H8S_IO_TMDR4 H8S_IO(0xFE91)
#define H8S_IO_TIOR4 H8S_IO(0xFE92)
#define H8S_IO_TIER4 H8S_IO(0xFE94)
#define H8S_IO_TSR4 H8S_IO(0xFE95)
#define H8S_IO_TCNT4_H H8S_IO(0xFE96)
#define H8S_IO_TCNT4_L H8S_IO(0xFE97)
#define H8S_IO_TGR4A_H H8S_IO(0xFE98)
#define H8S_IO_TGR4A_L H8S_IO(0xFE99)
#define H8S_IO_TGR4B_H H8S_IO(0xFE9A)
#define H8S_IO_TGR4B_L H8S_IO(0xFE9B)
// TPU5
#define H8S_IO_TTCR5 H8S_IO(0xFEA0)
#define H8S_IO_TMDR5 H8S_IO(0xFEA1)
#define H8S_IO_TIOR5 H8S_IO(0xFEA2)
#define H8S_IO_TIER5 H8S_IO(0xFEA4)
#define H8S_IO_TSR5 H8S_IO(0xFEA5)
#define H8S_IO_TTCNT5 H8S_IO(0xFEA6)
#define H8S_IO_TGR5A H8S_IO(0xFEA8)
#define H8S_IO_TGR5B H8S_IO(0xFEAA)
#define H8S_IO_TTCR5 H8S_IO(0xFEA0)
#define H8S_IO_TMDR5 H8S_IO(0xFEA1)
#define H8S_IO_TIOR5 H8S_IO(0xFEA2)
#define H8S_IO_TIER5 H8S_IO(0xFEA4)
#define H8S_IO_TSR5 H8S_IO(0xFEA5)
#define H8S_IO_TCNT5_H H8S_IO(0xFEA6)
#define H8S_IO_TCNT5_L H8S_IO(0xFEA7)
#define H8S_IO_TGR5A_H H8S_IO(0xFEA8)
#define H8S_IO_TGR5A_L H8S_IO(0xFEA9)
#define H8S_IO_TGR5B_H H8S_IO(0xFEAA)
#define H8S_IO_TGR5B_L H8S_IO(0xFEAB)
// DMA
#define H8S_IO_MAR1AH H8S_IO(0xFEF0)
#define H8S_IO_MAR1AL H8S_IO(0xFEF2)
@ -248,6 +300,7 @@ enum
#define H8S_P5_RXD2 0x02
#define H8S_P5_TXD2 0x01
#define H8S_PF_PF6 0x40
#define H8S_PF_PF2 0x04
#define H8S_PF_PF1 0x02
#define H8S_PF_PF0 0x01
@ -294,15 +347,15 @@ enum
#define H8S_INT_TGI0B 0x21
#define H8S_INT_TGI0C 0x22
#define H8S_INT_TGI0D 0x23
#define H8S_INT_TGI0V 0x24
#define H8S_INT_TCI0V 0x24
#define H8S_INT_TGI1A 0x28
#define H8S_INT_TGI1B 0x29
#define H8S_INT_TGI1V 0x2A
#define H8S_INT_TGI1U 0x2B
#define H8S_INT_TCI1V 0x2A
#define H8S_INT_TCI1U 0x2B
#define H8S_INT_TGI2A 0x2C
#define H8S_INT_TGI2B 0x2D
#define H8S_INT_TGI2V 0x2E
#define H8S_INT_TGI2U 0x2F
#define H8S_INT_TCI2V 0x2E
#define H8S_INT_TCI2U 0x2F
#define H8S_INT_CMIA0 0x40
#define H8S_INT_CMIB0 0x41
#define H8S_INT_OVI0 0x42
@ -322,6 +375,20 @@ enum
#define H8S_INT_TXI2 0x5A
#define H8S_INT_TEI2 0x5B
#define H8S_INT_TGI3A 48
#define H8S_INT_TGI3B 49
#define H8S_INT_TGI3C 50
#define H8S_INT_TGI3D 51
#define H8S_INT_TCI3V 52
#define H8S_INT_TGI4A 56
#define H8S_INT_TGI4B 57
#define H8S_INT_TCI4V 58
#define H8S_INT_TCI4U 59
#define H8S_INT_TGI5A 60
#define H8S_INT_TGI5B 61
#define H8S_INT_TCI5V 62
#define H8S_INT_TCI5U 63
DECLARE_LEGACY_CPU_DEVICE(H83002, h8_3002);
DECLARE_LEGACY_CPU_DEVICE(H83007, h8_3007);
DECLARE_LEGACY_CPU_DEVICE(H83044, h8_3044);

113
src/emu/cpu/h83002/h8_16.c
View File

@ -578,6 +578,111 @@ static WRITE16_HANDLER( h8_3007_itu1_w )
}
}
WRITE16_HANDLER( h8s2241_per_regs_w )
{
h83xx_state *h8 = get_safe_token(&space->device());
if (mem_mask == 0xffff)
{
h8s2241_per_regs_write_16(h8, (offset << 1), data);
}
else if (mem_mask & 0xff00)
{
h8s2241_per_regs_write_8(h8, (offset << 1), (data >> 8) & 0xff);
}
else if (mem_mask == 0x00ff)
{
h8s2241_per_regs_write_8(h8, (offset << 1) + 1, data & 0xff);
}
}
WRITE16_HANDLER( h8s2246_per_regs_w )
{
h83xx_state *h8 = get_safe_token(&space->device());
if (mem_mask == 0xffff)
{
h8s2246_per_regs_write_16(h8, (offset << 1), data);
}
else if (mem_mask == 0xff00)
{
h8s2246_per_regs_write_8(h8, (offset << 1), (data >> 8) & 0xff);
}
else if (mem_mask == 0x00ff)
{
h8s2246_per_regs_write_8(h8, (offset << 1) + 1, data & 0xff);
}
}
WRITE16_HANDLER( h8s2323_per_regs_w )
{
h83xx_state *h8 = get_safe_token(&space->device());
if (mem_mask == 0xffff)
{
h8s2323_per_regs_write_16(h8, (offset << 1), data);
}
else if (mem_mask & 0xff00)
{
h8s2323_per_regs_write_8(h8, (offset << 1), (data >> 8) & 0xff);
}
else if (mem_mask == 0x00ff)
{
h8s2323_per_regs_write_8(h8, (offset << 1) + 1, data & 0xff);
}
}
READ16_HANDLER( h8s2241_per_regs_r )
{
h83xx_state *h8 = get_safe_token(&space->device());
if (mem_mask == 0xffff)
{
return h8s2241_per_regs_read_16(h8, (offset << 1));
}
else if (mem_mask == 0xff00)
{
return h8s2241_per_regs_read_8(h8, (offset << 1)) << 8;
}
else if (mem_mask == 0x00ff)
{
return h8s2241_per_regs_read_8(h8, (offset << 1) + 1);
}
return 0;
}
READ16_HANDLER( h8s2246_per_regs_r )
{
h83xx_state *h8 = get_safe_token(&space->device());
if (mem_mask == 0xffff)
{
return h8s2246_per_regs_read_16(h8, (offset << 1));
}
else if (mem_mask == 0xff00)
{
return h8s2246_per_regs_read_8(h8, (offset << 1)) << 8;
}
else if (mem_mask == 0x00ff)
{
return h8s2246_per_regs_read_8(h8, (offset << 1) + 1);
}
return 0;
}
READ16_HANDLER( h8s2323_per_regs_r )
{
h83xx_state *h8 = get_safe_token(&space->device());
if (mem_mask == 0xffff)
{
return h8s2323_per_regs_read_16(h8, (offset << 1));
}
else if (mem_mask == 0xff00)
{
return h8s2323_per_regs_read_8(h8, (offset << 1)) << 8;
}
else if (mem_mask == 0x00ff)
{
return h8s2323_per_regs_read_8(h8, (offset << 1) + 1);
}
return 0;
}
// On-board RAM and peripherals
static ADDRESS_MAP_START( h8_3002_internal_map, AS_PROGRAM, 16 )
// 512B RAM
@ -599,18 +704,18 @@ static ADDRESS_MAP_START( h8_3007_internal_map, AS_PROGRAM, 16 )
ADDRESS_MAP_END
static ADDRESS_MAP_START( h8s_2241_internal_map, AS_PROGRAM, 16 )
AM_RANGE( 0xFFDC00, 0xFFFBFF ) AM_RAM // on-chip ram
AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE8( h8s2241_per_regs_r_byte, h8s2241_per_regs_w_byte, 0xffff ) // internal i/o registers
AM_RANGE( 0xFFEC00, 0xFFFBFF ) AM_RAM // on-chip ram
AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE( h8s2241_per_regs_r, h8s2241_per_regs_w ) // internal i/o registers
ADDRESS_MAP_END
static ADDRESS_MAP_START( h8s_2246_internal_map, AS_PROGRAM, 16 )
AM_RANGE( 0xFFDC00, 0xFFFBFF ) AM_RAM // on-chip ram
AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE8( h8s2246_per_regs_r_byte, h8s2246_per_regs_w_byte, 0xffff ) // internal i/o registers
AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE( h8s2246_per_regs_r, h8s2246_per_regs_w ) // internal i/o registers
ADDRESS_MAP_END
static ADDRESS_MAP_START( h8s_2323_internal_map, AS_PROGRAM, 16 )
AM_RANGE( 0xFFDC00, 0xFFFBFF ) AM_RAM // on-chip ram
AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE8( h8s2323_per_regs_r_byte, h8s2323_per_regs_w_byte, 0xffff ) // internal i/o registers
AM_RANGE( 0xFFFE40, 0xFFFFFF ) AM_READWRITE( h8s2323_per_regs_r, h8s2323_per_regs_w ) // internal i/o registers
ADDRESS_MAP_END
CPU_GET_INFO( h8_3002 )

26
src/emu/cpu/h83002/h8ops.h
View File

@ -105,7 +105,8 @@ static void h8_btst8(h83xx_state *h8, UINT8 src, UINT8 dst);
static void h8_bld8(h83xx_state *h8, UINT8 src, UINT8 dst); // loads to carry
static void h8_bild8(h83xx_state *h8, UINT8 src, UINT8 dst); // inverts and loads to carry
static void h8_bor8(h83xx_state *h8, UINT8 src, UINT8 dst); // result in carry
//static void h8_bxor8(h83xx_state *h8, UINT8 src, UINT8 dst);
static void h8_bxor8(h83xx_state *h8, UINT8 src, UINT8 dst);
static void h8_band8(h83xx_state *h8, UINT8 src, UINT8 dst);
static INT16 h8_mulxs8(h83xx_state *h8, INT8 src, INT8 dst);
static INT32 h8_mulxs16(h83xx_state *h8, INT16 src, INT16 dst);
@ -2143,8 +2144,12 @@ static void h8_group7(h83xx_state *h8, UINT16 opcode)
switch((opcode>>8)&0x7)
{
case 0: udata8 = h8_bset8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8); H8_IFETCH_TIMING(1); break;
case 1: udata8 = h8_bnot8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8); H8_IFETCH_TIMING(1); break;
case 2: udata8 = h8_bclr8(h8, bitnr, udata8); h8_setreg8(h8, dstreg, udata8);H8_IFETCH_TIMING(1);break;
case 3: h8_btst8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break;
case 4: h8_bor8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break;
case 5: h8_bxor8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break;
case 6: h8_band8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break;
case 7: h8_bld8(h8, bitnr, udata8); H8_IFETCH_TIMING(1); break;
default:
logerror("H8/3xx: Unk. group 7 0-7 def %x\n", opcode);
@ -3055,21 +3060,26 @@ static UINT8 h8_bset8(h83xx_state *h8, UINT8 src, UINT8 dst)
// does not affect result, res in C flag only
static void h8_bor8(h83xx_state *h8, UINT8 src, UINT8 dst)
{
// pass
UINT8 res;
res = dst & (1<<src);
h8->h8cflag |= res ? 1 : 0;
dst >>= src;
dst &= 0x1;
h8->h8cflag |= dst;
}
#ifdef UNUSED_FUNCTION
// does not affect result, res in C flag only
static void h8_band8(h83xx_state *h8, UINT8 src, UINT8 dst)
{
dst >>= src;
dst &= 0x1;
h8->h8cflag &= dst;
}
// does not affect result, res in C flag only
static void h8_bxor8(h83xx_state *h8, UINT8 src, UINT8 dst)
{
dst >>= src;
dst &= 0x1;
h8->h8cflag ^= dst;
}
#endif
static UINT8 h8_bclr8(h83xx_state *h8, UINT8 src, UINT8 dst)
{

29
src/emu/cpu/h83002/h8priv.h
View File

@ -17,8 +17,8 @@ typedef struct
typedef struct
{
emu_timer *timer;
H8S2XXX_TPU_ITEM item[8];
int prescaler, tgrmax, tgrcur;
int cycles_per_tick;
UINT64 timer_cycles;
} H8S2XXX_TPU;
typedef struct
@ -30,6 +30,8 @@ typedef struct
typedef struct
{
emu_timer *timer;
int cycles_per_tick;
UINT64 timer_cycles;
} H8S2XXX_TMR;
typedef struct _h83xx_state h83xx_state;
@ -68,7 +70,7 @@ struct _h83xx_state
emu_timer *frctimer;
H8S2XXX_TMR tmr[2];
H8S2XXX_TPU tpu[3];
H8S2XXX_TPU tpu[6];
H8S2XXX_SCI sci[3];
int mode_8bit;
@ -110,11 +112,20 @@ UINT8 h8_3007_itu_read8(h83xx_state *h8, UINT8 reg);
void h8_itu_write8(h83xx_state *h8, UINT8 reg, UINT8 val);
void h8_3007_itu_write8(h83xx_state *h8, UINT8 reg, UINT8 val);
READ8_HANDLER( h8s2241_per_regs_r_byte );
WRITE8_HANDLER( h8s2241_per_regs_w_byte );
READ8_HANDLER( h8s2246_per_regs_r_byte );
WRITE8_HANDLER( h8s2246_per_regs_w_byte );
READ8_HANDLER( h8s2323_per_regs_r_byte );
WRITE8_HANDLER( h8s2323_per_regs_w_byte );
UINT8 h8s2241_per_regs_read_8(h83xx_state *h8, int offset);
UINT8 h8s2246_per_regs_read_8(h83xx_state *h8, int offset);
UINT8 h8s2323_per_regs_read_8(h83xx_state *h8, int offset);
UINT16 h8s2241_per_regs_read_16(h83xx_state *h8, int offset);
UINT16 h8s2246_per_regs_read_16(h83xx_state *h8, int offset);
UINT16 h8s2323_per_regs_read_16(h83xx_state *h8, int offset);
void h8s2241_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
void h8s2246_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
void h8s2323_per_regs_write_8(h83xx_state *h8, int offset, UINT8 data);
void h8s2241_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
void h8s2246_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
void h8s2323_per_regs_write_16(h83xx_state *h8, int offset, UINT16 data);
#endif /* __H8PRIV_H__ */

1461
src/emu/cpu/h83002/h8speriph.c
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