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sparc: SWAP/SWAPA on unaligned address causes a trap

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This commit is contained in:
hap 2021-12-04 18:52:55 +01:00
parent e86f00b5bb
commit bbd5057a2a
2 changed files with 46 additions and 44 deletions
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88
src/devices/cpu/sparc/sparc.cpp
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@ -3885,9 +3885,8 @@ inline void sparc_base_device::dispatch_instruction(uint32_t op)
case OP2_BICC: // branch on integer condition codes
execute_bicc(op);
break;
case OP2_SETHI: // sethi
*m_regs[RD] = op << 10;
m_r[0] = 0;
case OP2_SETHI: // sethi or nop
if (RDBITS) RDREG = op << 10;
PC = nPC;
nPC = nPC + 4;
break;
@ -4419,52 +4418,55 @@ void sparcv8_device::execute_swap(uint32_t op)
}
}
if (address & 3)
{
m_trap = 1;
m_mem_address_not_aligned = 1;
m_stashed_icount = m_icount;
m_icount = 0;
return;
}
uint32_t word = 0;
uint32_t temp = 0;
if (!m_trap)
uint32_t data = RDREG;
//while (m_pb_block_ldst_byte || m_pb_block_ldst_word)
//{
// { wait for lock(s) to be lifted }
// { an implementation actually need only block when another SWAP is pending on
// the same word in memory as the one addressed by this SWAP, or a LDSTUB is
// pending on any byte of the word in memory addressed by this SWAP }
//}
m_pb_block_ldst_word = 1;
word = read_word(addr_space, address);
if (MAE)
{
temp = RDREG;
while (m_pb_block_ldst_byte || m_pb_block_ldst_word)
{
// { wait for lock(s) to be lifted }
// { an implementation actually need only block when another SWAP is pending on
// the same word in memory as the one addressed by this SWAP, or a LDSTUB is
// pending on any byte of the word in memory addressed by this SWAP }
}
m_pb_block_ldst_word = 1;
word = read_word(addr_space, address);
if (MAE)
{
m_trap = 1;
m_data_access_exception = 1;
m_stashed_icount = m_icount;
m_icount = 0;
return;
}
m_trap = 1;
m_data_access_exception = 1;
m_stashed_icount = m_icount;
m_icount = 0;
return;
}
if (!m_trap)
write_word(addr_space, address, data);
m_pb_block_ldst_word = 0;
if (MAE)
{
write_word(addr_space, address, temp);
m_pb_block_ldst_word = 0;
if (MAE)
{
m_trap = 1;
m_data_access_exception = 1;
m_stashed_icount = m_icount;
m_icount = 0;
return;
}
else
{
if (RDBITS)
RDREG = word;
}
m_trap = 1;
m_data_access_exception = 1;
m_stashed_icount = m_icount;
m_icount = 0;
return;
}
if (RDBITS)
RDREG = word;
PC = nPC;
nPC = nPC + 4;
}

2
src/devices/cpu/sparc/sparcdefs.h
View File

@ -142,7 +142,7 @@
#define RDREG *m_regs[RD]
#define RS1REG *m_regs[RS1]
#define RS2REG *m_regs[RS2]
#define SET_RDREG(x) do { if(RD) { RDREG = (x); } } while (0)
#define SET_RDREG(x) do { if(RDBITS) { RDREG = (x); } } while (0)
#define ADDRESS (USEIMM ? (RS1REG + SIMM13) : (RS1REG + RS2REG))
#define PC m_pc