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heathkit/tlb.cpp: Added page 2 memory support for ultra19, and other minor fixes. (#11075)
Cleaned up comments in heathkit/h19.cpp
This commit is contained in:
Mark Garlanger
GitHub
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commit
bbe5e9f379
@ -2,24 +2,10 @@
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// copyright-holders:Mark Garlanger
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/***************************************************************************
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Heathkit H19
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Heathkit H19
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A smart terminal designed and manufactured by Heath Company.
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The keyboard consists of a 9x10 matrix connected to a MM5740AAC/N
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mask-programmed keyboard controller. The output of this passes
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through a rom.
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Input can also come from the serial port (a 8250).
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Either device will signal an interrupt to the CPU when a key
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is pressed/data is received.
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TODO:
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- speed up emulation
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- update SW401 baud rate options for Watz ROM
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- update SW401 & SW402 definitions for Super-19 ROM
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- update SW401 & SW402 definitions for ULTRA ROM
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- add option for ULTRA ROMs second page of screen RAM
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A smart terminal designed and manufactured by Heath Company. This
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is identical to the Zenith Data Systems Z-19.
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****************************************************************************/
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@ -69,7 +55,7 @@ void h19_state::h19_ultrah19(machine_config &config)
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HEATH_ULTRA(config, m_tlb);
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}
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/* ROM definition */
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// ROM definition
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ROM_START( h19 )
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ROM_END
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@ -2,52 +2,49 @@
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// copyright-holders:Mark Garlanger
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/***************************************************************************
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Heathkit Terminal Logic Board (TLB)
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Heathkit Terminal Logic Board (TLB)
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The board used in the H19 smart terminal designed and manufactured
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by Heath Company. (and identical Z19 sold by Zenith Data Systems)
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The board used in the H19 smart terminal designed and manufactured
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by Heath Company. (and the identical Z19 sold by Zenith Data Systems)
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This board is also used the Heath's H89 / H88, and ZDS's Z-89 and Z-90.
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The keyboard consists of a 9x10 matrix connected to a MM5740AAC/N
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mask-programmed keyboard controller. The output of this passes
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through a rom.
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The keyboard consists of a 9x10 matrix connected to a MM5740AAC/N
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mask-programmed keyboard controller. The output of this passes
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through a rom.
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Input can also come from the serial port (a 8250).
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Either device will signal an interrupt to the CPU when a key
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is pressed/data is received.
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Input can also come from the serial port (a 8250).
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Either device will signal an interrupt to the CPU when a key
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is pressed/data is received.
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TODO:
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- speed up emulation
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- update SW401 baud rate options for Watz ROM
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- update SW401 & SW402 definitions for Super-19 ROM
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- update SW401 & SW402 definitions for ULTRA ROM
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- add option for ULTRA ROMs second page of screen RAM
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TODO:
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- determine why ULTRA ROM's self-diag (ESC |) fails for the ROM and
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scratchpad memory
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****************************************************************************/
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/***************************************************************************
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Memory Layout
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The U435 three-to-eight line decoder uses A14 and A15 to generate three memory addresses:
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Memory Layout
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1. Program ROM 0x0000
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The U435 three-to-eight line decoder uses A14 and A15 to generate three memory addresses:
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2. Scratchpad RAM 0x4000
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3. Display Memory 0xF800
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1. Program ROM 0x0000
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2. Scratchpad RAM 0x4000
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3. Display Memory 0xF800
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Port Layout
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Port Layout
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Only address lines A5, A6, A7 are used by the U442 three-to-eight line decoder
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Only address lines A5, A6, A7 are used by the U442 three-to-eight line decoder
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Address Description
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----------------------------------------------------
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0x00 Power-up configuration (primary - SW401)
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0x20 Power-up configuration (secondary - SW402)
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0x40 ACE (communications)
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0x60 CRT controller
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0x80 Keyboard encoder
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0xA0 Keyboard status
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0xC0 Key click enable
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0xE0 Bell enable
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Address Description
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----------------------------------------------------
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0x00 Power-up configuration (primary - SW401)
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0x20 Power-up configuration (secondary - SW402)
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0x40 ACE (communications)
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0x60 CRT controller
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0x80 Keyboard encoder
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0xA0 Keyboard status
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0xC0 Key click enable
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0xE0 Bell enable
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****************************************************************************/
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@ -55,17 +52,20 @@ Address Description
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#include "tlb.h"
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// Standard H19 used a 2.048 MHz clock
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#define H19_CLOCK (XTAL(12'288'000) / 6)
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#define MC6845_CLOCK (XTAL(12'288'000) /8)
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#define INS8250_CLOCK (XTAL(12'288'000) /4)
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// Clocks
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static constexpr XTAL MASTER_CLOCK = XTAL(12'288'000);
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// Capacitor value in pF
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#define H19_KEY_DEBOUNCE_CAPACITOR 5000
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#define MM5740_CLOCK (mm5740_device::calc_effective_clock_key_debounce(H19_KEY_DEBOUNCE_CAPACITOR))
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// Standard H19 used a 2.048 MHz clock
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static constexpr XTAL H19_CLOCK = MASTER_CLOCK / 6;
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static constexpr XTAL MC6845_CLOCK = MASTER_CLOCK / 8;
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static constexpr XTAL INS8250_CLOCK = MASTER_CLOCK / 4;
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// Beep Frequency is 1 KHz
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#define H19_BEEP_FRQ (H19_CLOCK / 2048)
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static constexpr XTAL H19_BEEP_FRQ = (H19_CLOCK / 2048);
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// Capacitor value in pF
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static constexpr uint32_t H19_KEY_DEBOUNCE_CAPACITOR = 5000;
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#define MM5740_CLOCK (mm5740_device::calc_effective_clock_key_debounce(H19_KEY_DEBOUNCE_CAPACITOR))
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DEFINE_DEVICE_TYPE(HEATH_TLB, heath_tlb_device, "heath_tlb", "Heath Terminal Logic Board");
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DEFINE_DEVICE_TYPE(HEATH_SUPER19, heath_super19_tlb_device, "heath_super19_tlb", "Heath Terminal Logic Board w/Super19 ROM");
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@ -79,9 +79,9 @@ heath_tlb_device::heath_tlb_device(const machine_config &mconfig, const char *ta
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heath_tlb_device::heath_tlb_device(const machine_config &mconfig, device_type type, const char *tag, device_t *owner, uint32_t clock) :
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device_t(mconfig, type, tag, owner, clock),
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m_maincpu(*this, "maincpu"),
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m_write_sd(*this),
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m_palette(*this, "palette"),
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m_maincpu(*this, "maincpu"),
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m_crtc(*this, "crtc"),
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m_ace(*this, "ins8250"),
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m_beep(*this, "beeper"),
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@ -118,8 +118,8 @@ TIMER_CALLBACK_MEMBER(heath_tlb_device::bell_off)
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void heath_tlb_device::mem_map(address_map &map)
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{
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map.unmap_value_high();
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map(0x0000, 0x1fff).mirror(0x2000).rom();
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map(0x4000, 0x4100).mirror(0x3e00).ram();
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map(0x0000, 0x0fff).mirror(0x3000).rom();
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map(0x4000, 0x40ff).mirror(0x3f00).ram();
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map(0xc000, 0xc7ff).mirror(0x3800).ram().share(m_p_videoram);
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}
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@ -192,19 +192,19 @@ void heath_tlb_device::bell_w(uint8_t data)
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/***************************************************************************
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MM5740 B Mapping to the ROM address
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MM5740 B Mapping to the ROM address
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B1 -> A0 A10 = 0
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B2 -> A1 A9 = 0
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B3 -> A2 A8 = B8
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B4 -> A3 A7 = B7
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B5 -> A4 A6 = B9
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B6 -> A5 A5 = B6
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B7 -> A7 A4 = B5
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B8 -> A8 A3 = B4
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B9 -> A6 A2 = B3
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ground -> A9 A1 = B2
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ground -> A10 A0 = B1
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B1 -> A0 A10 = 0
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B2 -> A1 A9 = 0
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B3 -> A2 A8 = B8
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B4 -> A3 A7 = B7
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B5 -> A4 A6 = B9
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B6 -> A5 A5 = B6
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B7 -> A7 A4 = B5
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B8 -> A8 A3 = B4
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B9 -> A6 A2 = B3
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ground -> A9 A1 = B2
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ground -> A10 A0 = B1
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****************************************************************************/
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uint16_t heath_tlb_device::translate_mm5740_b(uint16_t b)
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@ -319,18 +319,18 @@ static GFXDECODE_START(gfx_h19)
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GFXDECODE_END
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/* Input ports */
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// Input ports
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static INPUT_PORTS_START( tlb )
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PORT_START("MODIFIERS")
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// bit 0 connects to B8 of MM5740 - low if either shift key is
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// bit 7 is low if a key is pressed
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// bit 0 - 0x001 connects to B8 of MM5740 - low if either shift key is
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PORT_BIT(0x002, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CapsLock") PORT_CODE(KEYCODE_CAPSLOCK) PORT_TOGGLE
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PORT_BIT(0x004, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Break") PORT_CODE(KEYCODE_PAUSE)
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PORT_BIT(0x008, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("OffLine") PORT_CODE(KEYCODE_F12) PORT_TOGGLE
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PORT_BIT(0x010, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("CTRL") PORT_CODE(KEYCODE_LCONTROL) PORT_CHAR(UCHAR_MAMEKEY(LCONTROL))
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PORT_BIT(0x020, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("LeftShift") PORT_CODE(KEYCODE_LSHIFT) PORT_CHAR(UCHAR_SHIFT_1)
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PORT_BIT(0x040, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Repeat") PORT_CODE(KEYCODE_LALT)
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// bit 7 - 0x080 is low if a key is pressed
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PORT_BIT(0x100, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("RightShift") PORT_CODE(KEYCODE_RSHIFT)
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PORT_BIT(0x200, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Reset") PORT_CODE(KEYCODE_F10)
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@ -428,7 +428,7 @@ static INPUT_PORTS_START( tlb )
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PORT_BIT(0x040, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("U") PORT_CODE(KEYCODE_U) PORT_CHAR('u') PORT_CHAR('U')
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PORT_BIT(0x080, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("I") PORT_CODE(KEYCODE_I) PORT_CHAR('i') PORT_CHAR('I')
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PORT_BIT(0x100, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("O") PORT_CODE(KEYCODE_O) PORT_CHAR('o') PORT_CHAR('O')
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PORT_BIT(0x200, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Tab") PORT_CODE(KEYCODE_TAB) PORT_CHAR(9)
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PORT_BIT(0x200, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Tab") PORT_CODE(KEYCODE_TAB) PORT_CHAR(UCHAR_MAMEKEY(TAB))
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PORT_START("X9")
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PORT_BIT(0x001, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("1 !") PORT_CODE(KEYCODE_1) PORT_CHAR('1') PORT_CHAR('!')
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@ -440,7 +440,7 @@ static INPUT_PORTS_START( tlb )
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PORT_BIT(0x040, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("7 &") PORT_CODE(KEYCODE_7) PORT_CHAR('7') PORT_CHAR('&')
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PORT_BIT(0x080, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("8 *") PORT_CODE(KEYCODE_8) PORT_CHAR('8') PORT_CHAR('*')
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PORT_BIT(0x100, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("9 (") PORT_CODE(KEYCODE_9) PORT_CHAR('9') PORT_CHAR('(')
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PORT_BIT(0x200, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Esc") PORT_CODE(KEYCODE_ESC) PORT_CHAR(27)
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PORT_BIT(0x200, IP_ACTIVE_LOW, IPT_KEYBOARD) PORT_NAME("Esc") PORT_CODE(KEYCODE_ESC) PORT_CHAR(UCHAR_MAMEKEY(ESC))
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PORT_START("SW401")
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PORT_DIPNAME( 0x0f, 0x0c, "Baud Rate") PORT_DIPLOCATION("SW401:1,2,3,4")
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@ -469,7 +469,7 @@ static INPUT_PORTS_START( tlb )
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PORT_DIPSETTING( 0x00, "Half")
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PORT_DIPSETTING( 0x80, "Full")
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PORT_START("SW402") // stored at 40C8
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PORT_START("SW402")
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PORT_DIPNAME( 0x01, 0x00, "Cursor") PORT_DIPLOCATION("SW402:1")
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PORT_DIPSETTING( 0x00, "Underline")
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PORT_DIPSETTING( 0x01, "Block")
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@ -492,8 +492,8 @@ static INPUT_PORTS_START( tlb )
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PORT_DIPSETTING( 0x00, DEF_STR(No))
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PORT_DIPSETTING( 0x40, DEF_STR(Yes))
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PORT_DIPNAME( 0x80, 0x00, "Refresh") PORT_DIPLOCATION("SW402:8")
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PORT_DIPSETTING( 0x00, "50Hz")
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PORT_DIPSETTING( 0x80, "60Hz")
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PORT_DIPSETTING( 0x00, "60Hz")
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PORT_DIPSETTING( 0x80, "50Hz")
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INPUT_PORTS_END
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@ -660,7 +660,7 @@ WRITE_LINE_MEMBER(heath_tlb_device::cb1_w)
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void heath_tlb_device::device_add_mconfig(machine_config &config)
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{
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// basic machine hardware
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Z80(config, m_maincpu, H19_CLOCK); // From schematics
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Z80(config, m_maincpu, H19_CLOCK);
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m_maincpu->set_addrmap(AS_PROGRAM, &heath_tlb_device::mem_map);
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m_maincpu->set_addrmap(AS_IO, &heath_tlb_device::io_map);
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@ -740,6 +740,24 @@ heath_ultra_tlb_device::heath_ultra_tlb_device(const machine_config &mconfig, co
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{
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}
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void heath_ultra_tlb_device::device_add_mconfig(machine_config &config)
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{
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heath_tlb_device::device_add_mconfig(config);
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m_maincpu->set_addrmap(AS_PROGRAM, &heath_ultra_tlb_device::mem_map);
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}
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void heath_ultra_tlb_device::mem_map(address_map &map)
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{
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map.unmap_value_high();
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map(0x0000, 0x0fff).mirror(0x2000).rom();
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// Page 2 memory
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map(0x1000, 0x1fff).mirror(0x2000).ram();
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map(0x4000, 0x40ff).mirror(0x3f00).ram();
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map(0xc000, 0xc7ff).mirror(0x3800).ram().share("videoram");
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}
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const tiny_rom_entry *heath_ultra_tlb_device::device_rom_region() const
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{
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return ROM_NAME(ultra19);
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@ -2,7 +2,7 @@
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// copyright-holders:Mark Garlanger
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/***************************************************************************
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Heathkit Terminal Logic Board (TLB)
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Heathkit Terminal Logic Board (TLB)
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****************************************************************************/
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@ -39,11 +39,13 @@ protected:
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virtual void device_add_mconfig(machine_config &config) override;
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virtual void device_resolve_objects() override;
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private:
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void mem_map(address_map &map);
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void io_map(address_map &map);
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required_device<cpu_device> m_maincpu;
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private:
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void key_click_w(uint8_t data);
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void bell_w(uint8_t data);
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uint8_t kbd_key_r();
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@ -69,7 +71,6 @@ private:
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devcb_write_line m_write_sd;
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required_device<palette_device> m_palette;
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required_device<cpu_device> m_maincpu;
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required_device<mc6845_device> m_crtc;
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required_device<ins8250_device> m_ace;
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required_device<beep_device> m_beep;
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@ -114,6 +115,9 @@ public:
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protected:
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virtual const tiny_rom_entry *device_rom_region() const override;
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virtual ioport_constructor device_input_ports() const override;
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virtual void device_add_mconfig(machine_config &config) override;
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void mem_map(address_map &map);
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};
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DECLARE_DEVICE_TYPE(HEATH_TLB, heath_tlb_device)
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